81
P4C1981/1981L, P4C1982/1982L
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
10/12/15/20/25 ns (Commercial)
12/15/20/25/35 ns (Industrial)
15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
715 mW Active 12/15
550/660 mW Active 20/25/35/45
193/220 mW Standby (TTL Input)
83/110 mW Standby (CMOS Input) P4C1981/1981L
5.5 mW Standby (CMOS Input)
P4C1981L/82L (Military)
Output Enable and Dual Chip Enable Functions
5V
10% Power Supply
Data Retention with 2.0V Supply, 10
A Typical
Current (P4C1981L/1982L (Military)
Separate Inputs and Outputs
P4C1981/L Input Data at Outputs during Write
P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
28-Pin 300 mil DIP, SOJ
28-Pin 350 x 550 mil LCC
1Q97
Means Quality, Service and Speed
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when
OE
is low; the outputs of
the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V
10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is typically
10
A from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
DESCRIPTION
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby. For the P4C1982L and
P4C1981L, power is only 5.5 mW standby with CMOS
input levels. The P4C1981/L and P4C1982/L are mem-
bers of a family of PACE RAMTM products offering fast
access times.
The P4C1981/L and P4C1982/L are available in 28-pin
300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC
packages providing excellent board level densities.
DIP (P5, D5-2), SOJ (J5)
TOP VIEW
LCC (L5)
TOP VIEW
P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
A
0
A
3
A
4
A
5
A
6
A
7
A
8
I
1
O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A12
CE
1
I
GND
A13
A11
V
CC
2
O3
O2
O1
WE
CE
2
A
1
A
2
OE
A10
A9
I4
I3
P4C1981/ 1982
A
INPUT
DATA
CONTROL
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
A
A
A
(8)
(6)
I
1
I
2
I
3
I
4
COLUMN
SELECT
P4C1982
P4C1981
CE
2
O
1
O
2
O
3
O
4
WE
CE
1
OE
A
2
A3
A5
A6
A7
A8
I1
I2
O4
A12
A11
A10
A9
GN
D
A
0
A
1
V
CC
26
25
24
23
22
21
20
4
5
6
7
8
9
10
11
12
19
18
13
17
3
27
1
15
2
14
28
16
CE
1
I3
I4
O3
O2
A
13
OE
CE
2
WE
O
1
A4
82
P4C1981/1981L, P4C1982/1982L
CE
1
,
CE
2
V
HC,
Mil.
V
CC
= Max., Ind./Com'l.
f = 0, Outputs Open
V
IN
V
LC
or V
IN
V
HC
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
1
,
CE
2
V
IH
, Mil.
V
CC
= Max., Ind./Com'l.
f = Max., Outputs Open
___
___
40
35
___
___
___
___
20
15
40
n/a
1.0
n/a
mA
mA
___
___
Standby Power Supply
Current
(CMOS Input Levels)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
5
7
Unit
pF
pF
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= Min., I
IN
= 18 mA
I
OL
= +8 mA, V
CC
= Min.
I
OH
= 4 mA, V
CC
= Min.
V
CC
= Max. Mil.
V
IN
= GND to V
CC
Com'l.
P4C1981 / 1982
Min
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
2.4
10
5
10
5
Max
V
CC
+0.5
0.8
V
CC
+0.5
0.2
1.2
0.4
+10
+5
+10
+5
P4C1981L / 82L
Min
Max
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
2.4
5
n/a
5
n/a
V
CC
+0.5
0.8
V
CC
+0.5
0.2
0.4
1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
A
A
Typ.
Industrial
Commercial
Grade(2)
Ambient
Temperature
GND
V
CC
40
C to +85
C
0
C to +70
C
0V
0V
5.0V
10%
5.0V
10%
0V
5.0V
10%
55
C to +125
C
Military
I
SB1
V
CC
= Max., Mil.
CE
1
,
CE
2
= V
IH
Ind./Com'l.
V
OUT
= GND to V
CC
83
P4C1981/1981L, P4C1982/1982L
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
,
CE
2
= V
IL
,
OE
= V
IH
I
CC
Symbol
Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Industrial
Military
10
N/A
12
15
20
25
35
45
Unit
N/A
mA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
150
155
160
170
180
N/A
170
160
155
150
145
180
170
160
155
150
N/A
N/A
DATA RETENTION CHARACTERISTICS (P4C1981L/P4C1982L Military Temperature Only)
Typ.*
Max
Symbol
Parameter
Test Condition
Min
V
CC
=
V
CC
=
Unit
2.0V
3.0V
2.0V
3.0V
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
10
15
600
900
A
t
CDR
Chip Deselect to
CE
1
or
CE
2
V
CC
0.2V,
0
ns
Data Retention Time
V
IN
V
CC
0.2V or
t
R
Operation Recovery Time
t
RC
ns
*
T
A
= +25
C
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
V
IN
0.2V
DATA RETENTION WAVEFORM
V
CC
DATA RETENTION WAVEFORM
V
IH
t
CDR
4.5V
V
DR
2V
4.5V
t
R
V
DR
V
IH
1348 07
DATA RETENTION MODE
CE
1 or
CE
2
84
P4C1981/1981L, P4C1982/1982L
Sym.
Parameter
Unit
-10
-12
-15
-20
-25
-35
-45
Min Max Min
Max
Min Max Min
Max Min Max Min
Max Min
Max
t
RC
Read Cycle Time
10
12
15
20
25
35
45
ns
t
AA
Address Access
10
12
15
20
25
35
45
ns
Time
t
AC
Chip Enable
10
12
15
20
25
35
45
ns
Access Time
t
OH
Output Hold from
2
2
2
2
2
2
2
ns
Address Change
t
LZ
Chip Enable to
2
2
2
2
2
2
2
ns
Output in Low Z
t
HZ
Chip Disable to
6
7
8
10
10
15
15
ns
Output in High Z
t
OE
Output Enable
6
7
8
12
15
21
27
ns
Low to Data Valid
t
OLZ
Output Enable to
2
2
2
2
2
2
2
ns
Output in Low Z
t
OHZ
Output Disable to
6
7
9
9
10
14
15
ns
Output in High Z
t
PU
Chip Enable to
0
0
0
0
0
0
0
ns
Power Up Time
t
PD
Chip Disable to
10
12
15
20
25
25
30
ns
Power Down Time
AC CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
READ CYCLE NO.1 (
OE
OE
OE
OE
OE
controlled)
(5)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(10)
t
AA
t
OE
t
OH
CE
1,
CE
2
t
LZ
t
AC
t
HZ
t
OHZ
t
(9)
(9)
(9)
(9)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
,
CE
2
and
OE
are LOW for READ Cycle.
7.
OE
is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with,
CE
1
, and
CE
2
transition LOW.
9. Transition is measured
200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
85
P4C1981/1981L, P4C1982/1982L
Note:
11. Transitions caused by a chip enable control have similar delays irrespective of whether
CE
1
or
CE
2
causes them.
t
CE
1,
CE
2
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
SUPPLY
CC
CURRENT
V
(9,11)
(9,11)
(11)
(11)
(11)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
1
,
CE
CE
CE
CE
CE
2
Controlled)
(5,7,8)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(10)
RC
1520 05
READ CYCLE NO. 2 (ADDRESS Controlled)
(5,6)
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