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ISP1240
1
Features
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64-bit PCI host bus interface, complaint with PCI
Local Bus Specification revision 2.1
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Compliance with ANSI Fast-20 standard
X3T10/1071D
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Compliance with ANSI X3T10/855D SCSI-3
parallel interface (SPI) standard
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Supports fast, wide, and Ultra (Fast-20) SCSI data
transfer rates
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Two concurrently operating wide, Ultra SCSI
channels
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Supports single-ended and differential SCSI
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SCSI initiator and target modes of operation
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Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
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Supports PCI dual-address cycle (64-bit
addressing)
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SCSI operations executed from start to finish
without host intervention
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Simultaneous, multiple logical threads
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Supports JTAG boundary scan
Product Description
The ISP1240 adds dual channel, Ultra SCSI support to
the expanding functionality of the ISP product family. The
ISP1240 is a single-chip, highly integrated, bus master,
dual-channel SCSI I/O processor for SCSI initiator and
target applications. This device interfaces the 64-bit PCI
bus to two Ultra SCSI buses and contains an onboard RISC
processor. The ISP1240 is a fully autonomous device,
capable of managing multiple I/O operations and
associated data transfers simultaneously on two SCSI
channels from start to finish without host intervention. The
ISP1240 is host-software compatible with the QLogic
single channel ISP1040, requiring only a minor
input/output control block (IOCB) change to select the
additional channel. The ISP1240 block diagram is
illustrated in figure 1.
Figure 1. ISP1240 Block Diagram
DMA BUS 0
SCSI ENGINES
PCI INTERFACE
HOST MEMORY
HOST SOFTWARE
DRIVER
REQUEST
QUEUE
RESPONSE
QUEUE
64-BIT
PCI
BUS
IOCBS
512-BYTE
FIFO
WCS AND
BUFFERS
SEQUENCERS
CTRL REGS
FIFO
WCS AND
BUFFERS
SEQUENCERS
CTRL REGS
DMA BUS 1
SXP 0
SXP 1
COMMAND FIFO
DMA
CONTROL
MAILBOX
REGISTERS
CTRL/CONFIG
REGISTERS
RISC
REGISTER
FILE
ALU
BOOT
CODE
MEMORY
INTERFACE
ULTRA WIDE
SCSI BUS 0
ULTRA WIDE
SCSI BUS 1
ISP1240
DATA FIFO
512-BYTE
DATA FIFO
128-BYTE
I/O BUS
DATA 16
ADDRESS 16
EXTERNAL
CODE/DATA
MEMORY
FLASH
BIOS
NVRAM
QLogic Corporation
ISP1240 Intelligent, Dual SCSI Processor
Data Sheet
2
ISP1240
83240-580-00 B
QLogic Corporation
ISP Initiator and Target Firmware
The ISP1240 firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery. The multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP1240 can switch between initiator and target modes.
Software Drivers
BIOS firmware is available for the ISP1240. Software
drivers are available for the following operating systems:
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AIX
s
I
2
O
s
DOS/Windows
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Novell NetWare
s
OS/2
s
SCO UNIX
s
UnixWare
s
Windows 95
s
Windows NT
Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP1240 incorporates a
high-speed, proprietary RISC processor; two intelligent
SCSI bus controllers (SCSI executive processor [SXP]);
and a host bus, three-channel, first-party DMA controller.
The SCSI bus controllers and the host bus DMA controller
operate independently and concurrently under the control
of the onboard RISC processor for maximum system
performance. The ISP1240 RISC interface requires
external program data memory.
The complete I/O subsystem solution using the
ISP1240 and associated supporting memory devices is
shown in figure 2.
Interfaces
The ISP1240 interfaces consist of the 64-bit PCI bus
interface, two SCSI interfaces, and the RISC interface. Pins
that support these interfaces and other chip operations are
shown in figure 3.
ISP1240
SCSI
16
SCSI
TARGETS
TARGET
TARGET
PCI
I/F
SCSI
I/F
RISC
CODE/DATA
MEMORY
PCI
HOST
MEMORY
IOCB
DATA
64
Figure 2. I/O Subsystem Design Using the ISP1240
P
C
I
B
U
S
SCSI
I/F
SCSI
16
SCSI
TARGETS
TARGET
TARGET
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ISP1240
3
QLogic Corporation
PCI Interface
The ISP1240 PCI interface supports the following:
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64-bit, intelligent bus master, burst DMA host
interface for fetching I/O control blocks and data
transfers
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64-bit host memory addressing (dual address cycle)
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Backward compatible to 32-bit PCI
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Three-channel DMA controller
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512-byte data DMA FIFO per channel and 128-byte
command DMA FIFO with threshold control
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16-bit slave mode for communication with host
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Pipelined DMA registers for efficient scatter/gather
operations
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32-bit DMA transfer counter for I/O transfer lengths
of up to four gigabytes
Figure 3. ISP1240 Functional Signal Grouping
IF
RISC
INTERFACE
VDD
VSS
POWER
AND GROUND
MISC
CONTROL
BSY
CD
DIFFM
DIFFS
EARB
EBSY
EIG
ERST
SCSI
INTERFACE
CHANNEL 0
AND
CHANNEL 1
ISP1240
ROE
ECS3-0
RADDR15-0
IOCS
ACK
ATN
IO
MSG
ESEL
REQ
RST
SD15-0
SDP1-0
SEL
ESD
TRIG
TSTOUT
ETG
RESET
CLK
RISCSTB
WE
SCSI
DIFFERENTIAL
INTERFACE
CHANNEL 0
AND
CHANNEL 1
RDATA15-0
TESTMODE2-0
RESET
NVDATI
NVCS
NVDATO
NVCLK
NVRAM
CONTROL
POD
BSYLED
GPIO3-0
RDPAR
FRAME
PCI BUS
INTERFACE
STOP
AD63-0
TRDY
DEVSEL
PERR
IDSEL
SERR
IRDY
BREQ
CBE7-0
PAR, PAR64
INTA
BCLK
BGNT
ACK64
REQ64
IDENB
TDO
TDI
TMS
TCK
JTAG INTERFACE
TRST
FLASH BIOS
PDATA7-0
FLASHCS
FLASHOE
FLASHWR
EXTINT
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ISP1240
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QLogic Corporation
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Support for subsystem ID
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Support for flash BIOS PROM
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Support for PCI cache commands
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3.3V and 5.0V tolerant PCI I/O buffers
The ISP1240 is designed to interface directly to the PCI
bus and operate as a 64-bit, DMA bus master. This
operation is accomplished through a PCI bus interface unit
(PBIU) that contains an onboard DMA controller. The
PBIU generates and samples PCI control signals, generates
host memory addresses, and facilitates the transfer of data
between host memory and the onboard DMA FIFO. It also
allows the host to access the ISP1240 internal registers and
communicate with the onboard RISC processor through the
PCI target mode operation.
The ISP1240 onboard DMA controller consists of three
independent DMA channels that initiate transactions on the
PCI bus and transfer data between the host memory and
DMA FIFO. The three DMA channels consist of the
command DMA channel and two data DMA channels. The
command DMA channel is used mainly by the RISC
processor for small transfers such as fetching commands
from and writing status information to the host memory
over the PCI bus. The data DMA channels transfer data
between two SCSI buses and the PCI bus.
The PBIU internally arbitrates between the data DMA
channels and the command DMA channel and alternately
services them. Each DMA channel has a set of DMA
registers that are programmed for transfers by the RISC
processor.
SCSI Executive Processors
Each ISP1240 SXP supports the following:
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8- or 16-bit data transfers
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Ultra SCSI (Fast-20) synchronous data transfer
rates up to 40 Mbytes/sec
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Asynchronous SCSI data transfer rates up to
12 Mbytes/sec
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Programmable SCSI processor
Specialized instruction set with 16-bit
microword
384-bit by 16-bit internal RAM control store
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32-bit, configurable SCSI transfer counter
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Command, status, message in, and message out
buffers
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Device information storage area
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On-chip, single-ended SCSI transceivers (48-mA
drivers)
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Programmable active negation
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
RISC Processor
The ISP1240 RISC processor supports the following:
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Execution of multiple I/O control blocks from the
host memory
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Reduced host intervention and interrupt overhead
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One interrupt or less per I/O operation
The onboard RISC processor enables the ISP1240 to
handle complete I/O transactions with no intervention from
the host. The ISP1240 RISC processor controls the chip
interfaces; executes simultaneous, multiple input/output
control blocks (IOCB) for both SCSI channels; and
maintains the required thread information for each transfer.
Packaging
The ISP1240 is available in a 352-pin thermally
enhanced ball grid array (TE BGA) package.
AIX is a trademark of IBM Corporation.
DOS, OS/2, Windows NT, and Windows 95 are trademarks or registered trademarks of Microsoft Corp.
Novell and NetWare are registered trademarks of Novell, Inc.
SCO UNIX is a registered trademark of Santa Cruz Operations.
UNIX is a trademark of AT&T Bell Laboratories.
All other brand and product names are trademarks or registered trademarks of their respective holders.
July 29, 1997 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
Specifications are subject to change without notice.
QLogic is a trademark of QLogic Corporation.
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