83220-580-01 D
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S i m p l i f y
The ISP2200A is a single-chip, highly integrated,
bus master, Fibre Channel processor that targets
storage, clustering, and networking applications. This
chip connects the PCI bus to a Fibre Channel loop or
to a point-to-point Fibre Channel port.
The ISP2200A/33 is pin compatible with the
ISP2100A/33. The ISP2200A/66 is pin compatible
with the ISP2100A/66.
The ISP2200A is a fully autonomous device,
capable of managing multiple I/O operations and
associated data transfers from start to finish without
host intervention.
The ISP2200A balances the advanced bus
speeds and efficiency of PCI with exceptional 1-Gb
Fibre Channel performance. Fibre Channel support
for SCSI and VI allows the ISP2200A to target a wide
spectrum of storage and system area networks
(SANs).
Features
s
Available in two speed grades (collectively
referred to as ISP2200A):
66-MHz, 64-bit PCI host bus interface
(ISP2200A/66)
33-MHz, 64-bit PCI host bus interface
(ISP2200A/33)
s
Compliance with PCI Local Bus Specification
revision 2.2
s
Supports full-duplex communications in all
Fibre Channel topologies
s
Compliance with ANSI SCSI standards for
class 2 and class 3 service:
Fibre Channel Arbitrated Loop (FC-AL-2)
working draft, rev 6.4, August 28, 1998
Fibre Channel Fabric Loop Attachment
(FC-FLA) working draft, rev 2.7, August 12,
1997
Fibre Channel Private Loop SCSI Direct
Attach (FC-PLDA) working draft, rev 2.1,
September 22, 1997
Fibre Channel Tape (FC-TAPE) profile,
T11/98-124vD, rev 1.13, February 3, 1999
s
Supports Fibre Channel protocol SCSI
(FCP-SCSI) and Fibre Channel IP protocols
s
Compliance with PCI Bus Power Management
Interface Specification Revision 1.0 (PC98)
s
Supports up to 200 MBps sustained Fibre
Channel data transfer rate
s
Supports SCSI initiator, initiator/target, and
target modes
s
Onboard, enhanced RISC processor
s
Onboard gigabit serial transceivers
s
Supports PCI dual-address cycle and cache
commands
s
No host intervention required to execute
complete SCSI and IP operations
s
Supports multi-ID aliasing in target mode
s
Supports external frame buffering for
performance scalability over long distances
Subsystem Organization
To maximize I/O throughput and improve host and
Fibre Channel utilization, the ISP2200A incorporates
a high-speed, proprietary RISC processor; a Fibre
Channel protocol manager (FPM); integrated frame
buffer memory; and a host bus, three-channel, bus
master DMA controller. The FPM and host bus DMA
controller operate independently and concurrently
under the control of the onboard RISC processor for
maximum system performance.
ISP2200A/33 and ISP2200A/66 Data Sheet
1-Gb Fibre Channel to 66-MHz PCI Controller
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83220-580-01 D
The complete I/O subsystem solution using the
ISP2200A and directly connected hard drives is
shown in
figure 1
.
Figure 1. I/O Subsystem Design Using the ISP2200A
PCI Interface
The ISP2200A PCI interface supports the
following:
s
33-MHz (ISP2200A/33) or 66-MHz
(ISP2200A/66), 64-bit, intelligent bus master
interface
s
64-bit host memory addressing (dual address
cycle)
s
Backward compatible to 32-bit PCI
s
Three-channel DMA controller
s
16-bit PCI target mode for communication with
host
s
Pipelined DMA registers for efficient
scatter/gather operations
s
32-bit DMA transfer counter for I/O transfer
length of up to four gigabytes
s
Support for PCI cache commands
s
Support for flash BIOS PROM
s
Support for subsystem ID
s
3.3V and 5.0V tolerant PCI I/O buffers
s
Support for PCI power management
The ISP2200A is designed to interface directly to
the PCI bus and operate as a 64-bit DMA bus master.
This function is accomplished through a PCI bus
interface unit (PBIU) containing an onboard DMA
controller. The PBIU generates and samples PCI
control signals, generates host memory addresses,
and facilitates the transfer of data between host
memory and the onboard frame buffer. It also allows
the host to access the ISP2200A internal registers
and communicate with the onboard RISC processor.
The ISP2200A onboard DMA controller consists
of three independent DMA channels that initiate
transactions on the PCI bus and transfer data
between the host memory and the frame buffer or
RISC RAM.
The PBIU internally arbitrates between the DMA
channels and alternately services them. Each DMA
channel has a set of DMA registers that are
programmed for transfers by the RISC processor.
Fibre Channel Interface
The ISP2200A provides onboard gigabit
transceivers for direct connection to the Fibre
Channel ports on copper media. A standard 10-bit
interface is also provided to connect to external
transceivers, if desired.
Fibre Channel Protocol Manager
The ISP2200A FPM supports the following:
s
Support for one Fibre Channel port
s
Gigabit serial interface
s
Full-duplex data transfer rate up to 200 MBps
s
10-bit interface to external transceivers
s
Integrated frame buffer that supports up to
2112-byte frame payload
RESPONSE
QUEUE
ISP2200A
PCI
INTERFACE
FIBRE
CHANNEL
INTERFACE
RISC
PCI
64
16
HOST
SOFTWARE
DRIVER
REQUEST
QUEUE
IOCBs
HOST MEMORY
P
C
I
B
U
S
EXTERNAL
CODE/DATA MEMORY
FIBRE CHANNEL
SERVER/STORAGE
AREA NETWORK (SAN)
STORAGE SUBSYSTEM
SERVER
TAPE LIBRARY
83220-580-01 D
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s
8b/10b encoder and decoder with clock skew
management
s
Support for an external buffer
The FPM transmits and receives at the full Fibre
Channel rate of 106.25 MBps. The on-chip frame
buffer includes separate areas for received data and
transmit data, as well as areas for managing special
frames such as command and response. The FPM
receive path validates and routes frames received
from the Fibre Channel to the appropriate area in the
frame buffer. The transmit path transmits frames from
the frame buffer to the Fibre Channel. The FPM
automatically handles frame delimiters and frame
control.
The external buffer supports additional receive
buffering for 10-km optical Fibre Channel links to
eliminate dead time and allow a remote transmitter to
send frames continuously. Enough initial buffer credit
can then be issued by the ISP2200A to keep a remote
transmitter busy until it sees an R_RDY return.
RISC Processor
The ISP2200A RISC processor supports the
following:
s
Execution of multiple I/O control blocks from
the host memory
s
Reduced host intervention and interrupt
overhead
s
One interrupt or less per I/O operation
One of the major features of the ISP2200A is its
ability to handle complete I/O transactions from start
to finish with no intervention from the host. This high
level of integration is accomplished with the onboard
RISC processor. The ISP2200A RISC processor
controls the chip interfaces; executes simultaneous,
multiple IOCBs; and maintains the required thread
information for each transfer.
ISP Initiator/Target SCSI and IP
Firmware
The ISP2200A firmware implements a
multitasking host adapter that provides the host
system with IP communications and complete SCSI
command and data transport capabilities, thus freeing
the host system from the simultaneous execution of
SCSI and IP traffic. The firmware provides two
interfaces to the host system: the command interface
and the Fibre Channel transport interface. The
single-threaded command interface facilitates
debugging, configuration, and recovering errors. The
multithreaded transport interface maximizes use of
the Fibre Channel and host buses.
The ISP2200A can operate simultaneously in
SCSI initiator and target modes, and supports SCSI
and IP protocols concurrently.
Software Drivers
The ISP2200A supports a host software interface
similar to the QLogic parallel SCSI and FC-AL
processor family. Existing ISP2100A software drivers
for all major operating systems are easily modified to
support the ISP2200A. The ISP2200A also supports
FCP-SCSI and IP software drivers for most major
operating systems.
Packaging
The ISP2200A/33 and the ISP2200A/66 are
available in a 256-pin ball grid array (BGA) package.
The ISP2200A/33 is pin compatible with the
ISP2100A/33. The ISP2200A/66 is pin compatible
with the ISP2100A/66.
20012002 QLogic Corporation. All rights reserved worldwide.
QLogic is a trademark of QLogic Corporation.
All other brand and product names are trademarks or registered trademarks of their respective owners.
QLogic Corporation, 26600 Laguna Hills Drive, Aliso Viejo, CA 92656, (800) 662-4471 or (949) 389-6000
Specifications are subject to change without notice.
April 25, 2002
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