QL2007
3.3V and 5.0V pASIC
2 FPGA
Combining Speed, Density, Low Cost and Flexibility
3-25
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os
-3-layer metal ViaLink
process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
... 7,000
usable ASICgates,
174 I/O pins
480
Logic
Cells
pAS
I
C 2
3
QL2007
Block Diagram
Rev. E
pASIC 2
HIGHLIGHTS
QL2007
3-26
The QL2007 is a 7,000 usable ASIC gate, 11,000 usable PLD gate member
of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique
combination of architecture, technology, and software tools to provide high
speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high
performance silicon solution for designs described using HDLs such as
Verilog and VHDL, as well as schematics.
The QL2007 contains 480 logic cells. With 174 maximum I/Os, the
QL2007 is available in 84-pin PLCC, 144-pin TQFP, and 208-pin PQFP
packages.
Software support for the complete pASIC families, including the QL2007, is
available through three basic packages. The turnkey QuickWorks
package
provides the most complete FPGA software solution from design entry to
logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickTools
TM
and QuickChip
TM
packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
Total of 174 I/O Pins
- 166 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin,
or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
PRODUCT
SUMMARY
FEATURES
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