2002 QuickLogic Corporation
www.quicklogic.com
1
Device Highlights
High Performance & High Density
60,000 Usable PLD Gates with 316 I/Os
300 MHz 16-bit Counters,
400 MHz Datapaths
0.35
m four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 316 I/O Pins
308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Eight high-drive input/distributed
network pins
Eight Low-Skew Distributed
Networks
Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs -- each driven by an input-only pin
Six global clock/control networks available
to the logic cell F1, clock set, and reset
inputs and the input and I/O register clock,
reset, and enable inputs as well as the output
enable control -- each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
Figure 1: 1,584 pASIC 3 Logic Cells
QL3060 pASIC 3 FPGA Data Sheet
60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
2
www.quicklogic.com
2002 QuickLogic Corporation
QL3060 pASIC 3 FPGA Data Sheet Rev D
Architecture Overview
The QL3060 is a 60,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC
3 FPGAs are fabricated on a 0.35
m four-layer metal process using QuickLogic
's patented
ViaLink
technology to provide a unique combination of high performance, high density,
low cost, and extreme ease-of-use.
The QL3060 contains 1,584 logic cells. With a maximum of 316 I/Os, the QL3060 is
available in 208-PQFP and 456-pin PBGA packages.
Software support for the complete pASIC 3 family, including the QL3060, is available
through three basic packages. The turnkey QuickWorks
package provides the most
complete FPGA software solution from design entry to logic synthesis, to place and route,
to simulation. The QuickTools
TM
for Workstations package provides a solution for designers
who use Cadence
, Exemplar
TM
, Mentor
, Synopsys
, Synplicity
, Viewlogic
TM
, Aldec
TM
,
or other third-party tools for design entry, synthesis, or simulation.
2002 QuickLogic Corporation
www.quicklogic.com
3
QL3060 pASIC 3 FPGA Data Sheet Rev D
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25
C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 7
by the numbers provided
in
Table 1
through
Table 5
.
Table 1: Logic Cells
Symbol
Parameter
Propagation Delays (ns) Fanout
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7
.
1
2
3
4
8
t
PD
Combinatorial Delay
b
b. These limits are derived from a representative selection of the slowest paths through the pASIC
3 logic cell including typical net delays. Worst case delay values for specific paths should be de-
termined from timing analysis of your particular design.
1.4
1.7
1.9
2.2
3.2
t
SU
Setup Time
b
1.7
1.7
1.7
1.7
1.7
t
H
Hold Time
0.0
0.0
0.0
0.0
0.0
t
CLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
t
CWHI
Clock High Time
1.2
1.2
1.2
1.2
1.2
t
CWLO
Clock Low Time
1.2
1.2
1.2
1.2
1.2
t
SET
Set Delay
1.0
1.3
1.5
1.8
2.8
t
RESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
t
SW
Set Width
1.9
1.9
1.9
1.9
1.9
t
RW
Reset Width
1.8
1.8
1.8
1.8
1.8
Table 2: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanout
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-
ture settings as specified in
Table 7
.
1
2
3
4
8
12
24
t
IN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
t
INI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
t
ISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
3.1
t
IH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
0.0
t
lCLK
Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
t
lRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
t
lESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
2.3
t
lEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
0.0
4
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2002 QuickLogic Corporation
QL3060 pASIC 3 FPGA Data Sheet Rev D
Table 3: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column
a
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-
bal clock has up to 11 loads per half column.
1
2
3
4
8
10
11
t
ACK
Array Clock Delay
1.2
1.2
1.3
1.3
1.5
1.6
1.7
t
GCKP
Global Clock Pin Delay
0.7
0.7
0.7
0.7
0.7
0.7
0.7
t
GCKB
Global Clock Buffer Delay
0.8
0.8
0.9
0.9
1.1
1.2
1.3
Table 4: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7
.
1
2
3
4
8
10
t
I/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
t
ISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
t
IH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
t
lOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
t
lORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
t
lESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
t
lEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
2002 QuickLogic Corporation
www.quicklogic.com
5
QL3060 pASIC 3 FPGA Data Sheet Rev D
Figure 2: Loads used for t
PXZ
Table 5: Output-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Output Load
Capacitance (pF)
30
50
75
100
150
t
OUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
t
OUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
t
PZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
t
PZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
t
PHZ
Output Delay High to Tri-State
a
a. The loads presented in
Figure 2
are used for t
PXZ
:
2.0
-
-
-
-
t
PLZ
Output Delay Low to Tri-State
1.2
-
-
-
-
1
1
t
PHZ
t
PLZ
5 pF
5 pF
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