2002 QuickLogic Corporation
www.quicklogic.com
1
Device Highlights
High Performance & High Density
16,000 Usable PLD Gates with 118 I/Os
300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
0.35
m four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
10 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
5 ns access times, each port independently
accessible
Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
Figure 1: QuickRAM Block Diagram
10
RAM
Blocks
320
High Speed
Logic Cells
Interface
QL4016 QuickRAM Data Sheet
16,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
2
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2002 QuickLogic Corporation
QL4016 QuickRAM Data Sheet Rev I
Architecture Overview
The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in
combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate
member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35
m
four-layer metal process using QuickLogic's patented ViaLink
TM
technology to provide a
unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QL4016 contains 320 logic cells and 10 Dual Port RAM modules (see
Figure 1
). Each
RAM module has 1,152 RAM bits, for a total of 11,520 bits. RAM Modules are Dual Port
(one read port, one write port) and can be configured into one of four modes:
64 (deep)
18 (wide), 128
9, 256
4, or 512
2 (see
Figure 4
). With a maximum of 82
I/Os, the QL4016 is available in 84-pin PLCC, 100-pin TQFP, 100-pin CQFP and 144-pin
TQFP packages.
Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules (see
Figure 2
). This approach allows up to 512-deep configurations as
large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.
Software support for the complete QuickRAM family, including the QL4016, is available
through two basic packages. The turnkey QuickWorks
TM
package provides the most
complete ESP software solution from design entry to logic synthesis, to place and route, to
simulation. The QuickTools package provides a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for
design entry, synthesis, or simulation.
The QuickLogic
TM
variable grain logic cell features up to 16 simultaneous inputs and five
outputs within a cell that can be fragmented into five independent cells. Each cell has a fan-
in of 29 including register and control lines (see
Figure 3
).
Figure 2: QuickRAM Module Bits
RDATA
WDATA
RADDR
RDATA
WADDR
WDATA
RAM
Module
(1,152 bits)
RAM
Module
(1,152 bits)
2002 QuickLogic Corporation
www.quicklogic.com
3
QL4016 QuickRAM Data Sheet Rev I
Product Summary
Total of 118 I/O Pins
110 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
Two array clock/control networks available to the logic cell flip-flop clock, set and reset
inputs--each driven by an input-only pin
Six global clock/control networks available to the logic cell F1, clock, set and reset inputs
and the input and I/O register clock, reset and enable inputs as well as the output enable
contro--each driven by an input-only or I/O pin, or any logic cell output or I/O cell
feedback
High Performance Silicon
Input + logic cell + output total delays = under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160+ MHz
4
www.quicklogic.com
2002 QuickLogic Corporation
QL4016 QuickRAM Data Sheet Rev I
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25
C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 10: Operating Range
by the
following numbers in the tables provided.
Figure 3: QuickRAM Logic Cell
Table 1: Logic Cell
Symbol
Parameter
Propagation Delays (ns)
Fanout (5)
1
2
3
4
5
t
PD
Combinatorial Delay
a
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
1.4
1.7
1.9
2.2
3.2
t
SU
Setup Time
a
1.7
1.7
1.7
1.7
1.7
t
H
Hold Time
0.0
0.0
0.0
0.0
0.0
t
CLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
t
CWHI
Clock High Time
1.2
1.2
1.2
1.2
1.2
t
CWLO
Clock Low Time
1.2
1.2
1.2
1.2
1.2
t
SET
Set Delay
1.0
1.3
1.5
1.8
2.8
t
RESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
t
SW
Set Width
1.9
1.9
1.9
1.9
1.9
t
RW
Reset Width
1.8
1.8
1.8
1.8
1.8
QS
A1
A2
A3
A4
A5
A6
F1
F2
F3
F4
F5
F6
QS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
QC
QR
OZ
AZ
QZ
NZ
FZ
2002 QuickLogic Corporation
www.quicklogic.com
5
QL4016 QuickRAM Data Sheet Rev I
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
5
t
SWA
WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWA
WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
SWD
WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWD
WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
SWE
WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWE
WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
WCRD
WCLK to RD (WA=RA)
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
5.0
5.3
5.6
5.9
7.1
Table 3: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
Logic Cells
1
2
3
4
5
t
SRA
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
t
HRA
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
SRE
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
t
HRE
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
RCRD
RCLK to RD
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
4.0
4.3
4.6
4.9
6.1
WA
WD
WE
WCLK
RE
RCLK
RA
RD
[8:0]
[17:0]
[8:0]
[17:0]
MODE
ASYNCRD
[1:0]
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