2003 QuickLogic Corporation
www.quicklogic.com
Preliminary
1
Device Highlights
High Performance PCI Controller
32-bit/33 MHz PCI Target with Embedded
Programmable Logic
Zero-wait state target Write bursts and one-wait
state Read bursts
Programmable back-end interface to optional
local processor
Independent PCI bus and local bus (up to 160
MHz) clocks
Fully Customizable PCI Configuration Space
Reference design with driver code
(Win 95/98/Win 2000/NT4.0) available
PCI v2.2 compliant
Supports Type 0 Configuration Cycles in Target
mode
3.3 V, 5 V tolerant PCI signaling supports
Universal PCI Adapter designs
High performance PCI controller 3.3 V CMOS in
208-pin PQFP and 144-pin TQFP packages
Extendable PCI Functionality
Support for Configuration Space from 0 40 to
0 3FF
Multi-Function, Expanded Capabilities, and
Expansion ROM capable
Power Management, Compact PCI,
Hot-Swap/Hot-Plug compatible
PCI v2.2 Power Management Specification
compatible
PCI v2.2 Vital Product Data (VPD) configuration
support
I
2
O Support with local processor
Mailbox Register support
Programmable Logic
560 Logic Cells
250 MHz 16-bit counters and 275 MHz
datapaths
All back-end interface and glue-logic can be
implemented on chip
Three 32-bit bus interfaces between the PCI
Controller and the Programmable Logic
Figure 1: QL5020 Block Diagram
Architecture Overview
The QL5020 device in the QuickLogic QuickPCITM
ESP (Embedded Standard Product) family provides a
complete and customizable PCI interface solution
combined with programmable logic. This device
eliminates any need for the designer to worry about
PCI bus compliance, yet allows for the maximum 32-
bit PCI bus bandwidth (132 MBps).
The programmable logic portion of the device contains
560 QuickLogic logic cells.
The QL5020 device meets PCI 2.2 electrical and
timing specifications and has been fully hardware-
tested. This device also supports the Win'98 and PC'98
standards.
The QL5020 device features 3.3 V operation with
multi-volt compatible I/Os. Thus, it can easily operate
in 3 V systems and is fully compatible with 3.3 V, 5 V,
or Universal PCI card development.
PCI Bus
PCI Bus 66 MHz/32 bits (data and address
)
Target
Controller
Config
space
High Speed
Logic Cells
High Speed
Data Path
Programmable
Logic
32 bit PCI Interface
118/65 User I/O
PCI Controller
QL5020 QuickPCI Data Sheet
33 MHz/32-bit PCI with Embedded Programmable Logic
www.quicklogic.com
2003 QuickLogic Corporation
QL5020 QuickPCI Data Sheet Rev C
Preliminary
2
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Target Controller. It is capable to
accept infinite length Write transactions at zero wait states (132 MBps). The QL5020 will not
insert wait states during Write transfers as long as the logic in the programmable device can accept
the data. The Target interface offers full PCI Configuration Space and flexible target addressing.
Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and
optional PCI 2.2 Configuration Space registers can be implemented within the programmable
region of the device. A reference design of a Target Configuration and Addressing module is
provided.
The Target Configuration Space and Address Decoding are done in the programmable logic
region of the device. Since these functions are not timing critical, leaving these elements in the
programmable region allows the greatest degree of flexibility to the designer. References to
Configuration Space and Address Decoding blocks are included so that the design cycle can be
minimized.
Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device.
PCI address and command decoding is performed by logic in the programmable section of the
device. This allows support for any size of memory or I/O space for back-end logic. It also allows
the user to implement any subset of PCI commands supported by the QL5020. QuickLogic
provides a reference Address Register/Counter and Command Decode block.
Internal PCI Interface
Figure 2
shows the interface symbol you will use in your schematic design to attach the local
interface programmable logic design to the PCI core. If you were designing with a top-level
Verilog or VHDL file, then you would use a structural instantiation of this PCIT32N block,
instead of a graphical symbol.
2003 QuickLogic Corporation
www.quicklogic.com
QL5020 QuickPCI Data Sheet Rev C
Preliminary
3
Figure 2: PCI Interface Symbol
PCIT32N
www.quicklogic.com
2003 QuickLogic Corporation
QL5020 QuickPCI Data Sheet Rev C
Preliminary
4
PCI Target Interface
Table 1: PCI Target Interface Signals
Signal
I/O
Description
Usr_Addr_WrData
[31:0]
O
Target address and data from target Writes
. During all target accesses, the
address will be presented on Usr_Addr_WrData[31:0] and simultaneously,
Usr_Adr_Valid will be active. During target Write transactions, this port will present write
data to the PCI configuration space or
user logic.
Usr_CBE[3:0]
O
PCI command and byte enables
. During target accesses, the PCI command will be
presented on Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During
target Read or Write transactions, this port will present active-low byte-enables to the
PCI configuration space or user logic.
Usr_Adr_Valid
O
Indicates the beginning of a PCI transaction, and that a target address is valid on
Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this
signal is active, the target address must be latched and decoded to determine if this
address belongs to the device's memory space. Also, the PCI command must be decoded
to determine the type of PCI transaction. On subsequent clocks of a target access, this
signal will be low, indicating that data (not an address) is present on
Usr_Addr_WrData[31:0].
Usr_Adr_Inc
O
Indicates that the target address should be incremented, because the previous data
transfer was completed. During burst target accesses, the target address is only
presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid
is active), and must therefore be latched and incremented by four for subsequent data
transfers.
Usr_WrReq
O
This signal will be active for the duration of a target Write transaction, and may be used
by back-end logic to turn on output-enables for transmitting the data off-chip.
Usr_RdDecode
I
Active when a user Read command has been decoded from the Usr_CBE[3:0] bus. This
command may be mapped from any of the PCI Read commands, such as Memory Read,
Memory Read Line, Memory Read Multiple, I/O Read, etc.
Usr_WrDecode
I
Active when a user Write command has been decoded from the Usr_CBE[3:0] bus. This
command may be mapped from any of the PCI Write commands, such as Memory Write
or I/O Write.
Usr_Select
I
The address on Usr_Addr_WrData[31:0] has been decoded and determined to be within
the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of
the valid Base Address Registers in the PCI configuration space. Also, this signal must
be gated by the Memory Access Enable or I/O Access Enable registers in the PCI
configuration space (Command Register bits 1 or 0 at offset 04h).
Usr_Write
O Write enable for data on Usr_Addr_WrData[31:0] during PCI writes.
Cfg_Write
O
Write enable for data on Usr_Addr_WrData[31:0] during PCI configuration Write
transactions.
Cfg_RdData[31:0]
I
Data from the PCI configuration registers, required to be presented during PCI
configuration reads.
Usr_RdData[31:0]
I
Data from the back-end user logic (and/or DMA configuration registers), required to be
presented during PCI reads.
2003 QuickLogic Corporation
www.quicklogic.com
QL5020 QuickPCI Data Sheet Rev C
Preliminary
5
PCI Internal Signals
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5020
device. Six pins are dedicated to JTAG and programming functions on each QL5020 device, and
are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB
are JTAG pins. A sixth pin, STM, is used only for programming.
Cfg_CmdReg8
Cfg_CmdReg6
I
Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h).
Cfg_PERR_Det
O
Parity error detected on the PCI bus
. When this signal is active, bit 15 of the Status
Register must be set in the PCI configuration space (offset 04h).
Cfg_SERR_Sig
O
System error asserted on the PCI bus
. When this signal is active, the Signalled
System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space
(offset 04h).
Usr_TRDYN
O Copy of the TRDYN signal as driven by the PCI target interface.
Usr_STOPN
O Copy of the STOPN signal as driven by the PCI target interface.
Usr_Devsel
O Inverted copy of the DEVSELN signal as driven by the PCI target interface.
Usr_Last_Cycle_D1
O Last transfer in a PCI transaction is occurring.
Usr_Rdy
I
Used to delay (add wait states to) a PCI transaction when the back end needs additional
time. Subject to PCI latency restrictions.
Usr_Stop
I
Used to prematurely stop a PCI target access on the next PCI clock.
Table 2: PCI Internal Signals
Signal
I/O
Description
PCI_clock
O PCI clock.
PCI_reset
O PCI reset signal.
PCI_IRDYN_D1
O Copy of the IRDYN signal from the PCI bus, delayed by one clock.
PCI_FRAMEN_D1
O Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
PCI_DEVSELN_D1
O Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
PCI_TRDYN_D1
O Copy of the TRDYN signal from the PCI bus, delayed by one clock.
PCI_STOPN_D1
O Copy of the STOPN signal from the PCI bus, delayed by one clock.
PCI_IDSEL_D1
O Copy of the IDSEL signal from the PCI bus, delayed by one clock.
Table 1: PCI Target Interface Signals (Continued)
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