2003 QuickLogic Corporation
www.quicklogic.com
Preliminary
1
Device Highlights
Flexible Programmable Logic
0.18
, six layer metal CMOS process
1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O
Up to 4,008 dedicated flip-flops
Up to 55.2 K embedded SRAM bits
Up to 310 I/O
Up to 335 user available pins
Up to 370 K system gates
IEEE 1149.1 boundary scan testing compliant
Low power capability
Embedded Dual Port SRAM
Up to twenty-four 2,304 bit dual port high
performance SRAM blocks
RAM/ROM/FIFO wizard for automatic
configuration
Configurable and cascadable aspect ratio
Programmable I/O
High performance I/O cell with Tco of 3 ns
Programmable slew rate control
Programmable I/O standards:
LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,
SSTL2, and SSTL3
Independent I/O banks capable of supporting
multiple standards in one device
I/O register configurations: Input, Output,
Output Enable (OE)
Advanced Clock Network
Multiple dedicated low skew clock networks
High drive input-only networks
Quadrant-based
segmentable clock networks
User programmable Phase Locked Loops (PLL)
Embedded Computational Units
(ECUs)
Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate functions.
Security Features
The QuickLogic products come with secure
ViaLink
technology that protects intellectual
property from design theft and reverse engineering.
No external configuration memory needed;
instant-on at power-up.
Figure 1: Eclipse-II
Block Diagram
Embedded RAM Blocks
PLL
PLL
Fabric
Embeded Computational Units
Embedded RAM Blocks
PLL
PLL
Ultra-Low Power FPGA Combining Performance, Density, and
Embedded RAM
Eclipse-II Family Data Sheet
www.quicklogic.com
2003 QuickLogic Corporation
Eclipse-II Family Data Sheet Rev. C
Preliminary
2
QuickWorks Design Software
The QuickWorks
package provides the most complete ESP and FPGA software solution from design entry
to logic synthesis, to place and route, and simulation. The package provides a solution for designers who use
third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-party tools for design
entry, synthesis, or simulation.
Process Data
Eclipse-II is fabricated on a 0.18
, six layer metal CMOS process. The core voltage is 1.8 V and the I/Os are
up to 3.3 V drive/tolerant. The Eclipse-II product line is available in commercial, industrial, and military
temperature grades.
Table 1: Eclipse-II Product Family Members
QL8025
QL8050
QL8150
QL8250
QL8325
Max Gates
47,052
63,840
188,946
248,160
320,640
Logic Array
16 x 8
16 x 16
32 x 20
40 x 24
48 x 32
Logic Cells
128
256
640
960
1,536
Max Flip-Flops
526
884
1,697
2,670
4,002
Max I/O
90
92
143
250
310
RAM Modules
4
4
16
20
24
RAM Bits
9,216
9,216
36,864
46,100
55,300
PLLs
-
-
-
4
4
ECUs
-
-
-
10
12
Packages
VQFP
100
100
-
-
-
TFBGA (0.8 mm)
196
196
196
-
-
PQFP
-
-
208
208
208
LFBGA (0.8 mm)
-
-
-
280
280
BGA (1.0 mm)
-
-
-
484
484
Table 2: Max I/O per Device/Package Combination
Device
100 VQFP
196 TFBGA
208 PQFP
280 LFBGA
484 PBGA
QL8025
62
90
-
-
-
QL8050
62
92
-
-
-
QL8150
-
100
143
-
-
QL8250
-
-
115
163
250
QL8325
-
-
115
163
310
2003 QuickLogic Corporation
www.quicklogic.com
Eclipse-II Family Data Sheet Rev. C
Preliminary
3
Programmable Logic Architectural Overview
The Eclipse-II
logic cell structure is presented in
Figure 2
. This architectural feature addresses today's register-
intensive designs.
The Eclipse-II logic cell structure presented in
Figure 2
is a dual register, multiplexor-based logic cell. It is
designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and
RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be
loaded from the NZ output or directly from a dedicated input.
NOTE:
The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects
which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can
be connected to multiple routing channels.
The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one
multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30
(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six
outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell
accommodates many user functions with a single level of logic delay while other architectures require two or
more levels of delay.
Table 3: Performance Standards
Function
Description
Slowest Speed Grade
Fastest Speed Grade
Multiplexer
16:1
2.8 ns
2.4 ns
Parity Tree
24
3.4 ns
2.9 ns
36
4.6 ns
3.9 ns
Counter
16 bit
275 MHz
328 MHz
32 bit
250 MHz
300 MHz
FIFO
128 x 32
197 MHz
235 MHz
128 x 64
188 MHz
266 MHz
256 x 16
208 MHz
248 MHz
Clock-to-Out
4 ns
3.3 ns
System clock
200 MHz
300 MHz
www.quicklogic.com
2003 QuickLogic Corporation
Eclipse-II Family Data Sheet Rev. C
Preliminary
4
Figure 2: Eclipse-II Logic Cell
RAM Modules
The Eclipse-II Product Family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM,
ROM, and FIFO functions. Each module is user-configurable into four different block organizations and can be
cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown
in
Figure 4
.
Figure 3: 2,304-bit RAM Module
The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using
two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256 x 9 (Mode 1), 512 x 4
(Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily cascadable to increase their effective width
and/or depth (see
Figure 4
)
.
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MS
D1
E1
NP
E2
D2
NS
F1
F3
F5
F6
F2
F4
PS
PP
MP
AZ
OZ
QZ
NZ
FZ
Q2Z
QC
QR
MODE[1:0]
WA[9:0]
WD[17:0]
WE
WCLK
2,304-bit RAM Module
ASYNCRD
RA[9:0]
RD[17:0]
RE
RCLK
2003 QuickLogic Corporation
www.quicklogic.com
Eclipse-II Family Data Sheet Rev. C
Preliminary
5
Figure 4: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 512 words. In this case address signals higher
than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs
are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with
data from an external PROM (typically for ROM functions).
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively--
these functions require high logic cell usage while garnering only moderate performance results.
The Eclipse-II architecture allows for functionality above and beyond that achievable using programmable logic
devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-II device can address
various arithmetic functions efficiently. This approach offers greater performance than traditional
programmable logic implementations. The embedded block is implemented at the transistor level as shown in
Figure 5
.
WDATA
RDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
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