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PCI Bus Target Interface
Datasheet
Revision 1.1
V3 Semiconductor Corp.
V3 Semiconductor makes no warranties for the use of its products. V3 does not assume any liability for errors which may appear in this document,
however, we will attempt to notify customers of such errors.
V3 Semiconductor retains the right to make changes to either the documentation, specification or component without notice.
Please verify with V3 Semiconductor to be sure you have the latest specifications before finalizing a design.
V 3 S e m i c o n d u c to r 1 9 9 7
T h e E m b e d d e d C h i p s e t C o m p a n y i s a t ra d e m a r k o f V 3 S e m i c o n d u c to r C o r p .
A l l o t h e r t r a d e m a r k s a r e t h e p r o p e r t y o f t h e i r re s p e c ti v e o w n e r s .
Copyright 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
1
V300PSC
Rev. A0
PCI BUS TARGET INTERFACE
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V300PSC, V96SSC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
A general purpose PCI bus target interface
Multiplexed and de-multiplexed 32-, 16-, or 8-
bit local bus interface
Fully compliant with PCI 2.1 specification
Large, 288-byte FIFOs using V3's unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
TM architecture
On-the-fly byte order (endian) conversion
including automatic endian detection
Address space remapping
Mailboxes w/doorbell interrupts
Flexible PCI and local interrupt management
Serial EEPROM configuration interface
33MHz local bus with independent PCI bus
operation up to 33MHz
Low cost 160-pin EIAJ PQFP package
T h e V 3 0 0 P S C p r o v i d e s t h e h i g h e s t
performance, most flexible, and most economical
method to connect a general purpose 32-, 16-, 8-
bit local bus to the PCI bus. V3 Semiconductor's
simple to use local bus interface makes the
V300PSC the fastest route to adding PCI to your
system. The V300PSC may be used in systems
without a CPU for a generic PCI target interface.
The V300PSC supports independent interface
speeds allowing the PCI bus to run at the full
33MHz frequency, regardless of local bus clock
rate. The V300PSC uses the unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
TM FIFOs to decouple the
local and PCI bus, while dramatically improving
the overall throughput of the system.
A PCI master can gain access to the local bus
through two programmable address apertures
with address remapping capabilities, and on-the-
fly byte order conversion.
To support existing DOS I/O devices a special
decoder mode allows up to 3 I/O regions (and
one memory region below 1MB) to be decoded.
The V300PSC's interrupt control mechanism is
very flexible and allows interrupts from multiple
sources on the local bus to share a single PCI
interrupt.
The V300PSC operates up to 33MHz, and is
packaged in a low cost, 160-pin EIAJ Plastic
Quad Flat Pack (PQFP) package.
GENERIC
32-, 16-, 8-BIT TARGET
APPLICATION
V96BMC
V96SSC
MEMORY
D
R
A
M
ROM
V300PSC
PCI to LOCAL BUS
BRIDGE
PCI
PERIPHERAL
PCI SLOT or EDGE CONNECTOR
TYPICAL APPLICATION
V300PSC
2
V300PSC Data Sheet Rev 1.1
Copyright 1997, V3 Semiconductor Corp.
This document contains the product codes, pinouts, package mechanical information, DC
characteristics, and AC characteristics for the V300PSC. Detailed functional information is contained
in the V300PSC User's Manual.
V3 Semiconductor retains the rights to change documentation, specifications, or device
functionality at any time without notice. Please verify that you have the latest copy of all
documents before finalizing a design.
1.0 Product Codes
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V300PSC. Table 3 and 4 describe modes and function of
each pin on the V300PSC. Table 5 and Table 6 list the pins by pin number. Figure 1 and Figure 2 show
the pinout for the 160-pin EIAJ PQFP package and Figure 3 shows the mechanical dimensions of the
package.
Table 1: Product Codes
Product Code
Local Bus Type
Package
Frequency
V300PSC-33 REV A0
32-,16-,8- bit
multiplexed / demultiplexed
160-pin EIAJ PQFP
33MHz
Table 2: Pin Types
Pin Type
Description
PCI I
PCI input only pin.
PCI O
PCI output only pin.
PCI I/O
PCI tri-state I/O pin.
PCI I/O
D
PCI input with open drain output.
I/O
4
TTL I/O pin with 4mA output drive.
I
TTL input only pin.
O
4
TTL output pin with 4mA output drive.
Table 3: RESET State for Configuration and Test Mode Pins
PIN#
134 (ALE)
135 (BTERM)
153
Connection for de-multiplexed bus
Pull-Up
Pull-Up
Pull-Up
Connection for multiplexed bus
Pull-Down
Pull-Up
Pull-Down
V300PSC
Copyright 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
3
Table 4: Signal Descriptions
PCI Bus Interface
Signal
Type
R
a
Description
AD[31:0]
PCI I/O
Z
Address and data, multiplexed on the same pins.
C/BE[3:0]
PCI I
Z
Bus Command and Byte Enables, multiplexed on the same pins.
PAR
PCI I/O
Z
Parity represents even parity across AD[31:0] and C/BE[3:0].
FRAME
PCI I
Z
Cycle Frame indicates the beginning and burst length of an
access.
IRDY
PCI I
Z
Initiator Ready indicates the master agent is ready to complete
the current data phase of the transaction.
TRDY
PCI O
Z
Target Ready indicates the target agent's (V300PSC) ability to
complete the current data phase of the transaction.
STOP
PCI O
Z
Stop indicates the V300PSC is requesting the master to stop the
current transaction (retry or disconnect).
DEVSEL
PCI O
Z
Device Select, indicates the V300PSC device has decoded its
address as the target of the current access.
IDSEL
PCI I
Z
Initialization Device Select is used as a chip select during configu-
ration read and write transactions. It must be driven high in order
to access the chip's internal configuration space.
PCLK
PCI I
Z
PCLK provides timing for all transactions on the PCI bus.
PRST
PCI I
Z
Asserted low to bring all internal operations to a reset state.
PERR
PCI I/O
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
SERR
PCI I/O
D
Z
System Error is used to report address parity errors, data parity
errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
INT[A:D]
PCI I/O
D
Z
Level-sensitive interrupt requests may be received or generated.
Serial EEPROM Interface
Signal
Type
R
Description
SCL/LPERR
O
4
X
EEPROM clock. Local parity error.
SDA
I/O
4
X
EEPROM data.
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