Copyright 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
1
V350EPC
Rev. A0
LOCAL BUS TO PCI BRIDGE
FOR MULTIPLEXED A/D PROCESSORS
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V350EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
Glueless interface to Intel's i960Jx and IBM's
PowerPC
TM
401Gx processors
Configurable for primary master, bus master or
target operation.
Type 0 and type 1 configuration cycles.
Up to 1Kbyte burst access on PCI or local.
Large, 640-byte FIFOs using V3's unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
TM architecture
64-byte read FIFO per aperture.
Enhanced support for 8/16-bit local bus devices
with programmable region sizes.
3.3 volt support
Dual bi-directional address space remapping
Fully compliant with PCI 2.1 specification
On-the-fly byte order (endian) conversion
I
2
O ATU and messaging unit including
hardware controlled circular queues
2 channel DMA controller plus multiprocessor
DMA chaining and demand mode DMA
Hot swapping capability
16 8-bit bi-directional mailbox registers with
doorbell interrupts
Flexible PCI and local interrupt management
Optional power-on serial EEPROM initialization
33MHz and 40MHz local bus versions
Industrials temperature grade -40 to +85'C
Low cost 160-pin EIAJ PQFP package
V350EPC is a high-performance and low-cost
generic solution for interfacing both 32-bit and
16-bit multiplexed local bus applications to the
PCI bus. V350EPC directly connects to i960Jx or
i960Sx processors without any glue logic.
M i n i m a l g l u e l o g i c i s r e q u i r e d f o r h i g h -
performance interfacing to other multiplexed
processors like Motorola ColdFireTM.
V350EPC is the second generation of V3's I
2
O
ready PCI bridges - fully backward compatible
with both V961PBC and V960PBC Rev B2
devices - and is supporting powerful features like
Hot Swap and DMA chaining. The PCI bus can
be run at the full 33MHz frequency, independent
of local bus clock rate. The overall throughput of
t h e s y s t e m i s d r a m a t i c a l l y i m p r o v e d b y
increasing the FIFO depths and utilizing the
u n iq u e D
Y N A M I C
B
A N D W I D T H
A
L L O C AT I O N
TM
architecture.
Access to the PCI bus can be performed through
two programmable address apertures. Two more
apertures are provided for PCI-to-local bus
accesses. There are 64-bytes of read FIFOs in
each direction, 32-byte dedicated for each
aperture .
Two high-performance DMA channels with
chaining and demand mode capabilities provide
a powerful data transfer engine for bulk data
transfers. Mailbox registers and flexible PCI
interrupt controllers are also included to provide
a simple mechanism to emulate PCI device
control ports. The part is available in 160-pin low
cost PQFP packages in 33MHz and 40MHz
versions.
i960Jx
CPU
V96BMC
MEMORY
CONTROL
D
R
A
M
ROM
V350EPC
LOCAL TO
PCI BRIDGE
TYPICAL APPLICATION
PERIPHERAL
PCI
PCI SLOT or EDGE CONNECTOR
V350EPC
2
V350EPC Data Sheet Rev 1.1
Copyright 1998, V3 Semiconductor Inc.
This document contains the product codes, pinouts, package mechanical information, DC
characteristics, and AC characteristics for the V350EPC. Detailed functional information is contained
in the User's Manual.
V3 Semiconductor retains the rights to change documentation, specifications, or device
functionality at any time without notice. Please verify that you have the latest copy of all
documents before finalizing a design.
1.0 Product Codes
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V350EPC. Table 3 describes the function of each pin on
the V350EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ
PQFP package and Figure 2 shows the mechanical dimensions of the package.
Table 1: Product Codes
Product Code
Processors
Bus Type
Package
Frequency
V350EPC-33 REV A0
i960Jx/Sx
32/16-bit multiplexed
160-pin EIAJ PQFP
33MHz
V350EPC-40 REV A0
i960Jx/Sx
32/16-bit multiplexed
160-pin EIAJ PQFP
40MHz
Table 2: Pin Types
Pin Type
Description
PCI I
PCI input only pin.
PCI O
PCI output only pin.
PCI I/O
PCI tri-state I/O pin.
PCI I/OD
PCI input with open drain output.
I/O
4
TTL I/O pin with 4mA output drive.
I
TTL input only pin.
O
4
TTL output pin with 4mA output drive.
V350EPC
Copyright 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
3
Table 3: Signal Descriptions
PCI Bus Interface
Signal
Type
R
a
Description
AD[31:0]
PCI I/O
Z
Address and data, multiplexed on the same pins.
C/BE[3:0]
PCI I/O
Z
Bus Command and Byte Enables, multiplexed on the same pins.
PAR
PCI I/O
Z
Parity represents even parity across AD[31:0] and C/BE[3:0].
FRAME
PCI I/O
Z
Cycle Frame indicates the beginning and burst length of an
access.
IRDY
PCI I/O
Z
Initiator Ready indicates the initiating agent's (bus master's) ability
to complete the current data phase of the transaction.
TRDY
PCI I/O
Z
Target Ready indicates the target agent's (selected device's) abil-
ity to complete the current data phase of the transaction.
STOP
PCI I/O
Z
Stop indicates the current target is requesting the master to stop
the current transaction (retry or disconnect).
DEVSEL
PCI I/O
Z
Device Select, when actively driven by a target, indicates the driv-
ing device has decoded its address as the target of the current
access. As an input to the initiator, DEVSEL indicates whether
any device on the bus has been selected.
IDSEL
PCI I
Initialization Device Select is used as a chip select during configu-
ration read and write transactions. It must be driven high in order
to access the chip's internal configuration space.
REQ
PCI O
Z
Request indicates to the arbiter that this agent requests use of the
bus.
GNT
PCI I
Grant indicates to the agent that access to the bus has been
granted.
PCLK
PCI I
PCLK provides timing for all transactions on the PCI bus.
PRST
PCI I/O
Z/L
Acts as an input when RDIR is high, an output when RDIR is low.
As an input it is asserted low to bring all internal PBC operation to
a reset state.
PERR
PCI I/O
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
SERR
PCI I/OD
Z
System Error is used to report address parity errors, data parity
errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
INT[A:D]
PCI I/OD
Z
Level-sensitive interrupt requests may be received or generated.
V350EPC
4
V350EPC Data Sheet Rev 1.1
Copyright 1998, V3 Semiconductor Inc.
Local Bus Interface
Signal
Type
R
Description
LAD[31:0]
LAD[15:0]
b
I/O4
Z
Local multiplexed address and data bus.
LA[31:16]
b
I/O4
Z
Local address bus.
LA[5:2]
O4
Lower local address bus (non-multiplexed version).
ALE
I/O4
Z
Address Latch Enable: used to latch the address during the
address phase.
BE[3:0]
BE[1:0]
b
I/O4
Z
Local bus byte enables.
W/R
I/O4
Z
Write/Read.
ADS
AS
b
I/O4
Z
Asserted low to indicate the beginning of a bus cycle.
RDYRCV
READY
b
I/O4
Z
Local Bus data ready
HOLD
O4
L
Local bus hold request: asserted by the chip to initiate a local bus
master cycle.
HOLDA
I
Local bus hold acknowledge.
LPAR[3:0]
LPAR[1:0]
b
I/O4
Z
Local bus parity.
BLAST
I/O4
Z
Burst last.
BTERM
c
I/O4
Z
Bus Time-out. Burst terminate.
LINT
O4
H
Local interrupt request.
LRST
I/O4
L/Z
Local bus RESET signal.
LCLK
I
Local bus clock.
Serial EEPROM Interface
Signal
Type
R
Description
SCL/LPERR
O4
X
EEPROM clock. Local parity error.
SDA
I/O4
X
EEPROM data.
Table 3: Signal Descriptions (cont'd)
V350EPC
Copyright 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
5
2.1
Test Mode Pins
Several device pins are used during manufacturing test to put the V350EPC device into various test
modes.
These pins must be maintained at proper levels during reset to insure proper operation.
This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if
they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for
test mode pins:
Configuration
Signal
Type
R
Description
RDIR
I
Reset direction. Tie low to drive PRST out and LRST in, high to
drive LRST out and PRST in.
EN5V
I
Selects 5V (EN5V driven low) or 3.3V (EN5V driven high) device
operation modes.
Power and Ground Signals
Signal
Type
R
Description
V
CC
-
POWER leads intended for external connection to a V
CC
board
plane.
GND
-
GROUND leads intended for external connection to a GND board
plane.
a. R indicates state during reset.
b. Applies to i960Sx mode.
c. Applies to i960Jx mode.
Table 4: RESET State for Test Mode Pins
Mode
Pin 134
Pin 135
Pin 153
i960Jx
Pull-Down
Pull-Up
Pull-Down
i960Sx
Pull-Down
Pull-Down
Pull-Down
Table 3: Signal Descriptions (cont'd)
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