RTL8101L
2002/03/20
Rev. 120
1
REALTEK SINGLE CHIP
FAST ETHERNET CONTROLLER
AND
MC'97 CONTROLLER
WITH POWER MANAGEMENT
RTL8101L
1. Features:....................................................................... 3
1.1 Ethernet Controller Features: .................................. 3
1.2 MC'97 Controller Features:.................................... 3
2. General Description..................................................... 4
3. Pin Assignment............................................................. 5
4. Pin Description............................................................. 6
4.1 Power Management/Isolation Interface................... 6
4.2 PCI Interface........................................................... 6
4.3 EEPROM Interface ................................................. 7
4.4 Power Pins .............................................................. 8
4.5 LED Interface ......................................................... 8
4.6 Attachment Unit Interface....................................... 8
4.7 AC-Link Pins .......................................................... 8
4.8 Test and Other Pins............................................... 10
5. Ethernet Controller Register Descriptions .............. 11
5.1 Receive Status Register in Rx packet header ........ 13
5.2 Transmit Status Register (TSD0-3)....................... 13
5.3 ERSR: Early Rx Status Register ........................... 14
5.4 Command Register................................................ 14
5.5 Interrupt Mask Register ........................................ 15
5.6 Interrupt Status Register........................................ 15
5.7 Transmit Configuration Register........................... 16
5.8 Receive Configuration Register ............................ 17
5.9 9346CR: 93C46 Command Register..................... 20
5.10 CONFIG 0: Configuration Register 0 ................. 20
5.11 CONFIG 1: Configuration Register 1 ................. 20
5.12 Media Status Register ......................................... 21
5.13 CONFIG 3: Configuration Register3 .................. 22
5.14 CONFIG 4: Configuration Register4 .................. 23
5.15 Multiple Interrupt Select Register....................... 24
5.16 PCI Revision ID.................................................. 24
5.17 Transmit Status of All Descriptors (TSAD) Register............. 24
5.18 Basic Mode Control Register.............................. 24
5.19 Basic Mode Status Register ................................ 25
5.20 Auto-negotiation Advertisement Register ........... 25
5.21 Auto-Negotiation Link Partner Ability Register . 26
5.22 Auto-negotiation Expansion Register ................. 27
5.23 Disconnect Counter ............................................ 27
5.24 False Carrier Sense Counter ............................... 27
5.25 NWay Test Register ........................................... 27
5.26 RX_ER Counter.................................................. 27
5.27 CS Configuration Register.................................. 28
5.28 Config5: Configuration Register 5...................... 28
6. MC'97 Controller Register and Descriptor Descriptions.......... 30
6.1 The Starting Descriptor Index for LINE-Out........ 30
6.2 The Current Descriptor Index for LINE-Out........ 30
6.3 The Last Descriptor Index for LINE-Out ............. 30
6.4 LINE-Out DMA Status Register........................... 31
6.5 LINE-Out DMA Control Register ........................ 31
6.6 Residual Samples Count in Current LINE-Out Descriptor Register31
6.7 LINE-Out Descriptor Base Address Register ....... 32
6.8 The Starting Descriptor Index for LINE-In .......... 32
6.9 The Current Descriptor Index for LINE-In........... 32
6.10 The Last Descriptor Index for LINE-In.............. 32
6.11 LINE-In DMA Status Register ........................... 32
6.12 LINE-In DMA Control Register......................... 32
6.13 Residual Samples Count in Current LINE-In Descriptor Register 33
6.14 Line-In Descriptor Base Address Register ......... 33
6.15 MC'97-Link Control Register ............................ 34
6.16 MC'97-Link Status and Index Register .............. 34
6.17 AC-Link Data Port.............................................. 35
6.18 GPIO Control to MC'97..................................... 35
6.19 Real Time GPIO Input Data From MC'97 ......... 36
6.20 Interrupt Status Register ..................................... 36
6.21 PCI GPIO Setup Register ................................... 37
6.22 PCI GPIO Status Register................................... 39
6.23 Context For Line-Out Descriptor........................ 39
6.24 Context For Line-In Descriptor .......................... 40
6.25 Descriptor Definition.......................................... 40
7.
EEPROM (93C46) Contents................................ 42
7.1 Summary of RTL8101L's EEPROM registers ..... 44
7.2 Summary of EEPROM Power Management registers........... 44
8.
PCI Configuration Space Registers..................... 45
RTL8101L
2002-03-20
Rev.1.2
2
8.1 PCI Configuration Space Table ............................ 45
8.2 PCI Configuration Space functions....................... 46
8.3 The Default Value after Power-on ........................ 50
8.4 PCI Power Management functions........................ 51
8.5 VPD (Vital Product Data)..................................... 53
9. Block Diagram ........................................................... 54
10. Functional Description ............................................ 55
10.1 Transmit operation.............................................. 55
10.2 Receive operation ............................................... 55
10.3 Wander Compensation........................................ 55
10.4 Signal Detect....................................................... 55
10.5 Line Quality Monitor .......................................... 55
10.6 Clock Recovery Module ..................................... 55
10.7 Loopback Operation ........................................... 55
10.8 Tx Encapsulation ................................................ 56
10.9 Collision.............................................................. 56
10.10 Rx Decapsulation.............................................. 56
10.11 Flow Control..................................................... 56
10.11.1 Control Frame Transmission...................... 56
10.11.2 Control Frame Reception........................... 56
10.12 LED Functions.................................................. 57
10.12.1 10/100 Mbps Link Monitor........................ 57
10.12.2 LED_RX.................................................... 57
10.12.3 LED_TX .................................................... 58
10.12.4 LED_TX+LED_RX................................... 58
11. Application Diagram............................................... 59
12. Electrical Characteristics........................................ 60
12.1 Temperature Limit Ratings:................................ 60
12.2 DC Characteristics:............................................. 60
12.3 AC Characteristics.............................................. 61
12.3.1 PCI Bus Operation Timing: ......................... 61
13. Dimensions ............................................................... 67
RTL8101L
2002-03-20
Rev.1.2
3
1. Features:
1.1 Ethernet Controller Features:
100 pin LQFP
Integrated Fast Ethernet MAC, Physical chip and
transceiver in one chip
10 Mb/s and 100 Mb/s operation
Supports 10 Mb/s and 100 Mb/s N-way
Auto-negotiation operation
PCI local bus single-chip Fast Ethernet controller
Compliant to PCI Revision 2.2
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back transaction
Provides PCI bus master data transfers and PCI
memory space or I/O space mapped data transfers
of RTL8101L's operational registers
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports 25MHz crystal or 25MHz OSC as the internal
clock source. The frequency deviation of either crystal
or OSC must be within 50 PPM.
Compliant to PC99/PC2001 standard
Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft
wake-up frame)
Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
Supports auxiliary power-on internal reset, for remote
wake-up when main power remains off
Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space
Includes a programmable PCI burst size and early Tx/Rx
threshold
Supports a 32-bit general-purpose timer with the
external PCI clock as clock source to generate
timer-interrupt
Contains two large (2Kbyte) independent receive and
transmit FIFOs
Advanced power saving mode when LAN function or
wakeup function is not used
Uses 93C46 (64*16-bit EEPROM) to store resource
configuration, ID parameter, and VPD data
Supports LED pins for various network activity
indications
Supports loopback capability
Half/Full duplex capability
Supports Full Duplex Flow Control (IEEE 802.3x)
3.3V power supply, 3.3V and 5V I/O tolerance
Interface for 128K byte (max) Boot ROM for both
EEPROM and Flash Memory.
1.2 MC'97 Controller Features:
MC'97 compatible digital controller chip
PCI local bus single-chip Fast Ethernet controller
32-bit PCI bus master and PCI v 2.2 compliant
PCI Bus Power Management Interface Specification v
1.1 compliant
High performance bus master DMA for data transfer
AC'97 v 2.2 compliant
Supports 16-bit modem line (LINE1)
Full-duplex operation for simultaneous LINE1
transactions
Low latency GPIO updated
8 double-WORD (16 samples) FIFO depth for each bus
master of LINE1-OUT/IN
3.3V power supply, 3.3V and 5V I/O tolerance
RTL8101L
2002-03-20
Rev.1.2
4
2. General Description
The Realtek RTL8101L is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides 32-bit
performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-TX specifications and IEEE 802.3x Full
Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management
for modern operating systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management possible. The RTL8101L no longer supports CardBus mode as RTL8139C does.
In addition to the ACPI feature, the RTL8101L also supports remote wake-up (including AMD Magic Packet, LinkChg, and
Microsoft
wake-up frame) in both ACPI and APM environments. The RTL8101L is capable of performing an internal reset
through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8101L is
ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output
signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8101L LWAKE pin
provides motherboards with Wake-On-LAN (WOL) functionality.
The RTL8101L also supports Analog Auto-Power-down, that is, the analog part of the RTL8101L can be shut down temporarily
according to user requirements or when the RTL8101L is in a power down state with the wakeup function disabled. In addition,
when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop
functioning and the power consumption of the RTL8101L will be negligible. The RTL8101L also supports an auxiliary power
auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration
space.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the OEM brand
name of RTL8101L LAN card). The information may consist of part number, serial number, and other detailed information.
To provide cost down support, the RTL8101L is capable of using a 25MHz crystal or OSC as its internal clock source.
The RTL8101L keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network
from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at no additional cost. To
improve compatibility with other brands' products, the RTL8101L is also capable of receiving packets with InterFrameGap no
less than 40 Bit-Time. The RTL8101L is highly integrated and requires no "glue" logic or external memory.
The RTL8101L includes a PCI and Expansion Memory Share Interface (Realtek patent) for a boot ROM and can be used in
diskless workstations, providing maximum network security and ease of management.
RTL8101L
2002-03-20
Rev.1.2
5
3. Pin Assignment
81 RTSB
82 GNTB
83 REQB
84 CBE3B
85 AD31
87 AD29
88 GND
89 AD28
90 VDD
91 AD27
92 AD26
93 AD25
94 VDD25
95 VDD
96 AD24
97 PCICLK
98 IDSEL
86 AD30
100 GPIO0
99 GPIO1
79 INTBB
80 INTAB
76 LED2
77 LED1
78 LED0
RTL8101L LQFP
1 AC_RSTB
2 GND
3 AC_SYNC
4 AC_DOUT
5 AC_DIN
6 VDD
7 AC_BCK
8 AD23
9 AD22
10 AD21
11 AD20
12 AD19
13 AD18
25 PERRB
24 PAR
23 STOPB
22 VDD
21 DEVSELB
20 TRDYB
19 IRDYB
18 FRAMEB
17 CBE2B
16 GND
15 AD16
14 AD17
48 VDD25
47 AD0
46 AD1
45 AD2
44 GND
43 AD3
42 AD4
41 AD5
40 AD6
37 VDD
36 AD8
35 AD9
34 AD10
33 AD11
32 AD12
31 GND
30 AD13
29 AD14
39 AD7
38 CBE0B
27 CBE1B
26 SERRB
28 AD15
50 CLKRUNB
49 VDD
65 RTSET
66 GND
62 GND
61 X1
60 X2
59 AVDD
58 AVDD25
57 PMEB
56 VCTRL
55 EECS
54 EESK
53 EEDI
63 RTT3
52 EEDO
51 ROMCS/OEB
67 RXIN-
68 RXIN+
69 NC
70 AVDD
71 TXD-
72 TXD+
73 GND
74 ISOLATEB
64 LWAKE
75 AVDD
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