2-PORT 100/200/400MBPS
CABLE TRANSCEIVER/ARBITER CHIP
DATASHEET
Rev. 3.4
11 August 2003
Track ID: JATR-1076-21
RTL8801B
RTL8801B
Datasheet
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip
ii
Track ID: JATR-1076-21 Rev. 3.4
COPYRIGHT
2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
DISCLAIMER
Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
USING THIS DOCUMENT
This document is intended for use by the software engineer when programming for Realtek RTL8801B
controller chips. Information pertaining to the hardware design of products using these chips is contained in
a separate document.
Though every effort has been made to assure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
Summary
1.0 2002/05/30
First
release.
1.1
2003/02/12
Modify block diagram and general description.
2.0
2003/03/22
Modify pin descriptions.
3.0
2003/06/03
Modify application information.
3.4
2003/08/05
Cosmetic changes to document layout.
RTL8801B
Datasheet
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip
iii
Track ID: JATR-1076-21 Rev. 3.4
Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................. 1
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM ........................................................................................................................... 3
4. PIN ASSIGNMENTS.......................................................................................................................... 4
5. PIN DESCRIPTIONS......................................................................................................................... 5
6. REGISTER DESCRIPTIONS........................................................................................................... 7
6.1. PHY
R
EGISTER
M
AP FOR THE
C
ABLE
E
NVIRONMENT
................................................................... 7
6.2. PHY
R
EGISTER
F
IELDS FOR THE
C
ABLE
E
NVIRONMENT
................................................................ 7
6.3. PHY
R
EGISTER
P
AGE
0: P
ORT
S
TATUS
P
AGE
................................................................................. 9
6.4. PHY
R
EGISTER
P
ORT
S
TATUS
P
AGE
F
IELDS
.................................................................................. 9
6.5. PHY
R
EGISTER
P
AGE
1: V
ENDOR
I
DENTIFICATION
P
AGE
............................................................ 10
6.6. PHY
R
EGISTER
V
ENDOR
I
DENTIFICATION
P
AGE
F
IELDS
............................................................. 10
7. FUNCTIONAL DESCRIPTION ..................................................................................................... 11
8. CHARACTERISTICS...................................................................................................................... 12
8.1. A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................... 12
8.2. O
PERATING
R
ANGE
...................................................................................................................... 12
8.3. P
OWER
D
ISSIPATION
.................................................................................................................... 12
8.4. T
IMING
W
AVEFORMS
................................................................................................................... 12
9. APPLICATION INFORMATION.................................................................................................. 13
10.
MECHANICAL DIMENSIONS.................................................................................................. 14
10.1. M
ECHANICAL
D
IMENSIONS
N
OTES
.......................................................................................... 15
RTL8801B
Datasheet
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip
iv
Track ID: JATR-1076-21 Rev. 3.4
List of Tables
T
ABLE
1. P
IN
D
ESCRIPTIONS
........................................................................................................................ 5
T
ABLE
2. PHY R
EGISTER
M
AP FOR THE
C
ABLE
E
NVIRONMENT
.................................................................. 7
T
ABLE
3. PHY R
EGISTER
F
IELDS FOR THE
C
ABLE
E
NVIRONMENT
.............................................................. 7
T
ABLE
4. PHY R
EGISTER
P
AGE
0: P
ORT
S
TATUS
P
AGE
............................................................................... 9
T
ABLE
5. PHY R
EGISTER
P
ORT
S
TATUS
P
AGE
F
IELDS
................................................................................ 9
T
ABLE
6. PHY R
EGISTER
P
AGE
1: V
ENDOR
I
DENTIFICATION
P
AGE
.......................................................... 10
T
ABLE
7. PHY R
EGISTER
V
ENDOR
I
DENTIFICATION
P
AGE
F
IELDS
............................................................ 10
T
ABLE
8. A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................. 12
T
ABLE
9. O
PERATING
R
ANGE
.................................................................................................................... 12
T
ABLE
10. D
IGITAL
T
IMING
C
HARACTERISTICS
........................................................................................... 12
List of Figures
F
IGURE
1. B
LOCK
D
IAGRAM
........................................................................................................................ 3
F
IGURE
2. P
IN
A
SSIGNMENTS
....................................................................................................................... 4
F
IGURE
3. T
IMING
W
AVEFORMS
................................................................................................................ 12
F
IGURE
4. A
PPLICATION
I
NFORMATION
..................................................................................................... 13
RTL8801B
Datasheet
2-Port 100/200/400Mbps Cable Transceiver/Arbiter Chip
1
Track ID: JATR-1076-21 Rev. 3.4
1. General
Description
The RTL8801B provides a two-port physical layer (PHY) function in a cable-based IEEE 1394-1995 and
IEEE P1394a network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission.
1. Data bits to be transmitted through the cable ports are received from the Link On 2/4/8 data lines
(D0-D8), and are latched internally in the RTL8801B in synchronization with the 49.152MHz system
clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216Mbps
as an outbound data-strobe information stream. During transmission, the encoded data is transmitted
on the twisted pair B (TPB) cable pair(s), and the encoded strobe information is transmitted on the
twisted pair A (TPA) cable pair(s).
2. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair,
and the encoded strobe information is received on the TPB cable pair. The received data-strobe
information is decoded to recover the received clock signal and the serial data bits. The serial data bits
are split into two nibbles, or four by two bits, and parallel transmitted (repeated) out of the other active
(connected) cable ports.
3. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states
during initialization and arbitration. The output of these comparators is used by the internal logic to
determine the arbitration status. The TPA channel monitors the incoming cable common-mode
voltage. The value of the common-mode voltage is used during arbitration to set the speed of the next
packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage
for the presence of a remotely supplied twisted-pair bias voltage. The presence or absence of this
common-mode voltage is used as an indication of cable connection status. The cable connection status
signal is internally debounced in the RTL8801B on a cable disconnect-to-connect. The debounced
cable connection status signal initiates a bus reset. On a cable disconnect-to-connect, a debounce delay
is incorporated. There is no delay on a cable disconnect.
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