RTL8201CL
2002-03-29
Rev.1.0
1
REALTEK SINGLE CHIP
SINGLE PORT 10/100M
FAST ETHERNET PHYCEIVER
RTL8201CL
1. Features
.........................................................................2
2. General Description
....................................................2
3. Block Diagram
..............................................................3
4. Pin Assignments
.........................................................4
5. Pin Description
............................................................5
5.1 MII Interface ............................................................5
5.2 SNI (Serial Network Interface): 10Mbps only.....5
5.3 Clock Interface........................................................6
5.4 10Mbps / 100Mbps Network Interface ................6
5.5 Device Configuration Interface.............................6
5.6 LED Interface/PHY Address Config.....................7
5.7 Reset and other pins..............................................7
5.8 Power and Ground pins.........................................7
6. Register Descriptions
................................................8
6.1 Register 0 Basic Mode Control Register.............8
6.2 Register 1 Basic Mode Status Register ..............9
6.3. Register 2 PHY Identifier Register 1 ..................9
6.4. Register 3 PHY Identifier Register 2 ..................9
6.5. Register 4 Auto-negotiation Advertisement
Register(ANAR) ..........................................................10
6.6 Register 5 Auto-Negotiation Link Partner Ability
Register(ANLPAR) ......................................................10
6.7 Register 6 Auto-negotiation Expansion
Register(ANER) ..........................................................11
6.8 Register 16 Nway Setup Register(NSR)...........11
6.9 Register 17 Loopback, Bypass, Receiver Error
Mask Register(LBREMR) ..........................................12
6.10 Register 18 RX_ER Counter(REC) .................12
6.11 Register 19 SNR Display Register...............................12
6.12 Register 25 Test Register..................................13
7. Functional Description
............................................14
7.1 MII and Management Interface ..........................14
7.1.1 Data Transition..............................................14
7.1.2 Serial Management ......................................15
7.2 Auto-negotiation and Parallel Detection............16
7.3 Flow control support ............................................ 17
7.4 Hardware Configuration and Auto-negotiation........... 17
7.5 LED and PHY Address Configuration ............... 18
7.6 Serial Network Interface...................................... 18
7.7 Power Down, Link Down, Power Saving, and Isolation
Modes............................................................................. 18
7.8 Media Interface..................................................... 19
7.8.1 100Base TX .................................................. 19
7.8.2 100Base-FX Fiber Mode Operation .......... 19
7.8.3 10Base Tx/Rx ............................................... 20
7.9 Repeater Mode Operation .................................. 20
7.10 Reset, and Transmit Bias(RTSET).................. 20
7.11 3.3V power supply and voltage conversion
circuit ............................................................................ 20
7.12 Far End Fault Indication (FEFI) ....................... 21
8. Electrical Characteristics
........................................ 22
8.1 D.C. Characteristics............................................. 22
8.1.1. Absolute Maximum Ratings ....................... 22
8.1.2. Operating Conditions.................................. 22
8.1.3. Power Dissipation ....................................... 22
8.1.4 Supply Voltage: Vcc ..................................... 22
8.2 A.C. Characteristics ............................................. 23
8.2.1 MII Timing of Transmission Cycle .............. 23
8.2.2 MII Timing of Reception Cycle ................... 24
8.2.3 SNI Timing of Transmission Cycle............. 25
8.2.4 SNI Timing of Reception Cycle .................. 26
8.2.5 MDC/MDIO timing ........................................ 27
8.2.6 Transmission Without Collision .................. 27
8.2.7 Reception Without Error.............................. 28
8.3 Crystal and Transformer Specifications ............ 29
8.3.1 Crystal Specifications .................................. 29
8.3.2 Transformer Specifications ......................... 29
9. Mechanical Dimensions
.......................................... 30
10. Revision History
...................................................... 31
RTL8201CL
2002-03-29
Rev.1.0
2
1. Features
The Realtek RTL8201CL is a Fast Ethernet Phyceiver with selectable MII or SNI interface to the MAC chip. It
provides the following features:
!
Supports MII/7-wire SNI (Serial Network
Interface) interface
!
Supports 10/100Mbps operation
!
Supports half/full duplex operation
!
Support of twisted pair or Fiber mode output
!
IEEE 802.3/802.3u compliant
!
Supports IEEE 802.3u clause 28 auto
negotiation
!
Supports power down mode
!
Supports operation under Link Down Power
Saving mode
!
Supports Base Line Winder (BLW)
compensation
!
Supports repeater mode
!
Speed/duplex/auto negotiation adjustable
!
3.3V operation with 5V IO signal tolerance
!
Low operation power consumption and only
need single supply 3.3V
!
Adaptive Equalization
!
25MHz crystal/oscillator as clock source
!
Multiple network status LED support
!
Flow control ability support to co-work with
MAC (by MDC/MDIO)
!
48 pin LQFP package
2. General Description
The RTL8201CL is a single-port Phyceiver with an MII (Media Independent Interface)/SNI (Serial Network
Interface). It implements all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer
(PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD),
10Base-Tx Encoder/Decoder and Twisted Pair Media Access Unit (TPMAU). A PECL interface is supported to
connect with an external 100Base-FX fiber optical transceiver. The chip is fabricated with an advanced CMOS
process to meet low voltage and low power requirements. Further more, it is developed with on chip Digital Signal
Processing technology to ensure excellent performance under all operating conditions.
The RTL8201CL can be used as a Network Interface Adapter, MAU, CNR, ACR, Ethernet Hub, and Ethernet
Switch. Additionally, it can also be used in any embedded system with an Ethernet MAC that needs a UTP physical
connection or Fiber PECL interface to external 100Base-FX optical transceiver module.
RTL8201CL
2002-03-29
Rev.1.0
5
5. Pin Description
LI:
Latched Input during Power up or Reset
I/O:
Bi-directional input and output
I:
Input
O:
Output
P:
Power
5.1 MII Interface
Symbol
Type
Pin No.
Description
TXC O 7
Transmit Clock:
This pin provides a continuous clock as a timing
reference for TXD[3:0] and TXEN.
TXEN I 2
Transmit Enable:
The input signal indicates the presence of a valid
nibble data on TXD[3:0].
TXD[3:0]
I
3, 4, 5, 6
Transmit Data:
MAC will source TXD[0..3] synchronous with TXC
when TXEN is asserted.
RXC O 16
Receive Clock:
This pin provides a continuous clock reference for
RXDV and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode
and 2.5Mhz in the 10Mbps mode.
COL O 1
Collision Detect:
COL is asserted high when a collision is detected on the
media.
CRS O 23
Carrier Sense:
This pin's signal is asserted high if the media is not in IDEL
state.
RXDV O 22
Receive Data Valid:
This pin's signal is asserted high when received
data is present on the RXD[3:0] lines; the signal is de-asserted at the
end of the packet. The signal is valid on the rising of the RXC.
RXD[3:0]
O
18, 19, 20, 21
Receive Data:
These are the four parallel receive data lines aligned
on the nibble boundaries driven synchronously to the RXC for
reception by the external physical unit (PHY).
RXER/
FXEN
O/LI
24
Receive Error:
if any 5B decode error occurs, such as invalid J/K,
T/R, invalid symbol, this pin will go high.
Fiber/UTP Enable:
During power on reset, this pin status is latched
to determine at which media mode to operate:
1: Fiber mode
0: UTP mode
An internal weak pull low resistor, sets this to the default of UTP mode. It is
possible to use an external 5.1K pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
MDC I
25
Management Data Clock:
This pin provides a clock synchronous to
MDIO, which may be asynchronous to the transmit TXC and receive
RXC clocks. The clock rate can be up to 2.5MHz.
MDIO I/O 26
Management Data Input/Output:
This pin provides the bi-directional
signal used to transfer management information.
5.2 SNI (Serial Network Interface): 10Mbps only
Symbol
Type
Pin No.
Description
COL O 1
Collision Detect
RXD0 O 21
Received Serial Data
CRS O 23
Carrier Sense
RXC O 16
Receive Clock:
Resolved from received data
TXD0 I 6
Transmit Serial Data
TXC O 7
Transmit Clock:
Generate by PHY
TXEN I 2
Transmit Enable:
For MAC to indicate transmit operation
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