RTL8305S
2002/02/19
Rev. 1.2
1
RTL8305S
5-PORT 10/100 MBPS SINGLE CHIP
SWITCH CONTROLLER
1. Features..................................................................................................................................................................................... 2
2. General Description .................................................................................................................................................................. 2
3. Block Diagram .......................................................................................................................................................................... 3
4. Pin Assignments........................................................................................................................................................................ 4
5. Pin Descriptions ........................................................................................................................................................................ 6
5.1 Media Connection Pins ....................................................................................................................................................... 6
5.2 Mode Pins ........................................................................................................................................................................... 6
5.3 Port4 Related Pins............................................................................................................................................................... 7
5.4 LED Pins............................................................................................................................................................................. 8
5.5 Power Pins .......................................................................................................................................................................... 8
5.6 Miscellaneous Pins.............................................................................................................................................................. 8
5.7 Reserved Pins...................................................................................................................................................................... 8
6. Functional Description.............................................................................................................................................................. 9
6.1 Introduction......................................................................................................................................................................... 9
6.2 Switch Core Functional Overview ...................................................................................................................................... 9
6.2.1 Address Search, Learning and Aging........................................................................................................................... 9
6.2.2 Buffer Management.................................................................................................................................................... 10
6.2.3 Data Reception........................................................................................................................................................... 10
6.2.4 Data Forwarding......................................................................................................................................................... 10
6.2.5 Flow Control ...............................................................................................................................................................11
6.2.6 Back-off Algorithm.....................................................................................................................................................11
6.2.7 Inter-Frame Gap ..........................................................................................................................................................11
6.2.8 Illegal Frame ...............................................................................................................................................................11
6.2.9 Broadcast Storm Control.............................................................................................................................................11
6.3 Physical Layer Functional Overview .................................................................................................................................11
6.3.1 Auto-negotiation .........................................................................................................................................................11
6.3.2 10Base-T Transmit Function.......................................................................................................................................11
6.3.3 10Base-T Receive Function ........................................................................................................................................11
6.3.4 Link Monitor ...............................................................................................................................................................11
6.3.5 100Base-TX Transmit Function ................................................................................................................................. 12
6.3.6 100Base-TX Receive Function .................................................................................................................................. 12
6.3.7 Power Saving Mode ................................................................................................................................................... 12
6.4 LED................................................................................................................................................................................... 12
6.5 MII Port............................................................................................................................................................................. 13
6.5.1 General Description ................................................................................................................................................... 13
6.5.2 MII/SNI PHY Mode................................................................................................................................................... 16
6.5.3 MII MAC Mode ......................................................................................................................................................... 16
7. Electrical Characteristics......................................................................................................................................................... 18
7.1 Absolute Maximum Ratings ............................................................................................................................................. 18
7.2 Operating Range ............................................................................................................................................................... 18
7.3 DC Characteristics (0
C<Ta<60C, 3.15V<Vcc<3.45V) ................................................................................................. 18
7.4 AC Characteristics (0
C<Ta<60C, 3.15V<Vcc<3.45V) ................................................................................................. 19
7.5 Digital Timing Characteristics .......................................................................................................................................... 20
7.6 Thermal Data..................................................................................................................................................................... 20
8. Application Information.......................................................................................................................................................... 21
9. System Application Diagram .................................................................................................................................................. 22
10. Mechanical Dimensions........................................................................................................................................................ 23
RTL8305S
2002/02/19
Rev. 1.2
2
1. Features
5-port integrated switch with physical layer and
transceiver for 10Base-T and 100Base-TX with
5-port 10/100M UTP or
4-port 10/100M UTP + 1-port MII/SNI
PHY mode MII/SNI interface for router application
MAC mode MII interface for HomeLAN/100Base-FX
application
1Mbit internal RAM for packet buffer
Internal 1K look-up table entries
25MHz crystal or OSC input
Non-blocking wire-speed reception and transmission
Fully compliant with IEEE 802.3/802.3u
Supports broadcast storm filtering function
Support full duplex 802.3x flow control and half
duplex back-pressure flow control
LED indicators for link/activity, speed, full/half duplex
and collision
LEDs blinking upon reset for LED diagnostics
Unmanaged operation by strapping upon reset
Power saving with cable detection
Low power consumption at 3.3V operating voltage
128-pin PQFP package
2. General Description
The RTL8305S is a highly integrated layer 2 single chip switch controller which incorporates 5 MACs (Media Access
Controller), 5 physical layer transceivers, 1-Mbit SRAM and 1K-entry look-up table into one single chip.
The RTL8305S contains 5 ports, and each one provides support for a 10Base-T (10Mbps) or 100Base-TX (100Mbps) network
connection. The fifth port (port 4) can be configured as a MII/SNI to work with a routing engine, HomePHY or a fiber
transceiver for a 100Base-FX application. And each operation mode can be easily set up by hardware strapping upon restart or
power-on.
The RTL8305S is designed for a stand-alone switch system through hardware strapping upon reset to achieve unmanaged
operation and can be easily integrated with xDSL/Cable modem router. With the least peripheral components and using a
25MHz crystal, the RTL8305S has the best system cost structure. The integrated RTL8305S chip benefits from low power
consumption and ease of use for SOHO 5-port switch or xDSL/Cable router applications.
RTL8305S
2002/02/19
Rev. 1.2
5
' I ' stands for inputs; 'O' stands for outputs; 'A' stands for analog; 'D' stands for digital
Name
Pin No.
Type
Name
Pin No.
Type
RGND
TGND
TXOP[0]
TXON[0]
TVDD
TVDD
TXON[1]
TXOP[1]
TGND
RGND
RXIP[1]
RXIN[1]
RVDD
RVDD
RXIN[2]
RXIP[2]
RGND
TGND
TXOP[2]
TXON[2]
TVDD
TVDD
TXON[3]
TXOP[3]
TGND
RGND
RXIP[3]
RXIN[3]
RVDD
RVDD
RXIN[4]
RXIP[4]
RGND
TGND
TXOP[4]
TXON[4]
TVDD
MVDD
GND
RESET#
TESTCLK
TESTDATA
VDD
X1
X2
P4FLCTRL#
P4SPDSTA#
P4DUPSTA#
P4LNKSTA#
GND
MTXC/MRXC
MTXEN/MRXDV
VDD
MTXD[0]/MRXD[0]
MTXD[1]/MRXD[1]
MTXD[2]/MRXD[2]
MTXD[3]/MRXD[3]
MCOL
MRXC/MTXC
MRXDV/MTXEN
MRXD[0]/MTXD[0]
VDD
MRXD[1]/MTXD[1]
MGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61,
62
63
64
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
DVDD
DGND
I
I
I/O
DVDD
I
O
I
I
I
I
DGND
I/O
O
DVDD
O
O
O
O
I/O
I/O
I
I
DVDD
I
DGND
GND
MRXD[2]/MTXD[2]
MRXD[3]/MTXD[3]
SEL_MIIMAC#
RESERVED
VDD
CK25MOUT
NC
NC
NC
NC
NWAYHALF#
ENFCTRL
ENBKPRS
GND
ENBRDCTRL
NC
NC
NC
NC
NC
NC
VDD
NC
LED_BLNK_TIME
DIS_RST_BLNK#
ENP4LED
NC,
NC
GND
NC
NC
P4MODE[1]
P4MODE[0]
NC
VDD
NC
GND
LED_DUP[0]
LED_ACT[0]
LED_SPD[0]
VDD
LED_DUP[1]
LED_ACT[1]
LED_SPD[1]
LED_DUP[2]
LED_ACT[2]
GND
LED_SPD[2]
VDD
LED_DUP[3]
LED_ACT[3]
LED_SPD[3]
LED_DUP[4]
LED_ACT[4]
LED_SPD[4]
TEST#
GND
AGND
IBREF
AVDD
RVDD
RXIN[0]
RXIP[0]
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DGND
I
I
O
I
DVDD
O
I
I
I
DGND
I
DVDD
I
I
I
DGND
I
I
DVDD
DGND
O
O
O
DVDD
O
O
O
O
O
GND
O
DVDD
O
O
O
O
O
O
O
DGND
AGND
A
AVDD
AVDD
AI
AI
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