GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Rev. 01 -- 11 May 2004
Product data
1.
Description
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive
LOW-output-impedance (100 mA/12
) with LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a
master output enable pin, but also have individual latch timing and output enable
signals. D-type flip-flops and D-type latches enable three modes of data transfer;
Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between
cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The
combination of reduced output swing, reduced input threshold levels and configurable
edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (V
TT
= 1.2 V, V
REF
= 0.8 V) or GTL+ (V
TT
= 1.5 V,
V
REF
= 1.0 V) signalling levels. Port A and the control inputs are compliant with
LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or
GTL+ signal levels, with V
REF
providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA)
and the clock pin (CP) are used to control the data flow through the two 8-bit
transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the
transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A
data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of
CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control
pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be
controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control
(V
ERC
). By adjusting V
ERC
between GND and V
CC
, a designer can adjust the Port B
edge rate to suit an application's load conditions.
The GTL1655 permits true live insertion capability by incorporating:
BIAS V
CC
, to pre-charge outputs and avoid disturbing active data during card
insertion.
I
off
to disable current flow through powered-off I/Os.
Power-up 3-state, which ensures outputs are high-impedance during power-up,
thus preventing bus contention issues. Once V
CC
is above 1.5 V, the power-up
3-state circuit relinquishes control of the outputs to the OE pin. To ensure the
outputs remain 3-state, the OE pin should be tied to V
CC
via a pull-up resistor.
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Product data
Rev. 01 -- 11 May 2004
2 of 23
9397 750 12936
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2.
Features
s
Combination of D-type latches and D-type flip-flops for transceiver operation in
clocked, latched or transparent mode
s
Logic level translation between LVTTL and GTL/GTL+ signals
s
HIGH-drive LOW-output-impedance (100 mA/12
) on Port B
s
Configurable rise and fall times on Port B
s
Supports live insertion (I
off
, Power-up 3-state, and BIAS V
CC
)
s
Bus Hold on Port A inputs
s
Over voltage tolerance on Port A
s
Minimized switching noise through use of distributed V
CC
and GND pins
s
Available in TSSOP64 package
s
Industrial temperature range (
-
40
C to +85
C)
s
ESD protection
x
HBM EIA/JESD22-A114-A exceeds 2000 V
x
CDM EIA/JESD22-C101 exceeds 1000 V
s
Latch-up EIA/JEDS78 exceeds 200 mA
3.
Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
PLH
propagation delay, nAn to nBn
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
-
3.9
-
ns
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
-
4.4
-
ns
propagation delay, nBn to nAn
V
CC
= 3.3 V
-
2.6
-
ns
t
PHL
propagation delay, nAn to nBn
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
-
3.1
-
ns
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
-
2.7
-
ns
propagation delay, nBn to nAn
V
CC
= 3.3 V
-
4.2
-
ns
C
i
input capacitance (control pins)
V
i
= V
CC
or GND
-
3
-
pF
C
I/O
I/O capacitance, Port A
V
i
= V
CC
or GND
-
7
-
pF
I/O capacitance, Port B
V
i
= V
CC
or GND
-
8
-
pF
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Product data
Rev. 01 -- 11 May 2004
3 of 23
9397 750 12936
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
4.
Ordering information
Standard packing quantities and other packaging data are available at
www.philipslogic.com/packaging.
4.1 Ordering options
Table 2:
Ordering information
Type number
Package
Name
Description
Version
GTL1655DGG
TSSOP64
plastic thin shrink small outline package; 64 leads;
body width 6.1 mm
SOT646-1
Table 3:
Part marking
Type number
Topside mark
Temperature range
GTL1655DGG
GTL1655DGG
T
amb
=
-
40
C to +85
C
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Product data
Rev. 01 -- 11 May 2004
4 of 23
9397 750 12936
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.
Pinning information
5.1 Pinning
Fig 1.
TSSOP64 pin configuration.
GTL1655DGG
1OEAB
CP
1OEBA
1LEAB
V
CC
1LEBA
1A1
V
ERC
GND
GND
1A2
1B1
1A3
1B2
GND
GND
1A4
1B3
GND
1B4
1A5
1B5
GND
GND
1A6
1B6
1A7
1B7
V
CC
V
CC
1A8
1B8
2A1
2B1
GND
GND
2A2
2B2
2A3
2B3
GND
GND
2A4
2B4
2A5
2B5
GND
V
REF
2A6
2B6
GND
GND
2A7
2B7
V
CC
2B8
2A8
BIAS_V
CC
GND
2LEAB
2OEAB
2LEBA
2OEBA
002aaa763
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Product data
Rev. 01 -- 11 May 2004
5 of 23
9397 750 12936
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.2 Pin description
Table 4:
Pin description
Symbol
Pin
Description
1OEAB
1
output enable 1A-to-1B (active-LOW)
1OEBA
2
output enable 1B-to-1A (active-LOW)
V
CC
3, 15, 28, 50
DC supply voltage
1A1 to 1A8
4, 6, 7, 9, 11, 13,
14, 16
data inputs/outputs port 1A
GND
5, 8, 10, 12, 18,
21, 24, 26, 30,
39, 44, 47, 53,
57, 60
ground (0 V)
2A1 to 2A8
17, 19, 20, 22,
23, 25, 27, 29
data inputs/outputs port 2A
2OEAB
31
output enable 2A-to-2B (active-LOW)
2OEBA
32
output enable 2B-to-2A (active-LOW)
OE
33
output enable, all I/O pins (active-LOW)
2LEBA
34
latch enable 2B-to-2A
2LEAB
35
latch enable 2A-to-2B
BIAS_V
CC
36
bias supply voltage
2B8 to 2B1
37, 38, 40, 42,
43, 45, 46, 48
data inputs/outputs port 2B
V
REF
41
reference voltage
1B8 to 1B1
49, 51, 52, 54,
55, 56, 58, 59
data inputs/outputs port 1B
V
ERC
61
edge-rate control voltage Port B
1LEBA
62
latch enable 2B-to-2A
1LEAB
63
latch enable 1A-to-1B
CP
64
clock input
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