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these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
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HAF2021(L), HAF2021(S)
Silicon N Channel MOS FET Series
Power Switching
ADE-208-1459A (Z)
Rev.1
Jan. 2002
Description
This FET has the over temperature shutdown capability sensing to the junction temperature. This FET has
the builtin over temperature shutdown circuit in the gate area. And this circuit operation to shutdown
the gate voltage in case of high junction temperature like applying over power consumption, over current
etc.
Features
Logic level operation (6 V Gate drive)
High endurance capability against to the short circuit
Builtin the over temperature shutdown circuit
Latch type shutdown operation (Need 0 voltage recovery)
Outline
LDPAK
1. Gate
2. Drain
3. Source
4. Drain
1
2
3
4
1
2
3
4
Gate resistor
Tempe
rature
Sencing
Circuit
Latch
Circuit
Gate
Shut
down
Circuit
D
S
G
HAF2021(L), HAF2021(S)
Rev.1, Jan. 2002, page 3 of 11
Electrical Characteristics
(Ta = 25C)
Item
Symbol
Min Typ Max Unit Test
Conditions
Drain current
I
D1
90
--
-- A V
GS
= 6 V, V
DS
= 10 V
Drain current
I
D2
--
-- 10 mA
V
GS
= 1.2 V, V
DS
= 10 V
Drain to source breakdown
voltage
V
(BR)DSS
60
--
-- V I
D
= 10 mA, V
GS
= 0
Gate to source breakdown voltage V
(BR)GSS
16
--
-- V I
G
= 300
A, V
DS
= 0
Gate to source breakdown voltage V
(BR)GSS
2.5
--
-- V I
G
= 100
A, V
DS
= 0
Gate to source leak current
I
GSS1
--
-- 100
A V
GS
= 6 V, V
DS
= 0
I
GSS2
--
-- 50
A V
GS
= 3.5 V, V
DS
= 0
I
GSS3
--
-- 1
A V
GS
= 1.2 V, V
DS
= 0
I
GSS4
--
--
100
A V
GS
= 2.4 V, V
DS
= 0
Input current (shut down)
I
GS(op)1
-- 0.6 -- mA
V
GS
= 6 V, V
DS
= 0
I
GS(op)2
-- 0.35
-- mA
V
GS
= 3.5 V, V
DS
= 0
Zero gate voltage drain current
I
DSS
--
-- 10
A V
DS
= 60 V, V
GS
= 0
Gate to source cutoff voltage
V
GS(off)
2.2 -- 3.4 V I
D
= 1 mA, V
DS
= 10 V
Static drain to source on state
resistance
R
DS(on)
-- 8 12 m
I
D
= 25 A, V
GS
= 10 V
Note3
Static drain to source on state
resistance
R
DS(on)
-- 9.5 15 m
I
D
= 25 A, V
GS
= 6 V
Note3
Forward transfer admittance
|y
fs
| 15 39 -- S I
D
= 25 A, V
DS
= 10 V
Note3
Output capacitance
Coss
-- 1450
-- pF V
DS
= 10 V , V
GS
= 0
f = 1 MHz
Turn-on delay time
t
d(on)
-- 20 -- s I
D
= 25 A, V
GS
= 10 V
Rise time
t
r
-- 75 -- s R
L
= 1.2
Turn-off delay time
t
d(off)
-- 3 -- s
Fall time
t
f
-- 2.6 -- s
Bodydrain diode forward voltage V
DF
-- 0.9 -- V I
F
= 50 A, V
GS
= 0
Bodydrain diode reverse
recovery time
t
rr
-- 110
-- ns I
F
= 50 A, V
GS
= 0
diF/ dt =50 A/s
Over load shut down operation
time
Note4
t
os
-- 0.8 -- ms V
GS
= 6 V, V
DD
= 16 V
Notes: 3. Pulse test
4. Including the junction temperature rise of the over loaded condition.
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