Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

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Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

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these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
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Notes regarding these materials

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contained therein.

HD404654 Series

4-Bit Single-Chip Microcomputer

Rev. 7.0

Sept. 1999

Description

The HD404654 Series is a member of the HMCS400-series of microcomputers designed to increase
program productivity with large-capacity memory. Each microcomputer has a high-precision dual-tone
multi-frequency (DTMF) generator, three timers, serial interface, voltage comparator, and input capture
circuit.

The HD404654 Series includes three chips: the HD404652 with 2 k-word ROM; the HD404654 with 4 k-
word ROM; and the HD4074654 with 4 k-word PROM (ZTAT

version).

The HD4074654 is a PROM version (ZTAT

microcomputer). A program can be written to the PROM by

a PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The ZTAT

version is 27256-compatible.)

ZTAT

: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd.

Features

27 I/O pins and 5 dedicated input pins

10 high-current output pins: Six 15-mA sinks and four 10-mA sources

Three timer/counters

Eight-bit input capture circuit

Two timer outputs (including two PWM outputs)

One event counter input (including one double-edge function)

One clock-synchronous 8-bit serial interface

Voltage comparator (2 channels)

On-chip DTMF generator (f

OSC

= 400 kHz, 800 kHz, 2 MHz, 3.58 MHz or 4 MHz)

Built-in oscillators

Main clock: Ceramic or crystal oscillator (an external clock is also possible)

Six interrupt sources

Two by external sources

Four by internal sources

Subroutine stack up to 16 levels, including interrupts

HD404654 Series

Pin Arrangement

RD /COMP
RD /COMP

TONEC
TONER

ref

RE /VC

ref

TEST

OSC
OSC

RESET

GND

D
D
D
D
D
D
D
D
D
D

0 0

1 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

DP-42S

V
SEL
R4 /SO
R4 /SI
R4 /

SCK

R4 /EVND
R3
R3 /TOD
R3 /TOC
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0 /

INT

D /

INT

D /

STOPC

3 1

2 1

1 1

0 1

13 0

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

FP-44A

/VC

ref

TEST

OSC

RESET

GND

R4 /EVND
R3
R3 /TOD
R3 /TOC
R3
R2
R2
R2
R2
R1
R1

D /

STOPC

D /

INT

R0 /

INT

13 0

0 1

ref

TONER

TONEC

RD /COMP

SEL

R4 /SO

R4 /SI

R4 /

SCK

1 1

0 0

3 1

2 1

1 1

(top view)

HD404654 Series

Pin Description

Pin Number

Item

Symbol

DP-42S

FP-44A

I/O

Function

Power supply

Applies power voltage

GND

Connected to ground

Test

TEST

Used for factory testing only: Connect this pin to
V

Reset

RESET

Resets the MCU

Oscillator

OSC

Port

1221

716

I/O

Input/output pins addressed by individual bits;
pins D

are high-current sink pins that can

each supply up to 15 mA, D

are large-

current source pins that can each supply up to 10
mA

, D

22, 23

17, 18

Input pins addressable by individual bits

2440

1921,
2336

I/O

Input/output pins addressable in 4-bit units

, RD

, RE

1, 2, 6

39, 40,1

Input pins addressable in 4-bit units

Interrupt

INT

23, 24

18, 19

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active
mode

Serial

SCK

I/O

Serial clock input/output pin

Serial receive data input pin

Serial transmit data output pin

Timer

TOC, TOD

34, 35

30, 31

Timer output pins

EVND

Event count input pins

DTMF

TONER

Output pin for DTMF row signals

TONEC

Output pin for DTMF column signals.

ref

Reference voltage pin for DTMF signals

Voltage condition is V

ref

GND.

Comparator

COMP

1, 2

39, 40

Analog input pins for voltage comparator

ref

Reference voltage pin for inputting the threshold
voltage of the analog input pin.

Division rate

SEL

Input pin for selecting system clock division rate
rate after

RESET

input or after stop mode

cancellation.
1/4 division rate: Connect it to V

1/32 division rate: Connect it to GND

HD404654 Series

Block Diagram

RESET

TEST

STOPC

OSC

SEL

GND

System control

RAM

(512

4 bits)

W (2 bits)

X (4 bits)

SPX (4 bits)

Y (4 bits)

SPY (4 bits)

(1 bit)

A (4 bits)

B (4 bits)

SP (10 bits)

Instruction

decoder

PC (14 bits)

ROM

(4,096

10 bits)

(2,048

10 bits)

Internal address bus

Internal data bus

External
interrupt

Timer

SCI1

Compa-

rator

DTMF

D port

R0 port

R1 port

R2 port

R3 port

R4 port

RD port

RE port

: Data bus

: Signal line

ALU

Source

Sink

High
current
pins

CPU

D
D
D
D
D
D
D
D
D
D

D
D

0
1
2
3

0
1

TOC

EVND

TOD

INT

SCK

ref

COMP
COMP

ref

TONER
TONEC

Internal data bus

HD404654 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

$000F

$07FF

$003F

$0040

Vector address

Zero-page subroutine

(64 words)

2
3

4
5

6
7
8
9

10
11
12

13
14
15

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(Jump to

RESET

STOPC

routine)

JMPL instruction

(Jump to

INT

routine)

JMPL instruction

(Jump to timer A routine)

JMPL instruction

(Jump to timer D, routine)

JMPL instruction

(Jump to

INT

routine)

JMPL instruction

(Jump to serial 1 routine)

JMPL instruction

(Jump to timer C, routine)

Not used

$0010

Program & pattern

(HD404652)

2047

4095

$0FFF

Program & pattern

(HD404654, HD4074654)

Figure 1 ROM Memory Map

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000$07FF (HD404652), $0000$0FFF (HD404654, HD4074654)): Used for
program coding.

RAM Memory Map

The MCU contains a 512-digit

4-bit RAM area consisting of a memory register area, a data area, and a

stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.

HD404654 Series

$000

576

960

1023

$040
$050

4
5
6
7

12
13
14

8
9

16
17

18
19
20

$003

$004

$005

$006

$007

$008
$009

$00B

$00C

$00D

$00E
$00F

$010

$011
$012

$013
$014

$020
$023

$032
$033

$034
$035

$03F

$00E

$00F

R/W

W
W

W
W
W
W

W
W
W

R/W

R/W
R/W

$3C0

$240

RAM-mapped registers

Memory registers (MR)

Not used

Data (432 digits)

Not used

Stack (64 digits)

Interrupt control bits area

Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A

Miscellaneous register
Timer mode register C1

Timer C

Timer mode register D2

Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR

Port D to D DCR
Port D to D DCR
Port D and D DCR

Not used

Timer read register C lower

Timer read register C upper

Timer write register C lower

Timer write register C upper

$090

R:
W:
R/W:

Read only
Write only
Read/Write

$011

$012

17
18

Timer read register D lower

Timer read register D upper

Timer write register D lower

Timer write register D upper

144

Timer mode register D1

R/W
R/W

Timer D

Timer mode register C2

$015

$016

Compare data register

$017

$024

$025

$026

$027

$028

$029

$02A

$02B

24
25

$018

$019
$01A
$01B

$01F

$3FF

Compare enable register

W
W

44
45
46
47

Port mode register B
Port mode register C

Detection edge select register 2

Serial mode register 1B

System clock select register 1

Not used

Port R4 DCR

W
W
W

$02C
$02D
$02E
$02F

$031

$030

48
49
50
51
52

Two registers are mapped
on the same area.

R/W
R/W

(PMRA)

(SM1A)

(SR1L)

(SR1U)

(TMA)

(MIS)

(TMC1)

(TRCL/TWCL)

(TRCU/TWCU)

(TMD1)

(TRDL/TWDL)

(TRDU/TWDU)

(TMC2)
(TMD2)

(CDR)

(CER)

(TGM)

(TGC)

(PMRB)

(PMRC)

(SM1B)

(SSR1)
(SSR2)

(ESR2)

(DCD0)
(DCD1)
(DCD2)

(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)

Not used

(TRCL)

(TRCU)

(TRDL)

(TRDU)

(TWCL)

(TWCU)

(TWDL)

(TWDU)

TG mode register

TG control register

System clock select register 2

Not used

Figure 2 RAM Memory Map

HD404654 Series

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01A, $024$034)

This area is used as mode registers and data registers for external interrupts, serial interface 1,
timer/counters, and the comparator, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.

This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits
can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Data Area ($090$23F): 432 digits from $090 to $23F.

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404654 Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMS1

(IM of serial

interface 1)

IFS1

(IF of serial
interface 1)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

$020

$021

WDON

(Watchdog

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

Not used

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

ICSF
ICEF

RAME

RSP

WDON

Not used

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

If the TM or TDM instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404654 Series

$000

$003

PMRA $004

SM1A $005

SR1L $006

SR1U $007

TMA $008

MIS $00C

TMC1 $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

TMD1 $010

TRDL/TWDL $011

TRDU/TWDU $012

$013

TMC2 $014

TMD2 $015

$016

CDR $017

CER $018

TGM $019

TGC $01A

$020

$023

PMRB $024

PMRC $025

$026

ESR2 $027

SM1B $028

SSR1 $029

SSR2 $02A

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

$03F

Bit 3

Bit 2

Bit 1

Interrupt control bits area

: Not used

/SI

/SO

Serial transmit clock speed selection 1

Serial data register 1 (lower digit)

Serial data register 1 (upper digit)

Clock source selection (timer A)

PMOS control

Interrupt frame period selection

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Clock source selection (timer D)

Timer D register (lower digit)

Timer D register (upper digit)

Timer-C output mode selection

Timer-D output mode selection

Result of each analog input comparison

/EVND

EVND detection edge selection

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

STOPC

INT

SCK

Bit 0

System clock selection

TONEC output frequency

TONER output frequency

DTMF enable

1. Auto-reload on/off
2. Pull-up MOS control
3. Input capture selection
4. Comparator switch
5. Port/comparator selection
6. TONEC output control
7. TONER output control
8. SO

output level control in idle states

9. Serial clock source selection 1
10. System clock selection

Notes:

Figure 5 Special Function Register Area

HD404654 Series

Memory registers

65
66
67
68
69
70
71

73
74
75
76
77
78
79

$040

$041
$042

$043

$044

$045
$046

$047
$048
$049

$04A
$04B
$04C
$04D
$04E
$04F

960

$3C0

1023

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404654 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 7 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

HD404654 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN
instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

Reset

The MCU is reset by inputting a high-level voltage to the

RESET pin. At power-on or when stop mode is

cancelled,

RESET must be high for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be high for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

Interrupts

The MCU has 6 interrupt sources: Two external signals (

INT

), three timer/counters (timers A, C,

and D), and one serial interface (serial 1).

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

HD404654 Series

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404654 Series

Table 1 Initial Values After MCU Reset

Item

Abbr.

Initial Value Contents

Program counter

(PC)

$0000

Indicates program execution point
from start address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt
flags/mask

Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0
DCD2)

All bits 0

Turns output buffer off (to high
impedance)

(DCR0
DCR4)

All bits 0

Port mode register A

(PMRA)

- - 00

Refer to description of port mode
register A

Port mode register B

(PMRB)

- - - 0

Refer to description of port mode
register B

Port mode register C
bits 3, 1, 0

(PMRC3,
PMRC1,
PMRC0)

000 -

Refer to description of port mode
register C

Detection edge select
register 2

(ESR2)

00 - -

Disables edge detection

Timer/counters,
serial interface

Timer mode register A (TMA)

- 000

Refer to description of timer mode
register A

Timer mode register
C1

(TMC1)

0000

Refer to description of timer mode
register C1

Timer mode register
C2

(TMC2)

- 000

Refer to description of timer mode
register C2

Timer mode register
D1

(TMD1)

0000

Refer to description of timer mode
register D1

Timer mode register
D2

(TMD2)

0000

Refer to description of timer mode
register D2

Serial mode register
1A

(SM1A)

0000

Refer to description of serial mode
register 1A

Serial mode register
1B

(SM1B)

- - X0

Refer to description of serial mode
register 1B

Prescaler S

(PSS)

$000

Timer counter A

(TCA)

$00

HD404654 Series

Item

Abbr.

Initial Value Contents

Timer/counters,
serial interface

Timer counter C

(TCC)

$00

Timer counter D

(TCD)

$00

Timer write register C

(TWCU,
TWCL)

$X0

Timer write register D

(TWDU,
TWDL)

$X0

Octal counter

000

Comparator

Compare enable
register

(CER)

0 - 00

Refer to description of voltage
comparator

Bit register

Watchdog timer on flag (WDON)

Refer to description of timer C

Input capture status
flag

(ICSF)

Refer to description of timer D

Input capture error flag (ICEF)

Refer to description of timer D

Others

Miscellaneous register (MIS)

00 - -

Refer to description of operating
modes, and oscillator circuit

System clock select
register 1 bits 1, 0

(SSR11,
SSR10)

Refer to description of operating
modes, and oscillator circuit

System clock select
register 2

(SSR2)

- 0 - -

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404654 Series

Item

Abbr.

Status After
Cancellation of Stop
Mode by

STOPC

Input

Status After
Cancellation of Stop
Mode by MCU Reset

Status After all
Other Types of
Reset

Carry flag

(CA)

Pre-stop-mode values are not guaranteed; values
must be initialized by program

Pre-MCU-reset values
are not guaranteed;
values must be
initialized by program

Accumulator

(A)

B register

(B)

W register

(W)

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register (SRL, SRU)

RAM

Pre-stop-mode values are retained

RAM enable flag

(RAME)

Port mode register
1 bit 2

(PMRC12)

Pre-stop-mode values
are retained

System clock
select register 1 bit
3

(SSR13)

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET

STOPC*

$0000

INT

$0002

INT

$0004

Timer A

$0006

Not used

$0008

Timer C

$000A

Timer D

$000C

Serial 1

$000E

Note:

The

STOPC

interrupt request is valid only in stop mode.

HD404654 Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer C

Timer D

Serial 1

IF0 ·

IM0

IF1 ·

IM1

IFTA ·

IMTA

IFTC ·

IMTC

IFTD ·

IMTD

IFS1 ·

IMS1

Note:

Can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.

Stacking

Figure 9 Interrupt Processing Sequence

HD404654 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

): Two external interrupt signals.

External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set at the falling edge of
signals input to

INT

and

INT

as listed in table

Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001)

IF0, IF1

Interrupt Request

Yes

External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the
corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0, IM1: $000, $001)

IM0, IM1

Interrupt Request

Enabled

Disabled (Masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.

HD404654 Series

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (Masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 9.

Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 10.

Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (Masked)

Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
11.

Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)

IFTD

Interrupt Request

Yes

Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 12.

HD404654 Series

Operating Modes

The MCU has three operating modes as shown in table 15. The operations in each mode are listed in tables
16 and 17. Transitions between operating modes are shown in figure 11.

Table 15 Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Activation method

RESET

cancellation,

interrupt request,

STOPC

cancellation

in stop mode

SBY instruction

STOP instruction

Status

System oscillator

Stopped

Cancellation
method

RESET

input,

STOP/SBY
instruction

RESET

input,

interrupt request

RESET

input,

STOPC

input in stop

mode

Note:

OP implies in operation

Table 16 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Standby Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer C

Reset

Timer D

Reset

Serial 1

Reset

DTMF

Reset

Comparator

Reset

Stopped

I/O

Reset

Retained

Notes: OP implies in operation

Output pins are at high impedance.

HD404654 Series

Table 17 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode

Stop Mode

Active Mode

Retained

High impedance

Input enabled

, RD

, RE

Input enabled

R0R4

Retained or output of
peripheral functions

High impedance

Input enabled

Reset by

RESET

input or

by watchdog timer

OSC

CPU

PER

Oscillate
Stop

cyc

OSC

CPU

PER

Oscillate
f

cyc

OSC

CPU

PER

Standby mode

(TMA3 = 0)

SBY

Interrupt

OSC

cyc

Main oscillation
frequency
f /4 or or f /32
(hardware selectable)

OSC

System clock
Clock for other
peripheral functions

Active
mode

CPU

PER

RESET1

RESET2

RAME = 0

RAME = 1

STOPC

STOP

OSC

Stop
Stop
Stop

Stop mode

Figure 11 MCU Status Transitions

Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC

and OSC

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a

RESET input or an interrupt request. If it is terminated by RESET input,

the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 12.

HD404654 Series

Standby

Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop

Yes

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

RESET

= 0?

IF0 ·

IM0

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTC ·

IMTC

= 1?

IFTD ·

IMTD

= 1?

Yes

IFS1 ·

IMS1

= 1?

Stop

Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop

RESET

= 0?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Execute

next instruction

Figure 12 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops. The MCU enters

stop mode if the STOP instruction is executed in active mode.

Stop mode is terminated by a

RESET input or a STOPC input as shown in figure 13. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

HD404654 Series

Stop Mode Cancellation by

STOPC: The MCU enters active mode from stop mode by inputting STOPC

as well as by

RESET. In either case, the MCU starts instruction execution from the starting address

(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by

STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0;

when cancelled by

STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop

mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop

mode has been cancelled by

STOPC (for example, when the RAM contents before entering stop mode are

used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the
beginning of the program.

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

STOPC

RESET

Figure 13 Timing of Stop Mode Cancellation

HD404654 Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 17. As shown in table 18, a ceramic
oscillator or crystal oscillator can be connected to OSC

and OSC

. The system oscillator can also be

operated by an external clock. Bit 1 (SSR11) of system clock select register 1 (SSR1: $029) and bit 2
(SSR22) of system clock select register 2 (SSR2: $02A) must be selected according to the frequency of the
oscillator connected to OSC

and OSC

(figure 18).

Note:

If the SSR10, SSR11 and SSR22 setting does not match the oscillator frequency, the DTMF
generator will malfunction.

After

RESET input or after stop mode has been cancelled, the division ratio of the system clock can be

selected as 1/4 or 1/32 by setting the SEL pin level.

1/4 division ratio: Connect SEL to V

1/32 division ratio: Connect SEL to GND.

OSC

System

oscillator

1/4 or

1/32

division

circuit

Timing

generator

circuit

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

cyc

OSC

CPU

PER

Note:

1/4 or 1/32 division ratio can be selected by pin SEL.

Figure 17 Clock Generation Circuit

HD404654 Series

Bit

Initial value

Read/Write

Bit name

Not used

SSR10

SSR11

System clock select register 1 (SSR1: $029)

System clock selection

400 kHz

800 kHz

2 MHz

4 MHz

3.58 MHz

SSR10

SSR11

SSR22

: Don't care

Figure 18 System Clock Select Register 1

Bit

Initial value

Read/Write

Bit name

Not used

SSR22

Not used

System clock select register 2 (SSR2: $02A)

SSR22

System clock selection

Selected from 400 kHz, 800 kHz,
2 MHz, 4 MHz

Note:

3.58 MHz

Refer to system clock select register 1 (SSR1) of figure 18.

Figure 19 System Clock Select Register 2

HD404654 Series

Table 18 Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic
oscillator

GND

Ceramic oscillator: CSB400P22
(Murata), CSB400P (Murata)
R

= 1 M

20%

= C

= 220 pF

Ceramic oscillator: CSB800J122
(Murata), CSB800J (Murata)
R

= 1 M

20%

= C

= 220 pF

Ceramic oscillator: CSA2.00MG
(Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Ceramic oscillator: CSA4.00MG
(Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Ceramic oscillator: CSA3.58MG
(Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of

the board, the user should consult with the ceramic oscillator manufacturer to determine the
circuit parameters.

2. Wiring among OSC

, OSC

, and elements should be as short as possible, and must not cross

other wiring (see figure 20).

HD404654 Series

Input/Output

The MCU has 27 input/output pins (D

, R0

) and 5 input pins (D

, D

13,

R D

, RD

, RE

). The

features are described below.

A maximum current of 15 mA is allowed for each of the pins D

to D

with a total maximum current of

less than 105 mA. In addition, D

can each act as a 10-mA maximum current source.

Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial
interface. For these pins, the peripheral function setting is done prior to the D or R port setting.
Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection
are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R4

/SO

pin can be set to NMOS open-

drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.

Pins D

have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs,

which can be individually turned on or off by software.

The I/O buffer configuration is shown in figure 21 and 22, programmable I/O circuits are listed in table 19,
and I/O pin circuit types are shown in table 20.

Table 19 Programmable I/O Circuits

MIS3 (Bit 3 of MIS)

DCD, DCR

PDR

CMOS buffer

PMOS --

NMOS --

Pull-up MOS

Pull-down MOS

Note:

-- indicates off status.

HD404654 Series

I/O Pin Type

Circuit

Pins

Peripheral
function pins

Input/
output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Peripheral
function pins

Output
pins

Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

MIS2

Pull-up control signal

Output data

HLT

MIS3

TOC, TOD

Input
pins

Input data

INT

, EVND

HLT

MIS3

PDR

INT

, EVND

Input data

INT

STOPC

INT

STOPC

Note:

The MCU is reset in stop mode, and peripheral function selection is cancelled. The

HLT

signal

becomes low, and input/output pins enter high-impedance state.

D Port (D

): Consist of 10 input/output pins and 2 input pins addressed by one bit. D

are high-

current sources, D

are large-current sinks, and D

and D

are input-only pins.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D

are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0DCD2:
$02C$02E) that are mapped to memory addresses (figure 23).

HD404654 Series

Pins D

and D

are multiplexed with peripheral function pins

STOPC and I

, respectively. The

peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 24).

R Ports (R0

, R1

R4

, RD

, RE

): 17 input/output pins and 3 input pins addressed in 4-bit units.

Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB
instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the
output buffers of the R ports are controlled by R-port data control registers (DCR0DCR4: $030$034) that
are mapped to memory addresses (figure 23).

Pin R0

is multiplexed with peripheral pin

INT

. The peripheral function mode of this pins is selected by

bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 25).

Pins R3

are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function

modes of these pins are selected by bits 02 (TMC20TMC22) of timer mode register C2 (TMC2: $014),
and bits 03 (TMD20TMD23) of timer mode register D2 (TMD2: $015) (figures 26, and 27).

Pin R4

is multiplexed with peripheral pin EVND. The peripheral function mode of this pins is selected by

bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 24).

Pins R4

are multiplexed with peripheral pins

SCK

, SI

, and SO

, respectively. The peripheral

function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 28 and 29.

Ports RD

and RD

are multiplexed with peripheral function pins COMP

and COMP

, respectively. The

function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018), as
shown in figure 30.

Port RE

is multiplexed with peripheral function pin VC

ref

. While functioning as VC

ref

, do not use this pin

as an R port at the same time, otherwise, the MCU may malfunction.

Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D

and D

. The on/off status of

all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin--enabling on/off control of that pin alone (table 19 and figure 31).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

their pull-up MOS transistors or by resistors of about 100 k

or pulled down to GND by their pull-down

MOS transistors.

HD404654 Series

DCD0, DCD1

Bit

Initial value

Read/Write

Bit name

DCD03,

DCD13

DCD02,

DCD12

DCD00,

DCD10

DCD01,

DCD11

Data control register

(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034)

DCD2

Bit

Initial value

Read/Write

Bit name

Not used

DCD20

DCD21

DCR0

Bit

Initial value

Read/Write

Bit name

Not used

DCR00

Not used

DCR1 to DCR4

Bit

Initial value

Read/Write

Bit name

DCR13

DCR43

DCR12

DCR42

DCR10

DCR40

DCR11

DCR41

Correspondence between ports and DCD/DCR bits

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR4

Off (high-impedance)

All Bits

CMOS Buffer On/Off Selection

Register Name

Bit 3

Bit 2

Bit 1

Bit 0

Figure 23 Data Control Registers (DCD, DCR)

HD404654 Series

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

Not used

PMRC1

Port mode register C (PMRC: $025)

PMRC1

/EVND mode selection

EVND

PMRC2

STOPC

PMRC3

INT

mode selection

INT

STOPC

mode selection

Note:

PMRC2 is reset to 0 only by

RESET

input. When

STOPC

is input in stop

mode, PMRC2 is not reset but retains its value.

Figure 24 Port Mode Register C (PMRC )

Bit

Initial value

Read/Write

Bit name

Not used

PMRB0

Not used

Port mode register B (PMRB: $024)

PMRB0

INT

mode selection

INT

Figure 25 Port Mode Register B (PMRB)

HD404654 Series

Bit

Initial value

Read/Write

Bit name

SM1A3

SM1A2

SM1A0

SM1A1

Serial mode register 1A (SM1A: $005)

Output

Input

Prescaler

System clock

External clock

2048

512

128

Prescaler
division
ratio

SM1A2

SM1A0

SM1A1

Clock source

SM1A3

SCK

mode selection

SCK

Figure 28 Serial Mode Register 1A (SM1A)

PMRA0

/SO

mode selection

Bit

Initial value

Read/Write

Bit name

Not used

PMRA0

PMRA1

Port mode register A (PMRA: $004)

PMRA1

/SI

mode selection

Not used

Figure 29 Port Mode Register A (PMRA)

HD404654 Series

Bit

Initial value

Read/Write

Bit name

CER3

Not used

CER0

CER1

Compare enable register (CER: $018)

CER1

Analog input pin selection

COMP

Not used

CER3

Digital input mode:
RD /COMP

and RD /COMP

operate as an R port.

Digital/Analog selection

Analog input mode:
RD /COMP

and RD /COMP

operate as analog input.

CER0

Figure 30 Compare Enable Register

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

CMOS buffer
on/off selection
for pin R4

/SO

Miscellaneous register (MIS: $00C)

Off

MIS3

Pull-up MOS
on/off selection

Off

Not used

Figure 31 Miscellaneous Register (MIS)

HD404654 Series

Prescalers

The MCU has the following prescaler S.

The prescaler operating conditions are listed in table 21, and the prescaler output supply is shown in figure
32. The timer AD input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset.

Table 21 Prescaler Operating Conditions

Prescaler

Input Clock

Reset Condition

Stop Conditions

Prescaler S

System clock

MCU reset

MCU reset, stop mode

System

clock

Prescaler S

Timer A

Timer C

Timer D

Serial 1

Figure 32 Prescaler Output Supply

HD404654 Series

Timers

The MCU has three timer/counters (A, C, and D).

Timer A: Free-running timer

Timer C: Multifunction timer

Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are
listed in table 22. The operating modes are selected by software.

Table 22 Timer Functions

Functions

Timer A

Timer C

Timer D

Clock source

Prescaler S

Available

External event

Available

Timer functions

Free-running

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer outputs

Toggle

Available

0 output

Available

1 output

Available

PWM

Available

Note:

-- means not available.

HD404654 Series

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

The block diagram of timer A is shown in figure 33.

System
clock

Selector

Prescaler S (PSS)

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

Figure 33 Block Diagram of Timer A

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 34.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

Operating mode

Timer A mode

TMA1

TMA2

TMA0

Source
prescaler

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

Input clock
frequency

Not used

Note: Timer counter overflow output period (seconds) = input clock period (seconds)

256.

Figure 34 Timer Mode Register A (TMA)

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (toggle, 0, 1, and PWM outputs)

The block diagram of timer C is shown in figure 35.

HD404654 Series

Watchdog on

flag (WDON)

System
reset signal

Timer C interrupt

flag (IFTC)

Timer output

control logic

Timer read register CU (TRCU)

Timer output
control

Timer read
register CL

(TRCL)

Clock

Timer counter C

(TCC)

Selector

System
clock

Prescaler S (PSS)

Overflow

Internal data bus

Timer write

(TWCU)

Timer write
register CL

(TWCL)

Timer mode

(TMC1)

Timer mode

(TMC2)

Free-running
/reload control

Watchdog timer

control logic

TOC

PER

128

512

1024

2048

Figure 35 Block Diagram of Timer C

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

HD404654 Series

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.

Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R3

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer C has reached $FF. By using this function and the reload timer function, clock signals
can be output at a required frequency for the buzzer. The output waveform is shown in figure 36.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output

function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 36.

0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer C has reached $FF. Note that this function must be used only when the output level is high.

1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer

C has reached $FF. Note that this function must be used only when the output level is low.

HD404654 Series

(N + 1)

256

(256 N)

TMC13 = 0

The waveform is always fixed low when N = $FF.
T:
N:

TMC13 = 1

Input clock period to counter (figures 37 and 44)
The value of the timer write register

Notes:

TMD13 = 0

TMD13 = 1

256 clock cycles

Free-running timer

Toggle output waveform (timers C, and D)

PWM output waveform (timers C and D)

(256 N)

clock cycles

(256 N)

clock cycles

Reload timer

Figure 36 Timer Output Waveform

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C1 (TMC1: $00D)

Timer mode register C2 (TMC2: $014)

Timer write register C (TWCL: $00E, TWCU: $00F)

Timer read register C (TRCL: $00E, TRCU: $00F)

Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 37.
It is reset to $0 by MCU reset.

HD404654 Series

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMC13

TMC12

TMC10

TMC11

Timer mode register C1 (TMC1: $00D)

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC12

TMC10

TMC11

TMC13

Free-running/reload timer selection

Free-running timer

Reload timer

Input clock period

Figure 37 Timer Mode Register C1 (TMC1)

Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 38. It is reset to $0 by MCU reset.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Inhibited

PWM output

TMC20

Figure 38 Timer Mode Register C2 (TMC2)

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and an upper digit (TWCU) as shown in figures 39 and 40. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.

Timer C is initialized by writing to timer write register C (TWCL: $00E, TWCU: $00F). In this case,
the lower digit (TWCL) must be written to first, but writing only to the lower digit does not change the
timer C value. Timer C is initialized to the value in timer write register C at the same time the upper
digit (TWCU) is written to. When timer write register C is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer C.

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 39 Timer Write Register C Lower Digit (TWCL)

HD404654 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 40 Timer Write Register C Upper Digit (TWCU)

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures
41 and 42. The upper digit (TRCU) must be read first. At this time, the count of the timer C upper digit
is obtained, and the count of the timer C lower digit is latched to the lower digit (TRCL). After this, by
reading TRCL, the count of timer C when TRCU is read can be obtained.

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 41 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 42 Timer Read Register C Upper Digit (TRCU)

Timer D

Timer D Functions: Timer D has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, 1, and PWM outputs)

Input capture timer

The block diagram for each operation mode of timer D is shown in figures 43 (A) and (B).

HD404654 Series

Selector

128

512

2048

PER

Input capture

status flag (ICSF)

Input capture

error flag (ICEF)

Timer D interrupt

request flag (IFTD)

Error

control

logic

Edge

detection

logic

Timer read

(TRDU)

Timer read
register DL

(TRDL)

Read signal

Clock

Timer counter D

(TCD)

Overflow

System
clock

Edge detection control

Prescaler S (PSS)

Input capture

timer control

Timer mode

(TMD1)

Timer mode

(TMD2)

Edge detection

selection register

2 (ESR2)

EVND

Internal data bus

Figure 43 (B) Block Diagram of Timer D (in Input Capture Timer Mode)

Timer D Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

HD404654 Series

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R4

/EVND must be set to EVND by port

mode register C (PMRC: $025).

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t

cyc

or longer.

Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.

Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R3

/TOD is set to TOD. The output from TOD is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-C's toggle output.

0 output: The operation is basically the same as that of timer-C's 0 output.

1 output: The operation is basically the same as that of timer-C's 1 output.

PWM output: The operation is basically the same as that of timer-C's PWM output.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).

When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.

By selecting the input capture operation, pin R3

/TOD is set to R3

and timer D is reset to $00.

HD404654 Series

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.

Timer mode register D1 (TMD1: $010)

Timer mode register D2 (TMD2: $015)

Timer write register D (TWDL: $011, TWDU: $012)

Timer read register D (TRDL: $011, TRDU: $012)

Port mode register C (PMRC: $025)

Detection edge select register 2 (ESR2: $027)

Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44.
It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Bit

Initial value

Read/Write

Bit name

TMD13

TMD12

TMD10

TMD11

Timer mode register D1 (TMD1: $010)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMD12

TMD10

TMD11

Input clock period and

input clock source

/EVND (external event input)

TMD13

Free-running/reload timer selection

Free-running timer

Reload timer

Figure 44 Timer Mode Register D1 (TMD1)

Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 45. It is reset to $0 by MCU reset.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Inhibited

PWM output

Input capture (R3

port)

TMD23

Don't care

Figure 45 Timer Mode Register D2 (TMD2)

Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and an upper digit (TWDU) as shown in figures 46 and 47. The operation of timer write
register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F).

Bit

Initial value

Read/Write

Bit name

TWDL3

TWDL2

TWDL0

TWDL1

Timer write register D (lower digit) (TWDL: $011)

Figure 46 Timer Write Register D Lower Digit (TWDL)

HD404654 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWDU3

Undefined

TWDU2

Undefined

TWDU0

Undefined

TWDU1

Timer write register D (upper digit) (TWDU: $012)

Figure 47 Timer Write Register D Upper Digit (TWDU)

Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and an upper digit (TRDU) as shown in figures 48 and 49. The operation of timer read register
D is basically the same as that of timer read register C (TRCL: $00E, TRCU: $00F).

When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.

Bit

Initial value

Read/Write

Bit name

Undefined

TRDL3

Undefined

TRDL2

Undefined

TRDL0

Undefined

TRDL1

Timer read register D (lower digit) (TRDL: $011)

Figure 48 Timer Read Register D Lower Digit (TRDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDU3

Undefined

TRDU2

Undefined

TRDU0

Timer read register D (upper digit) (TRDU: $012)

Undefined

TRDU1

Figure 49 Timer Read Register D Upper Digit (TRDU)

Port mode register C (PMRC: $025): Write-only register that selects R4

/EVND pin function as shown

in figure 50. It is reset to $0 by MCU reset.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

Not used

PMRC1

/EVND mode selection

EVND

Port mode register C (PMRC: $025)

PMRC3

INT

mode selection

INT

PMRC2

STOPC

mode selection

STOPC

Figure 50 Port Mode Register C (PMRC)

Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 51. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

Not used

Detection edge register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 51 Detection Edge Select Register 2 (ESR2)

HD404654 Series

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 23. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 23 PWM Output Following Update of Timer Write Register

PWM Output

Mode

Timer Write Register is Updated during
High PWM Output

Timer Write Register is Updated during
Low PWM Output

Free running

Timer write
register
updated to
value N

Interrupt
request

Timer write
register
updated to
value N

Interrupt
request

(255 N) T

(N + 1)

(N' + 1)

(255 N)

(N + 1)

Reload

Timer write
register
updated to
value N

Interrupt
request

Timer write
register
updated to
value N

Interrupt
request

(255 N)

HD404654 Series

Selector

Prescaler S (PSS)

128

512

2048

Selector

I/O control

logic

Idle control

logic

Octal counter

(OC)

Serial interrupt

request flag

(IFS1)

Clock

Serial data

(SR1L/U)

Serial mode register

1A (SM1A)

Serial mode register

1B (SM1B)

Transfer
control

SCK

System
clock

Internal data bus

PER

1/2

Figure 52 Block Diagram of Serial Interface 1

Serial Interface Operation

Selecting and Changing the Operating Mode: Table 24 lists the serial interfaces' operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial
mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always
initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface
1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for
Serial Interface for details.

HD404654 Series

Table 24 Serial Interface 1 Operating Modes

SM1A

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Pin Setting: The R4

SCK

pin is controlled by writing data to serial mode register 1A (SM1A: $005).

Pins R4

/SI

and R4

/SO

are controlled by writing data to port mode register A (PMRA: $004). Refer to

the following section Registers for Serial Interface for details.

Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following
section Registers for Serial Interface for details.

Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data
register 1. The serial data is shifted by the transmit clock and is input from or output to an external system.

The output level of the SO

pin is invalid until the first data is output after MCU reset, or until the output

level control in idle states is performed.

Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000
by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When
the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal
counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SM1A0SM1A2) of serial mode register 1A (SM1A: $005) and bit 0

(SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 25.

HD404654 Series

Table 25 Serial Transmit Clock (prescaler output)

SM1B

SM1A

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

tcyc

Operating States: Serial interface 1 has the following operating states; transitions between them are
shown in figure 53.

STS wait state

Transmit clock wait state

Transfer state

Continuous transmit clock output state (only in internal clock mode)

HD404654 Series

STS wait state

(Octal counter = 000,

Transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

MCU reset

SM1A write

STS instruction

Transmit clock

8 transmit clocks

STS instruction (IFS1 1)

SM1A write (IFS1 1)

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

SM1A write

STS instruction

Transmit clock

STS instruction (IFS1 1)

8 transmit clocks

Internal clock mode

Continuous transmit

clock output state

(PMRA 0, 1 = 0, 0)

SM1A write

Transmit clock

Note: Refer to the Operating States section for the corresponding encircled numbers.

MCU reset

SM1A write (IFS1 1)

Figure 53 Serial Interface State Transitions

STS wait state: Serial interface 1 enters STS wait state by MCU reset (00, 10 in figure 53). In STS wait
state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.

Transmit clock wait state: Transmit clock wait state is the period between STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
serial interface in transfer state. However, note that if continuous clock output mode is selected in
internal clock mode, the serial interface does not enter transfer state but enters continuous clock output
state (17).

The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait

HD404654 Series

state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode.
In internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.

If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.

Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/ receive data but only
outputs the transmit clock from the

SCK

pin.

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output
of serial output pin SO

can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B:

$028) to 0 or 1. The output level control example of serial interface 1 is shown in figure 54. Note that the
output level cannot be controlled in transfer state.

HD404654 Series

State

MCU reset

PMRA write

SM1A write

SM1B write

SR1L, SR1U
write

STS instruction

SCK

pin (input)

IFS1

STS wait state

Transmit
clock
wait state

Transfer state

Transmit
clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SM1A write

SM1B write

SR1L, SR1U
write

STS instruction

SCK

pin (output)

IFS1

STS wait state

Transfer state

Transmit
clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Figure 54 Example of Serial Interface 1 Operation Sequence

HD404654 Series

Transmit Clock Error Detection (In External Clock Mode): Serial interface 1 will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 55.

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005)
changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the
serial 1 interrupt request flag (IFS1: $003, bit 2) is set again, and therefore the error can be detected.

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, serial interface 1 must be initialized by writing to serial mode
register 1A (SM1A: $005) again.

Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from
transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS
instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (IFS1:
$003, bit 2) is not set. To set the serial 1 interrupt request flag (IFS1: $003, bit 2), a serial mode register
1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after
confirming that the

SCK

pin is at 1, that is, after executing the input instruction to port R4.

HD404654 Series

Registers for Serial Interface 1

When serial interface 1 operation is selected, serial data is read and written by the following registers.

Serial mode register 1A (SM1A: $005)

Serial mode register 1B (SM1B: $028)

Serial data register 1 (SR1L: $006, SR1U: $007)

Port mode register A (PMRA: $004)

Miscellaneous register (MIS: $00C)

Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 56).

SCK

pin function selection

Serial interface 1 transmit clock selection

Serial interface 1 prescaler division ratio selection

Serial interface 1 initialization

Serial mode register 1A is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock
to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to
000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003,
bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

SM1A3

SM1A2

SM1A0

SM1A1

Serial mode register 1A (SM1A: $005)

SM1A2

SM1A0

SM1A1

SM1A3

SCK

mode selection

SCK

Output

Input

Clock source

Prescaler

System clock

External clock

Prescaler
division ratio

Refer to
table 25

Figure 56 Serial Mode Register 1A (SM1A)

Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 57).

Serial interface 1 prescaler division ratio selection

Serial interface 1 output level control in idle states

Serial mode register 1B is a 2-bit write-only register. It cannot be written during data transfer.

By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit
0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO

pin is

controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is
written to.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

Not used

SM1B0

Undefined

SM1B1

SM1B0

Serial clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

Serial mode register 1B (SM1B: $028)

SM1B1

Output level control in idle states

Low level

High level

Figure 57 Serial Mode Register 1B (SM1B)

Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 58
and 59)

Serial interface 1 transmission data write and shift

Serial interface 1 receive data shift and read

Writing data in this register is output from the SO

pin, LSB first, synchronously with the falling edge of

the transmit clock; data is input, LSB first, through the SI

pin at the rising edge of the transmit clock.

Input/output timing is shown in figure 60.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR13

Undefined

R/W

SR12

Undefined

R/W

SR10

Undefined

R/W

SR11

Serial data register 1 (lower digit) (SR1L: $006)

Figure 58 Serial Data Register 1 (SR1L)

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR17

Undefined

R/W

SR16

Undefined

R/W

SR14

Undefined

R/W

SR15

Serial data register 1 (upper digit) (SR1U: $007)

Figure 59 Serial Data Register 1 (SR1U)

HD404654 Series

DTMF Generator Circuit

The MCU provides a dual-tone multifrequency (DTMF) generator circuit. The DTMF signal consists of
two sine waves to access the switching system.

Figure 63 shows the DTMF keypad and frequencies. Each key enables tones to be generated corresponding
to each frequency. Figure 64 shows a block diagram of the DTMF circuit.

The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz or 4 MHz) is changed into four clock signals
through the division circuit (1/2, 1/5, 1/9 and 1/10). The DTMF circuit uses one of the four clock signals,
which is selected by system clock select register 1 (SSR1: $029) and system clock select register 2 (SSR2:
$02A) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers,
sine wave counters, and control registers.

The DTMF generation circuit is controlled by the following three registers.

R1 (697 Hz)

R2 (770 Hz)

R3 (852 Hz)

R4 (941 Hz)

C1 (1,209 Hz)

C2 (1,336 Hz)

C3 (1,477 Hz)

C4 (1,633 Hz)

Figure 63 DTMF Keypad and Frequencies

HD404654 Series

Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output
frequencies as shown in figure 65, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

TGM3

TGM2

TGM0

TGM1

Tone generator mode register (TGM: $019)

TGM3

TGM2

TONEC output frequencies

f (1,209 Hz)

f (1,336 Hz)

f (1,477 Hz)

f (1,633 Hz)

TGM1

TGM0

TONER output frequencies

f (697 Hz)

f (770 Hz)

f (852 Hz)

f (941 Hz)

Figure 65 Tone Generator Mode Register (TGM)

Tone Generator Control Register (TGC: $01A): Three-bit write-only register, which controls the
start/stop of the DTMF signal output as shown in figure 66, and is reset to $0 by MCU reset. TONER and
TONEC output can be independently controlled by bits 2 and 3 (TGC2, TGC3), and the DTMF circuit is
controlled by bit 1 (TGC1) of this register.

Bit

Initial value

Read/Write

Bit name

TGC3

TGC2

Not used

TGC1

Tone generator control register (TGC: $01A)

TGC1

DTMF enable bit

DTMF disable

DTMF enable

TGC3

TONEC output control (column)

No output

TONEC output (active)

TGC2

TONER output control (row)

No output

TONER output (active)

Figure 66 Tone Generator Control Register (TGC)

HD404654 Series

System Clock Select Registers 1 and 2 (SSR1: $029, SSR2: $02A): Four-bit write-only registers.
These registers must be set to the value specified in figures 67 and 68 depending on the frequency of the
oscillator connected to the OSC

and OSC

pins. Note that if the combination of the oscillation frequency

and the values in these registers is different from that specified in figures 67 and 68, the DTMF output
frequencies will differ from the correct frequencies as listed in Table 26.

Bit

Initial value

Read/Write

Bit name

Not used

SSR10

SSR11

System clock select register 1 (SSR1: $029)

SSR22

400 kHz

800 kHz

2 MHz

4 MHz

3.58 MHz

SSR11

SSR10

System clock
selection

: Don't care

Figure 67 System Clock Select Register 1 (SSR1)

Bit

Initial value

Read/Write

Bit name

Not used

SSR22

Not used

SSR22

Serial clock select register 2 (SSR2: $02A)

System clock selection

Selected from 400 kHz, 800 kHz,
2 MHz, 4 MHz

3.58 MHz

Note:

Refer to system clock select register 1 (SSR1).

Figure 68 System Clock Select Register 2 (SSR2)

HD404654 Series

DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A
conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER,
TONEC) transmit the sine waves of the row-group and column-group, respectively. Figure 69 shows the
tone output equivalent circuit. Figure 70 shows the output waveform. One cycle of this wave consists of
32 slots. Therefore, the output waveform is stable with little distortion. Table 26 lists the frequency
deviation of the MCU from standard DTMF signals.

Table 26 Frequency Deviation of the MCU from Standard DTMF

fosc = 400 kHz, 800 kHz, 2 MHz, 4 MHz

fosc = 3.58 MHz

Standard
DTMF (Hz)

MCU (Hz)

Deviation from
Standard (%)

MCU (Hz)

Deviation from
Standard (%)

697

694.44

0.37

690.58

0.92

770

769.23

0.10

764.96

0.65

852

851.06

0.11

846.33

0.67

941

938.97

0.22

933.75

0.77

1,209

1,212.12

0.26

1,205.39

0.30

1,336

1,333.33

0.20

1,325.92

0.75

1,477

1,481.48

0.30

1,473.25

0.25

1,633

1,639.34

0.39

1,630.23

0.17

Notes: This frequency deviation value does not include the frequency deviation due to the oscillator

element. Also note that in this case the ratio of the high level and low level widths in the oscillator
waveform due to the oscillator element will be 50%:50%.

Switch control

GND

ref

TONER

TONEC

Figure 69 Tone Output Equivalent Circuit

HD404654 Series

Comparator

The block diagram of the comparator is shown in figure 71. The comparator compares input voltage with
the reference voltage.

Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison. If an
input voltage at COMP

or COMP

is higher than the reference voltage, the TM or TMD command sets the

status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to COMP

COMP

. On the other hand, if an input voltage at COMP

or COMP

is lower than the reference voltage,

the TM or TMD command clears the ST to 0.

Selector

Com-
parator

Comparator data

Comparator enable

Internal data bus

COMP

ref

COMP

Figure 71 Block Diagram of Comparator

Compare Enable Register (CER: $018): Three-bit write-only register which enables comparator
operation, and selects the reference voltage and the analog input pin.

Compare Data Register (CDR: $017): Two-bit read-only register which latches the result of the
comparison between the analog input pins and the reference voltage. Bits 0 and 1 reflect the results of
comparison with COMP

and COMP

, respectively. This register can be read only by the TM or TMD

command. Only bit CER3 corresponds to the analog input pin, which is selected by bits CER0 and CER1.
After a compare operation, the data in this register is not retained.

Note on Use: During compare operation, pins RD

/COMP

and RD

/COMP

operate as analog inputs and

cannot operate as R ports.

The comparator can operate in active mode but is disabled in other modes.

/VC

ref

cannot operate as an R port when the external input voltage is selected as the reference.

HD404654 Series

Bit

Initial value

Read/Write

Bit name

CER3

Not used

CER0

CER1

Compare enable register (CER: $018)

CER3

Digital/Analog selection

Digital input mode:
RD /COMP

, RD /COMP

operate as R port

Analog input mode:
RD /COMP

, RD /COMP

operate as analog input

CER1

Analog input pin selection

COMP

Not used

CER0

Figure 72 Compare Enable Register

Bit

Initial value

Read/Write

Bit name

Not used

CDR0

CDR1

Compare data register (CDR: $017)

Undefined Undefined

Result of COMP

comparison

Result of COMP

comparison

Figure 73 Compare Data Register

HD404654 Series

Programmable ROM (HD4074654)

The HD4074654 is a ZTAT

microcomputer with built-in PROM that can be programmed in PROM

mode.

PROM Mode Pin Description

Pin No.

MCU Mode

PROM Mode

DP-42S

FP-44A

Pin Name

I/O

Pin Name

I/O

/COMP

TONEC

TONER

ref

/VC

ref

TEST

OSC

RESET

GND

I/O

STOPC

INT

I/O

HD404654 Series

Programming the Built-In PROM

The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling

TEST, M

, and

low, and

RESET low as shown in figure 74. In PROM mode, the MCU does not operate, but it can be

programmed in the same way as any other commercial 27256-type EPROM using a standard PROM
programmer and a 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters
of the HD4074654 are listed in table 28.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general- purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that
if, for example, 4 kwords of built-in PROM are to be programmed by a general-purpose PROM
programmer, an 8 kbyte address space ($0000$7FFF) must be specified.

Warnings

1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address

$2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased or reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that ZTAT

devices

require a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.

Programming and verification modes are selected as listed in table 27.

For details of PROM programming, refer to the preface section, Notes on PROM Programming.

Table 27 PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibited

High

High impedance

HD404654 Series

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 75 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Direct Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 75 RAM Addressing Modes

HD404654 Series

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 76 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 78. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-
bit immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 77. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404654 Series

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 76 ROM Addressing Modes

HD404654 Series

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3

Total permissible input current

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

7, 9

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to D

) of the HD4074654.

2. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to GND.

3. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

4. The maximum input current is the maximum current flowing from each I/O pin to GND.

5. Applies to D

, and

R0R4.

6. Applies to D

7. The maximum output current is the maximum current flowing out from V

to each I/O pin.

8. Applies to D

and R0R4.

9. Applies to D

HD404654 Series

Electrical Characteristics

DC Characteristics (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V, T

= 20 to +75

HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit Test Condition

Notes

Input high
voltage

RESET

STOPC

INT

SCK

, EVND

0.9V

+ 0.3 V

OSC

0.3 --

+ 0.3 V

External clock

Input low
voltage

RESET

STOPC

INT

SCK

, EVND

0.3

0.10 V

OSC

0.3

External clock

Output high
voltage

SCK

, SO

TOC,TOD

1.0 --

= 0.5 mA

Output low
voltage

SCK

, SO

, TOC,

TOD

0.4

= 0.4 mA

I/O leakage
current

| I

RESET

STOPC

INT

SCK

, SO

, EVND,

OSC

, TOC, TOD

= 0 V to V

Current
dissipation in
active mode

CC1

mA V

= 5 V,

OSC

= 4 MHz

Digital input mode

2, 5

CC2

0.6

1.8

mA V

= 3 V,

OSC

= 800 kHz

Digital input mode

2, 5

CMP1

mA V

= 5 V,

OSC

= 4 MHz

Analog comp. mode

3, 5

CMP2

3.1

4.3

mA V

= 3 V,

OSC

= 800 kHz

Analog comp. mode

3, 5

Current
dissipation in
standby
mode

SBY1

1.2

mA V

= 5 V,

OSC

= 4 MHz

4, 5

SBY2

0.2

0.7

mA V

= 3 V

OSC

= 800 kHz

4, 5

Current
dissipation in
stop mode

STOP

= 3 V

HD404654 Series

Item

Symbol

Pin(s)

Min

Typ

Max

Unit Test Condition

Notes

Stop mode
retaining
voltage

STOP

1.3

Comparator
input
reference
voltage
scope

ref

1.2 V

Notes: 1. Output buffer current is excluded.

2. I

CC1

and I

CC2

are the source currents when no I/O current is flowing while the MCU is in reset

state.

Test conditions:

MCU:

Reset

Pins:

RESET

at GND (0 to 0.3V)

TEST

at V

0.3 to V

)

3. RD

, RD

pins are in analog input mode when no I/O current is flowing.

Test conditions:

MCU:

DTMF does not operate

Pins:

/COMP

at GND (0 V to 0.3 V)

/COMP

at GND (0 V to 0.3 V)

/VC

ref

at GND (0 V to 0.3 V)

4. I

SBY1

and I

SBY2

are the source currents when no I/O current is flowing while the MCU timer is

operating.

Test conditions:

MCU:

I/O reset

Serial interface stopped

DTMF does not operate

Standby mode

Pins:

RESET

at V

0.3 to V

)

TEST

at V

0.3 to V

)

5. The current dissipation is in proportion to f

OSC

while the MCU is operating or is in standby mode.

The current dissipation when f

OSC

= F MHz is given by the following equation: Maximum value

OSC

= F MHz) = F/4 X maximum value (f

OSC

= 4 MHz)

6. These are the source currents when no I/O current is flowing.

Test conditions:

Pins:

RESET

at V

0.3 to V

)

TEST

at V

0.3 to V

)

at V

0.3 to V

)

Note:

Applies to HD4074654.

7. RAM data retention.

HD404654 Series

I/O Characteristics for Standard Pins (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V,

= 20 to +75

C; HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise

specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

R0RD, RE

0.7V

+ 0.3 V

Input low
voltage

R0RD, RE

0.3

0.3V

Output high
voltage

R0R4

1.0

= 0.5 mA

Output low
voltage

R0R4

0.4

= 0.4 mA

I/O leakage
current

| I

, R0RD,

= 0 V to V

1, 2

= V

0.3 V to V

1, 3

= 0 V to 0.3 V

1, 3

Pull-up MOS
current

R0R4

= 3 V,

= 0 V

Input high
voltage

IHA

COMP

ref

+0.05

Analog compare mode

Input low

ILA

COMP

ref

0.05

Analog compare mode

Notes: 1. Output buffer current is excluded.

2. Applies to HD404652, HD404654.

3. Applies to HD4074654.

4. Use an analog input reference voltage in the range 0 V

ref

1.2.

HD404654 Series

I/O Characteristics for High-Current Pins (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V, T

= 20 to +75

C; HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise

specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Note

Input high
voltage

0.7 V

+ 0.3 V

Input low
voltage

0.3

0.3 V

Output high
voltage

1.0 --

= 0.5 mA

2.0

= 10 mA,

= 4.5 V to 6.0 V

Output low
voltage

0.4

= 0.4 mA

2.0

= 15 mA,

= 4.5 V to 6.0 V

I/O leakage
current

| I

= 0 V to V

Pull-down
MOS current

= 3 V, V

= 3 V

Pull-up MOS
current

= 3 V, V

= 0 V

Notes: 1. Output buffer current is excluded.

2. When using HD4074654, V

= 4.5 V to 5.5 V.

DTMF Characteristics (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V, T

= 20 to +75

HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Note

Tone output
voltage (1)

TONER

500

660

rms

ref

GND = 2.0 V,

= 100 k

, V

= 3.0 V

Tone output
voltage (2)

TONEC

520

690

rms

ref

GND = 2.0 V,

= 100 k

, V

= 3.0 V

Tone output
distortion

%DIS

Short circuit between
TONER and TONEC
R

= 100 k

Tone output
ratio

2.5

Short circuit between
TONER and TONEC
R

= 100 k

Notes: 1. See figure 79.

2. See figure 80.

These characteristics are guaranteed for an operating frequency (f

OSC

) of 400 kHz, 800 kHz, 2 MHz,

3.58 MHz, or 4 MHz.

HD404654 Series

100

AC Characteristics (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V, T

= 20 to +75

HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Clock
oscillation
frequency

OSC

, OSC

400

kHz

800

kHz

MHz

3.58

MHz

Instruction
cycle time

cyc

OSC

= 4 MHz

1/4 division,

OSC

= 4 MHz,

1/32 division

Oscillation
stabilization
time

OSC

, OSC

7.5

= 2.7 V to 6.0 V

4, 5,
13

(ceramic)

= 1.8 V to 2.7 V

4, 5,
12

External
clock high
width

CPH

OSC

1100

OSC

= 400 kHz

550

OSC

= 800 kHz

215

OSC

= 2 MHz

115

OSC

= 3.58 MHz

105

OSC

= 4 MHz

External
clock low
width

CPL

OSC

1100

OSC

= 400 kHz

550

OSC

= 800 kHz

215

OSC

= 2 MHz

115

OSC

= 3.58 MHz

105

OSC

= 4 MHz

External
clock rise
time

CPr

OSC

150

OSC

= 400 kHz

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 3.58 MHz

OSC

= 4 MHz

HD404654 Series

101

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

External
clock fall
time

CPf

OSC

150

OSC

= 400 kHz

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 3.58 MHz

OSC

= 4 MHz

INT

EVND high
width

INT

EVND

cyc

INT

EVND low
width

INT

EVND

cyc

RESET

low

width

RSTL

RESET

cyc

STOPC

low

width

STPL

STOPC

RESET

rise

time

RSTr

RESET

STOPC

rise

time

STPr

STOPC

Input
capacitance

All pins except
D

, D

f = 1 MHz, V

= 0 V

180

Analog
comparator
stabilization
time

CSTB

COMP

cyc

= 2.7 V to 6.0 V

11, 12

cyc

= 1.8 V to 2.7 V

Notes: 1. Bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bit 2 (SSR22)

of system clock select register 2 (SSR2: $02A) must be set according to the system clock
frequency.

2. SEL = 1

3. SEL = 0

4. The oscillation stabilization time is the period required for the oscillator to stabilize after V

reaches 2.7 V (1.8 V for HD404654 and HD404652) at power-on, after

RESET

input goes low

when stop mode is cancelled, or after

STOPC

input goes low when stop mode is cancelled. At

power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least t

ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to
determine what stabilization time is required, since it will depend on the circuit constants and
stray capacitance.

HD404654 Series

102

5. Applies to ceramic oscillator only.

When using crystal oscillator: V

= 2.7 V to 6.0 V, t

= 40 ms (typ) or V

= 1.8 V to 2.6 V, t

60 ms (typ)

Crystal oscillator

(OSC

, OSC

)

Crystal
oscillator

GND

OSC

= 1 M

20%

= C

= 1022 pF

20%

Crystal: Equivalent to circuit
shown below
C

= 7 pF max

= 100

max

f = 400 kHz, 800 kHz,
2 MHz, 3.58 MHz, 4 MHz

Since the circuit constants change depending on the crystal or ceramic resonator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator

manufacturer to determine the circuit parameters.

Wiring among OSC

, OSC

, and elements should be as short as possible, and must not cross

other wiring (see figure 20).

6. Refer to figure 81.

7. Refer to figure 82.

8. Refer to figure 83.

9. Refer to figure 84.

10. Applies to HD4074654.

11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for

correct data to be read after entering RD

/COMP

and RD

/COMP

into analog input mode.

12. HD4074654 : V

= 2.7 V to 5.5 V

HD404654 Series

103

Serial Interface Timing Characteristics (HD404652, HD404654: V

= 1.8 to 6.0 V, GND = 0 V, T

20 to +75

C; HD4074654: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise

specified)

During Transmit Clock Output

Item

Symbol

Pin (s) Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Load shown in figure 86

Transmit clock high
width

SCKH

SCK

0.5

Scyc

Load shown in figure 86

Transmit clock low
width

SCKL

SCK

0.5

Scyc

Load shown in figure 86

Transmit clock rise time t

SCKr

SCK

100

Load shown in figure 86

Transmit clock fall time

SCKf

SCK

100

Load shown in figure 86

Serial output data delay
time

DSO

500

Load shown in figure 86

Serial input data setup
time

SSI

300

Serial input data hold
time

HSI

300

Note: 1. Refer to figure 85.

During Transmit Clock Input

Item

Symbol

Pin (s) Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Transmit clock high
width

SCKH

SCK

0.5

Scyc

Transmit clock low
width

SCKL

SCK

0.5

Scyc

Transmit clock rise time t

SCKr

SCK

100

Transmit clock fall time

SCKf

SCK

100

Serial output data delay
time

DSO

500

Load shown in figure 86

Serial input data setup
time

SSI

300

Serial input data hold
time

HSI

300

Note: 1. Refer to figure 85.

HD404654 Series

108

HD404652/HD404654 Option List

Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTATTM version).

5. ROM Code Media

7. Stop Mode

Used

Not used

8. Package

DP-42S

FP-44A

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are

programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

6. Oscillator for OSC1 and OSC2

Ceramic oscillator

Crystal oscillator

External clock

f =

MHz

Date of order

Customer

Department

Name

ROM code name

LSI number

1. ROM Size

Please check off the appropriate applications and
enter the necessary information.

HD404652

HD404654

2-kword

4-kword

HD404654 Series

109

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404654

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404654