Rev.0.01, Jun.02.2003, page 1 of 17
HM62A16100I Series
Wide Temperature Range Version
16 M SRAM (1-Mword
16-bit)
REJ03C0053-0001Z
Preliminary
Rev. 0.01
Jun.02.2003
Description
The Renesas HM62A16100I Series is 16-Mbit static RAM organized 1-Mword
16-bit. HM62A16100I
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it
is suitable for battery backup systems. It has the package variations of 48-bump chip size package with
0.75 mm bump pitch for high density surface mounting.
Features
Single 1.8 V supply: 1.65 V to 2.2 V
Fast access time: 70 ns (max)
Power dissipation:
Active: 3.6 mW/MHz (typ)
Standby: 0.9
W (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
Temperature range:
-
40 to +85
C
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Renesas Technology's Sales Dept. regarding specification.
HM62A16100I Series
Rev.0.01, Jun.02.2003, page 2 of 17
Ordering Information
Type No.
Access time
Package
HM62A16100LBPI-7
70 ns
48-bump CSP with 0.75 mm bump pitch (TBP-48F)
HM62A16100LBPI-7SL 70
ns
HM62A16100I Series
Rev.0.01, Jun.02.2003, page 3 of 17
Pin Arrangement
(Top view)
48-bumps CSP
A
B
C
D
E
F
G
H
1 2 3 4 5 6
LB
I/O8
I/O9
VSS
VCC
I/O14
I/O15
A18
OE
UB
I/O10
I/O11
I/O12
I/O13
A19
A8
A3
A5
A17
VSS
A14
A0
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1
I/O1
I/O3
I/O4
I/O5
WE
A11
CS2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NU
Pin Description
Pin name
Function
A0 to A19
Address input
I/O0 to I/O15
Data input/output
CS1
Chip
select
1
CS2 Chip
select
2
WE
Write
enable
OE
Output
enable
LB
Lower
byte
select
UB
Upper
byte
select
V
CC
Power
supply
V
SS
Ground
NU*
1
Not used (test mode pin)
Note: 1. This pin should be connected to a ground (V
SS
), or not be connected (open).
HM62A16100I Series
Rev.0.01, Jun.02.2003, page 4 of 17
Block Diagram
I/O0
I/O15
CS2
WE
OE
A17 A7 A5
A2
V
V
CC
SS
Row
decoder
Memory matrix
8,192 x 128 x 16
Column I/O
Column decoder
Input
data
control
Control logic
A1
A19
A8
A9
A10
A11
A12
A13
A14
A16
A18
A15
A3
A6
CS1
LB
UB
A4
LSB
MSB
MSB
LSB
A0
HM62A16100I Series
Rev.0.01, Jun.02.2003, page 5 of 17
Operation Table
CS1
CS1
CS1
CS1
CS2
WE
WE
WE
WE OE
OE
OE
OE
UB
UB
UB
UB
LB
LB
LB
LB
I/O0 to I/O7
I/O8 to I/O15
Operation
H
High-Z High-Z Standby
L
High-Z High-Z Standby
H
H
High-Z High-Z Standby
L H H L L
L
Dout Dout Read
L H H L H L Dout
High-Z
Lower
byte
read
L H H L L H High-Z
Dout
Upper
byte
read
L H L
L L Din
Din
Write
L H L
H L Din
High-Z
Lower
byte
write
L H L
L H High-Z
Din
Upper
byte
write
L H H H
High-Z High-Z Output
disable
Note: H: V
IH
, L: V
IL
,
: V
IH
or V
IL
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Power supply voltage relative to V
SS
V
CC
-
0.3 to + 2.6
V
Terminal voltage on any pin relative to V
SS
V
T
-
0.3*
1
to V
CC
+ 0.3*
2
V
Power dissipation
P
T
1.0
W
Storage temperature range
Tstg
-
55 to +125
C
Storage temperature range under bias
Tbias
-
40 to +85
C
Notes: 1. V
T
min:
-
2.0 V for pulse half-width
10 ns.
2. Maximum voltage is +2.6 V.
DC Operating Conditions
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
CC
1.65
1.8 2.2 V
V
SS
0 0 0 V
Input high voltage
V
IH
0.75
V
CC
V
CC
+ 0.3 V
Input low voltage
V
IL
-
0.3
0.25
V
CC
V
1
Ambient temperature range
Ta
-
40
85
C
Note: 1. V
IL
min:
-
2.0 V for pulse half-width
10 ns.
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