Document Outline
- Description
- Features
- Ordering Information
- Pin Arrangement
- Pin Description
- Block Diagram
- Operation Table
- Absolute Maximum Ratings
- DC Operating Conditions
- DC Characteristics
- Capacitance
- AC Characteristics
- Timing Waveforms
- Read Cycle-1
- Read Cycle-2 (SS Controlled)
- Read Cycle-3 (G Controlled)
- Write Cycle
- Read-Write Cycle
- ZZ Control
- Boundary Scan Test Access Port Operations
- ID register
- TAP Controller State Diagram
- Package Dimensions
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April 1, 2003
To all our customers
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Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi's Sales Dept. regarding specification.
HM62G18512A Series
9M Synchronous Fast Static RAM
(512k-word
18-bit)
ADE-203-1268B (Z)
Preliminary
Rev. 0.2
Sep. 12, 2001
Description
The HM62G18512A is a synchronous fast static RAM organized as 512-kword
18-bit. It has realized
high speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note:
All power supply and ground pins must be connected for proper operation of the device.
Features
2.5 V
5% and 3.3 V
5% operation and 0.9 V (V
REF
)
Internal self-timed late write
Byte write control (2 byte write selects, one for each 9-bit)
Optional
36 configuration
HSTL compatible I/O
Programmable impedance output drivers
User selective input trip-point
Differential, HSTL clock inputs
Asynchronous
G output control
Asynchronous sleep mode
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Protocol: Single clock register-register mode
HM62G18512A Series
2
Ordering Information
Type No.
Access time
Cycle time
Package
HM62G18512ABP-30
HM62G18512ABP-33
HM62G18512ABP-40
1.7 ns
1.7 ns
2.0 ns
3.0 ns
3.3 ns
4.0 ns
119-bump 1. 27 mm
14 mm
22 mm BGA (BP-119C)
Pin Arrangement
1
2
3
4
5
6
7
A
V
DDQ
SA0
SA1
NC
SA13
SA12
V
DDQ
B
NC
NC
SA2
NC
SA14
SA11
NC
C
NC
SA3
SA4
V
DD
SA5
SA6
NC
D
DQb5
NC
V
SS
ZQ
V
SS
DQa0
NC
E
NC
DQb3
V
SS
SS
V
SS
NC
DQa4
F
V
DDQ
NC
V
SS
G
V
SS
DQa1
V
DDQ
G
NC
DQb6
SWEb
NC
V
SS
NC
DQa8
H
DQb7
NC
V
SS
NC
V
SS
DQa2
NC
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
NC
DQb2
V
SS
K
V
SS
NC
DQa7
L
DQb8
NC
V
SS
K
SWEa
DQa6
NC
M
V
DDQ
DQb1
V
SS
SWE
V
SS
NC
V
DDQ
N
DQb4
NC
V
SS
SA8
V
SS
DQa3
NC
P
NC
DQb0
V
SS
SA10
V
SS
NC
DQa5
R
NC
SA7
M1
V
DD
M2
SA15
NC
T
NC
SA18
SA9
NC
SA17
SA16
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
(Top view)
HM62G18512A Series
3
Pin Description
Name
I/O type
Descriptions
Notes
V
DD
Supply
Core power supply
V
SS
Supply
Ground
V
DDQ
Supply
Output power supply
V
REF
Supply
Input reference: provides input reference voltage
K
Input
Clock input. Active high.
K
Input
Clock input. Active low.
SS
Input
Synchronous chip select
SWE
Input
Synchronous write enable
SAn
Input
Synchronous address input
n = 0-18
SWEx
Input
Synchronous byte write enables
x = a, b
G
Input
Asynchronous output enable
ZZ
Input
Power down mode select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous data input/output
x = a, b
n = 0, 1, 2...8
M1, M2
Input
Output protocol mode select
TMS
Input
Boundary scan test mode select
TCK
Input
Boundary scan test clock
TDI
Input
Boundary scan test data input
TDO
Output
Boundary scan test data output
NC
--
No connection
M1
M2
Protocol
Notes
V
SS
V
DD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to V
SS
via a resistance RQ where 225
RQ
275
. If ZQ = V
DDQ
or
open, output buffer impedance will be maximum.
2. There is 1 protocol with mode pin. For this application, M1 and M2 need to connect to V
SS
and
V
DD
, respectively. The state of the Mode control inputs must be set before power-up and must
not change during device operation. Mode control inputs are not standard inputs and may not
meet V
IH
or V
IL
specification. This SRAM is tested only in the synchronous register to register
operation.
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