Document Outline
- Description
- Features
- Ordering Information
- Pin Arrangement
- Pin Description
- Pin Function
- Block Diagram
- Memory Map and Address
- Address Input
- Mode Selection
- Command Definition
- State transition diagram
- Absolute Maximum Ratings
- Capacitance
- DC Characteristics
- DC Characteristics (1)
- DC Characteristics (2)
- AC Characteristics
- AC Characteristics (1)
- AC Characteristics (2)
- Program/Erase/Rewrite Characteristics
- Timing Waveforms
- Power on and off
- Basic timing for command, address and data latch
- Command input cycle
- Command input cycle after data output cycle
- Address input cycle
- Data input cycle
- Serial read cycle
- Invalid input cycle
- Invalid output cycle
- Status read
- ID read
- Read mode
- Read cycle
- Status read during the read operation
- Read stop cycle
- Sequential read mode
- Sequential read cycle
- Sequential read stop cycle
- Stop in Busy state
- Power on auto read / Auto read
- Auto read
- Auto read (Deep standby mode which transferred by the command)
- Auto read stop cycle
- Program mode
- Program cycle
- Erase mode
- Rewrite mode
- Rewrite cycle
- Notes on usage
- Package Dimensions
Rev.0.03, Jun.06.2003, page 1 of 50
HN29V128A1A (3.3 V/
8)
HN29V128A0A (3.3 V/
16)
HN29A128A1A (1.8 V/
8)
HN29A128A0A (1.8 V/
16)
128M superAND Flash Memory
(with internal sector management)
REJ03C0031-0003Z
(Previous ADE-203-1344B (Z) Rev.0.2)
Preliminary
Rev. 0.03
Jun. 06, 2003
Description
The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash
memory, which uses cost effective and high performance AND type multi-level memory cell technology.
Current AND flash memory requires us to support complicated operations such as sector management for
defect sector and error check correction. But this series doesn't need such operations. Beside it supports
wear leveling function, which is sector replacement function in case of that certain sector, reaches certain
erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest
sector(2k byte) without command and address data input when power is on.
Note: This product is authorized for using consumer application such as cellular phone,
Therefore, please contact Renesas Technology's sales office before using other applications.
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology's Sales Dept. regarding specifications.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 2 of 50
Features
On-board single power supply (V
CC
): V
CC
= 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A)
: V
CC
= 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A)
Operating temperature range: Ta = 0 to
+
70
C
Program/erase, rewrite endurance
10
5
times
Access time
First access
80
s (typ) (3.3 V,
8/
16)
150
s (typ) (1.8 V,
8/
16)
Serial read cycle
50 ns (min) (3.3 V,
8/
16)
100 ns (min) (1.8 V,
8/
16)
maximum transfer rate (sequential read)
20.0 Mbyte/s (3.3 V,
8)
40.0 Mbyte/s (3.3 V,
16)
10.0 Mbyte/s (1.8 V,
8)
20.0 Mbyte/s (1.8 V,
16)
Program time
1.2 ms (typ) /sector (2048 byte) (3.3 V,
8/
16)
2.0 ms (typ) /sector (2048 byte) (1.8 V,
8/
16)
Erase time
2.2 ms (typ) /sector (2048 byte) (3.3 V,
8/
16)
3.5 ms (typ) /sector (2048 byte) (1.8 V,
8/
16)
Rewrite time
2.2 ms (typ) /sector (2048 byte) (3.3 V,
8/
16)
3.5 ms (typ) /sector (2048 byte) (1.8 V,
8/
16)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 3 of 50
Low power dissipation (3.3 V and 1.8 V)
Standby current
I
CCS1
= 1 mA (max)
I
CCS2
= 50
A (max) (CMOS level)
I
CCS3
= 10
A (max) (3.3 V), 15
A (max) (1.8 V) (deep standby)
Serial read operation current
I
CC1
= 30 mA (max)
Program/erase/rewrite operation current
I
CC2/3/4
= 60 mA (max) (program/erase/rewrite)
Sector management
Following functions are build-in flash memory component.
Sector management:
If certain sector had been damaged, it would be replaced by the spare sector automatically.
Always 100% of sector number are available up to 10
5
erase/write cycles per device.
Error check and correction:
ECC code is generated at the time of programming, and data error is checked at the time of read
operation. If data error occurs, the data will be corrected automatically.
(ECC: 1-byte error correction, 2-byte error detection per 512byte page)
Wear leveling:
To avoid erase/program/rewrite operation converge on the particular physical sector, The number of
erase/program/rewrite operation will be leveled automatically by changing internal logical sector
address.
Package line up
CSP: CSP 95-bump (TBP-95V)
Ordering Information
Type No.
Operating voltage (V
CC
) Organization
Package
HN29V128A1ABP-5E 3.3
V
8 10.0
11.50 mm
2
, 95-bump
HN29V128A0ABP-5E 3.3
V
16
0.8 mm ball pitch CSP (TBP-95V)
HN29A128A1ABP-8E 1.8
V
8 Lead
free
HN29A128A0ABP-8E 1.8
V
16
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 4 of 50
Pin Arrangement 95-bump CSP
1
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
WE
V
SS
WP
DU
CLE
ALE
DU
DU
R/
B
DSE
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
(TOP View)
95-bump CSP
DU
DU
DU
PRE
I/O3
DU
DU
DU
DU
I/O15
I/O13
I/O5
DU
I/O1
DU
DU
DU
I/O6
DU
I/O11
I/O4
I/O9
DU
V
SS
DU
DU
I/O2
DU
RE
MRES
I/O7
I/O8
I/O14 I/O16
V
CC
V
SS
I/O12
I/O10
DU
CE
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
A
B
C
D
E
F
G
H
J
K
L
M
2
3
4
5
6
7
8
9
10
11
12
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 5 of 50
Pin Description
Name Description
I/O1 to I/O8
Command, address, data input/output
I/O9 to I/O16
Data input/output (
8 device: DU)
CLE
Command latch enable
ALE
Address latch enable
CE
Chip
enable
RE
Read enable
WE
Write enable
WP
Write protect
R/
B
Ready/
busy
PRE
Power on auto read enable
MRES
Master reset output
DSE
Deep standby enable
V
CC
Power
supply
V
SS
Ground
DU Don't
use
Note: 1. All V
SS
pins should be connected respectively.
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