Preliminary
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
Page 1 of 7
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
http://www.rfm.com
2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
OP4004B-041003
Quartz SAW Stabilized Differential Output Technology
Very Low Jitter Fundamental-Mode Operation at 625.00 MHz
Voltage Tunable for Phase Locked Loop Applications
Timing Reference for 10G Optical Ethernet Communications Systems
The OP4004B is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4004B are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4004B differential outputs fea-
ture 1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4004B is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
Value
Units
DC Suppy Voltage
0 to 5.5
Vdc
Tune Voltage
0 to 5.5
Vdc
Case Temperature
-55 to 100
C
625.00 MHz
Optical
Timing Clock
OP4004B
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. COCOM CAUTION: Approval by the U.S. Department of Commerce is required
prior to export of this device.
Notes:
1. Unless otherwise noted, all specifications include the combined effects of load VSWR, V
CC
and T
C
.
2. Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, V
CC
, T
C
and aging.
3. The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
4. Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a V
CC
= 3.0 Vdc.
5. Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
6. Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
7. Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 samples.
8. See Figure 4.
9. One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
Characteristic
Sym
Notes
Minimum
Typical
Maximum
Units
Operating Frequency
Absolute Frequency
f
O
1
625.00
MHz
Tuning Range
2
100
ppm
Tuning Voltage
1
0
3.3
Vdc
Tuning Linearity
1, 8
5
%
Tuning Sensitivity
df/dv
2
140
300
ppm/V
Modulation Bandwidth
50
kHz
Q and Q Output
Voltage into 50
(VSWR
1.2)
V
O
1,3
0.60
1.1
V
P-P
Operating Load VSWR
1,3
2:1
Symmetry
3, 4, 5
49
51
%
Harmonic Spurious
3, 4, 6
-30
dBc
Nonharmonic Spurious
3, 4, 6, 7
-60
dBc
Phase Noise
@ 100 Hz offset
3, 6
-70
dBc/Hz
@ 1 kHz offset
3, 6
-100
dBc/Hz
@ 10 kHz offset
3, 6
-125
dBc/Hz
Noise Floor
3, 6
-150
dBc/Hz
Q and Q Jitter
RMS Jitter
3, 4, 6, 7
2
ps
No Noise on V
CC
3, 4, 6, 7
12
ps
P-P
200 mV
P-P
Noise, from 1 MHz to f
O
on V
CC
3
12
ps
P-P
Input Impedence (Tuning Port)
1
K
Output DC Resistance (between Q & Q)
1, 3
50
K
DC Power Supply
Operating Voltage
V
CC
1, 3
3.13
3.3 or 5.0
5.25
Vdc
Operating Current
I
CC
1, 3
70
mA
Operating Case Temperature
T
C
1, 3
-40C
+85C
C
Lid Symbolization (YY=Year, WW=Week)
RFM OP4004B YYWW
SMC-08
Electrical Characteristics
625.00 MHz Optical Timing Clock
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
Page 2 of 7
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
http://www.rfm.com
2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
OP4004B-041003
OP4004B Performance Parameters
The OP4004B has been developed to achieve high performance in five parameters critical to optical data communications
applications:
Low Jitter and Phase Noise - low clock jitter (or low phase noise in the frequency domain) is critical to achieving low bit error
rates in optical data communications systems. The OP4004B provides very low free-running jitter and phase noise at 1/16
the 10 G ethernet clock rate, as shown in Figures 1 and 2. This makes the OP4004B an excellent reference for the generation
or regeneration of low-jitter clocks and data streams. The OP4004B achieves this performance over its full -40 to +85 C
operating temperature range using RFM's patented SAW oscillator architecture.
Single-Sideband Phase Noise
Figure 1
High Power Supply Noise Immunity - the OP4004B uses both differential active devices and differential SAW technology to
minimize the effects of power supply noise on jitter and phase noise, as shown in Figures 2 and 3. Optical data communi-
cations circuits must switch relatively high levels of current, making power supply noise immunity an important clock require-
ment.
Controlled Tuning Characteristics - the OP4004B voltage tuning constant, K
V
, is bounded between 140 and 300 ppm/V un-
der locked conditions for reference signals with 100 ppm or better stability over the OP4004B's full operating temperature
and supply voltage range. This allows a PLL based on the OP4004B to be designed with a well-controlled loop bandwidth
and damping factor, avoiding problems such a jitter peaking, etc. The voltage tuning characteristic of the OP4004B is mono-
tonic from 0 to 3.3 V, supporting reliable acquisition of phase lock. Figure 4 shows typical OP4004B tuning characteristics.
625.00 MHz Optical Timing Clock
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
Page 3 of 7
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
http://www.rfm.com
2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
OP4004B-041003
OP4004B Jitter Plot
No Power Supply Noise
OP4004B Jitter Plot
200 mV of Power Supply Noise
Figure 2
Figure 3
100
200
300
400
500
600
3.5
3.0
2.5
2.0
1.5
0
0.5
1.0
625.40
625.30
625.20
625.10
625.00
624.80
624.90
Tuning Voltage
Operating Frequency at +25 C in MHz
K
V
in ppm/V
Typical OP4004B Tuning Characteristics
0
Frequency
K
V
Voltage Tuning
Range for Lock
-40 to +85 C
Figure 4
625.00 MHz Optical Timing Clock
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
Page 4 of 7
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
http://www.rfm.com
2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
OP4004B-041003
Output DC Voltage Configurability - the OP4004B differential outputs can be DC-configured to support a wide range of high-
speed logic families and ASIC drive requirements by the selection of four resistors (see Configuring the OP4004B DC Output
Voltage below) and a logic supply voltage. Each differential output of the OP4004B is AC-coupled to provide this flexibility.
OP4004B Tuning Details
The frequency tuning of the OP4004B is characterized over a voltage range of 0 to 3.3 V. The tuning voltage applied to the
OP4004B should be limited to this range. Figure 4 shows the typical locked tuning range for operation over -40 or +85 C.
The frequency shift of a quartz SAW frequency control device with temperature has the shape of an inverted parabola, with
the highest frequency occurring around +25 C. At both -40 and +85 C, there will be a 170 ppm downward shift in the fre-
quency of the SAW device compared to +25 C. Tuning to compensate for this temperature shift is the same as tuning
170 ppm higher at +25 C. This is well within the tuning range of the OP4004B, as shown in Figure 4. Note that the voltage
tuning constant, K
V
, is bounded between 140 and 300 ppm/V under locked conditions for any temperature within the
OP4004B's specified operating range.
Differential Output Symmetry - for balanced output loads, the differential output symmetry of the OP4004B is 1%.
This differential output symmetry meets the requirements of the most demanding high-speed logic families.
The OP4004B tuning port presents a input impedance greater than 100 kilohms from DC to 50 kHz, and at least 1 kilohm
for any RF frequency up to the operating frequency of the OP4004B. Most operational amplifiers used in active loop filters
will be stable when driving the tuning port directly. Special care are should be taken to avoid ground loops in the path from
the output of the phase detector though the loop filter to the tuning input of the OP4004B. For most applications, the band-
width of the loop filter in a OP4004B PLL will be less than 50 Hz, as discussed in the example OP4004B PLL application
section below.
Configuring the OP4004B DC Output Voltage
Each differential output of the OP4004B is AC coupled, allowing the static DC level at each output to be set with a resistive
divider to match the logic family being driven by the clock. The parallel-equivalent resistance of the two resistors in each
divider should be approximately 50 ohms. The supply voltage to the dividers, V
LOAD
, should be two to three times the value
of the static DC voltage, V
DC
.
Referring to Figure 5:
V
DC
= V
LOAD
*R1/(R1 + R2)
and
50 = R1*R2/(R1 + R2)
The values of the resistors R2 and
R1 are given directly as:
R2 = 50*V
LOAD
/V
DC
R1 = 1/(0.02 - (1/R2))
R1
R1
R2
R2
3.3 Vdc
V
Load
OP4004B
TUNE
V
DC
V
DC
V
LOAD
OP4004B DC Output Voltage Adjustment
Figure 5
625.00 MHz Optical Timing Clock
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
Page 5 of 7
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
http://www.rfm.com
2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
OP4004B-041003
Table 1 provides R1 and R2 values for six high-speed logic families commonly used in optical data communications systems.
Note that the OP4004B can be used with logic families that run from a negative power supply voltage by simply using a
negative V
LOAD
voltage.
Table 1
Load Type
V
DC
R1
R2
V
LOAD
10k 3.3 V PECL
1.95
120
91
3.3 V
100k 3.3 V PECL
1.88
120
91
3.3 V
10k 5 V PECL
3.65
180
68
5.0 V
100k 5 V PECL
3.58
180
68
5.0 V
10k -5 V NECL
-1.30
240
62
-5.0 V
100k -5 V NECL
-1.42
240
62
-5.0 V
Loop Filter
Tune
+Vcc
Q
Q
N
PLL for Generating a High Stability 625 MHz Clock
OP4004B
External
Reference
Internal
Reference
(holdover)
Phase
Detector
Figure 6
Example OP4004B Phase-Locked Loop Application
One of the most important applications for the OP4004B is in a PLL circuit used to generate a very high quality 625.00 MHz
clock. The PLL combines the long-term stability of a precision external or internal 19.53125 MHz reference clock with the
very low jitter and phase noise of the OP4004B. A block diagram of the PLL is shown in Figure 6. A sample of the OP4004B
output is divided by 32 and is compared to a 19.53125 MHz reference clock in the phase detector. The loop filter at the output
of the phase detector is set to a very low bandwidth (less than 50 Hz typical). This imparts the long-term stability of the pre-
cision 19.53125 MHz reference to the OP4004B without degrading the OP4004B's low jitter and phase noise.
OP4004B Enable/Disable
Pin 3 on the OP4004B is the enable/disable control pin for the clock outputs. When Pin 3 is grounded, full output power is
available from the clock. When Pin 3 is pulled to Vcc, the power on the clock outputs is decreased at least 25 dB.
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