2-261
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Preliminary
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
VCC OUT
DCS OUT
VC
C2
DCS IN
BAND SELECT
VREG
VRAMP
TX ENABLE
VBATT
GSM OUT
VC
C2
GSM IN
10
11
12
1
3
2
6
5
4
9
8
7
RF3110
TRIPLE-BAND GSM/DCS/PCS
POWER AMP MODULE
3V Dual-Band GSM Handsets
Commercial and Consumer Systems
Portable Battery-Powered Equipment
GSM, E-GSM and DCS/PCS Products
GPRS Class 10 Compatible
The RF3110 is a high-power, high-efficiency power ampli-
fier module with integrated power control. The device is
self-contained with 50
input and output terminals. The
power control function is also incorporated, eliminating
the need for directional couplers, detector diodes, power
control ASICs and other power control circuitry; this
allows the module to be driven directly from the DAC out-
put. The device is designed for use as the final RF ampli-
fier in GSM/DCS and PCS handheld digital cellular
equipment and other applications in the 880 MHz to
915MHz, 1710MHz to 1785MHz and 1850MHz to
1910 MHz bands. On-board power control provides over
35dB of control range with an analog voltage input; and,
power down with a logic "low" for standby operation.
Complete Power Control Solution
Single 2.9V to 5.5V Supply Voltage
+35dBm GSM Output Power at 3.5V
+33dBm DCS/PCS Output Power at 3.5V
55% GSM and 55% DCS/PCS
EFF
10mmx10mm Package Size
RF3110
Triple-Band GSM/DCS/PCS Power Amp Module
RF3110 PCBA
Fully Assembled Evaluation Board
2
Rev A0 010921
1.70
1.45
0.450
0.075
0.
400
T
YP
1.
200
T
YP
1.
800
T
YP
2.
600
T
YP
3.
200
T
YP
4.
000
T
YP
4.
600
T
YP
5.
400
T
YP
6.
000
T
YP
6.
800
T
YP
7.
400
T
YP
8.
200
T
YP
8.
275
T
YP
8.
800
T
YP
9.
600
T
YP
9.600 TYP
8.800 TYP
8.200 TYP
7.400 TYP
6.800 TYP
6.000 TYP
5.400 TYP
4.600 TYP
4.000 TYP
3.200 TYP
2.600 TYP
1.800 TYP
1.200 TYP
0.400 TYP
0.000
9.
098
T
Y
P
0.
00
0
1.
79
7
8.
20
5
8.
28
0
1.245
4.075
5.925
8.747
0.306
Pin 1
10.00 0.10
Pin 1
10.00 0.10
Package Style: Module
Preliminary
2-262
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to +6.0
V
DC
Power Control Voltage (V
RAMP
)
-0.5 to +1.8
V
Input RF Power
+11.5
dBm
Duty Cycle at Max Power
37.5
%
Output Load VSWR
8:1
Operating Case Temperature
-40 to +85
C
Storage Temperature
-55 to +150
C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall (GSM Mode)
Temp= +25 C, V
CC
= 3.5V, V
RAMP
Max,
V
RAMP
= V
RAMP
Max, P
IN
=6dBm,
Freq= 880MHz to 915MHz, 12.5% Duty
Cycle, Pulse Width= 577
s
Operating Frequency Range
880 to 915
MHz
Maximum Output Power
+34.5
35.0
dBm
Temp = 25C, V
CC
= 3.5V,
V
RAMP
= V
RAMP
Max
+32.0
dBm
Temp= +85 C, V
CC
= 2.9V,
V
RAMP
= V
RAMP
Max
Total Efficiency
55
%
At P
OUT
,
MAX
, V
CC
= 3.5V
Input Power Range
+4
+6
+8
dBm
Full output power guaranteed at minimum
drive level
Output Noise Power
-86
dBm
RBW= 100kHz, 925MHz to 935MHz,
P
OUT
> +5dBm
-88
dBm
RBW= 100kHz, 935MHz to 960MHz,
P
OUT
> +5dBm
Forward Isolation
-35
-30
dBm
TX_ENABLE= 0V, PIN= +8dBm
Second Harmonic
-15
-5
dBm
Third Harmonic
-30
-15
dBm
All other Non-Harmonic Spurious
-36
dBm
Input Impedance
50
Input VSWR
2.5:1
P
OUT,MAX
-5dB< P
OUT
<P
OUT,MAX
Output Load VSWR
8:1
Spurious<-36dBm, V
RAMP
=0.2V to 1.6V,
RBW= 3MHz
Output Load Impedance
50
Load impedance presented at RF OUT pad
Power Control V
RAMP
Power Control "ON"
1.6
V
Max. P
OUT
, Voltage supplied to the input
Power Control "OFF"
0.2
0.25
V
Min. P
OUT
, Voltage supplied to the input
Power Control Range
35
dB
V
RAMP
= 0.2V to 1.6V
V
RAMP
Input Capacitance
15
pF
DC to 2MHz
V
RAMP
Input Current
10
A
V
RAMP
= 1.6V
Turn On/Off Time
4
S
V
RAMP
=0 to 1.6V
Note: V
RAMP
Max=3/8*VBATT+0.18<1.6V
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Preliminary
2-263
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall Power Supply
Power Supply Voltage
3.5
V
Specifications
2.9
5.5
V
Nominal operating limits, P
OUT
< +33dBm
Power Supply Current
2
A
DC Current at P
OUT,MAX
1
10
A
P
IN
< -30dBm, V
RAMP
=0V,
Temp= -40C to +85C
V
REG
Voltage
2.7
2.8
2.9
V
V
REG
Current
7
mA
TX Enable= High
10
A
TX Enable= Low
Overall (DSC/PCS Mode)
Temp= 25C, V
CC
= 3.5V, V
RAMP
= V
RAMP
Max, P
IN
= 6dBm, Freq= 1710MHz to
1785MHz, 12.5% Duty Cycle, pulse
width= 577
s
Operating Frequency Range
1710 to 1910
MHz
Maximum Output Power
+32
+33
dBm
Temp= 25C, V
CC
= 3.5V, V
RAMP
= V
RAMP
Max, 1710MHz to 1785MHz
31.5
dBm
1850- 1910MHz
30
dBm
Temp= +85C, V
CC
= 2.9V, V
RAMP
= V
RAMP
Max, 1710MHz to 1785MHz
29.5
dBm
1850MHz to 1910MHz
Total Efficiency
45
52
%
At P
OUT,MAX,
V
CC
= 3.5V, 1710- 1785MHz
45
1850- 1910MHz
Input Power Range
+4
+6
+8
dBm
Full output power guaranteed at minimum
drive level
Output Noise Power
-77
dBm
RBW =100kHz, 1805MHz to 1880MHz and
1930MHz to 1990MHz, P
OUT
> 34.5dBm,
V
CC
= 3.5V
Forward Isolation
-37
-30
dBm
TX_ENABLE =0V, P
IN
=+8dBm
Second Harmonic
-25
-15
dBm
P
OUT,
= +32.5dBm
Third Harmonic
-30
-15
dBm
All other Non-Harmonic Spurious
-36
dBm
Input Impedance
50
Input VSWR
-
2.5
P+ 5dB <P
OUT
< P
OUT,MAX
Output Load VSWR
8:1
Spurious <-36dBm, V
APCDCS
= 0.2V to 1.5V,
RBW =3MHz
Output Load Impedance
50
Load impedance presented at RF OUT pin
Power Control V
RAMP
Power Control "ON"
1.6
V
Max. P
OUT
, Voltage supplied to the input
Power Control "OFF"
0.2
0.25
V
Min. P
OUT
, Voltage supplied to the input
Power Control Range
33
dB
V
RAMP
= 0.15V to 1.6V, P
IN
=+8dBm
V
RAMP
Input Capacitance
15
pF
DC to 2MHz
V
RAMP
Input Current
10
A
V
RAMP
= 1.6V
10
A
V
RAMP
=0V
Turn On/Off TIme
4
s
V
RAMP
=0to1.6V
Note: V
RAMP
max=3/8* VBATT +0.18<1.6V
Preliminary
2-264
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall Power Supply
Power Supply Voltage
3.5
V
Specifications
2.9
5.5
V
Nominal operating limits, P
OUT
<+33dBm
Power Supply Current
1.3
A
DC Current at P
OUT,MAX
1
10
A
P
IN
<-30dBm, V
RAMP
=0V,
Temp= -40C to +85C
V
REG
Voltage
2.7
2.8
2.9
V
V
REG
Current
7
mA
TX Enable= High
10
A
TX Enable= Low
Preliminary
2-265
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Pin
Function
Description
Interface Schematic
1
DCS IN
RF input to the DCS band. This is a 50
input.
2
BAND
SELECT
Allows external control to select the GSM or DCS band with a logic high
or low. A logic low enables the GSM band whereas a logic high enables
the DCS band.
3
TX ENABLE
This signal enables the PA module for operation with a logic high. Once
TX Enable is asserted the RF output level will increase to 0dBm.
4
VBATT
Power supply for the module. This should be connected to the battery.
5
VREG
Regulated voltage input for power control function. (2.8V nom)
6
VRAMP
Ramping signal from DAC. A simple RC filter may need to be con-
nected between the DAC output and the VRAMP input depending on
the baseband selected. The ramping profiles shown later in the data
sheet are recommended profiles for meeting the GSM specification for
burst timing and transient spectrum.
7
GSM IN
RF input to the GSM band. This is a 50
input.
8
VCC2
Controlled voltage input to driver stage for GSM bands. This voltage is
part of the power control function for the module. This node must be
connected to V
CC
out.
9
GSM OUT
RF output for the GSM band. This is a 50
output. The output load line
matching is contained internal to the package.
10
VCC OUT
Controlled voltage output to feed V
CC2
. This voltage is part of the
power control function for the module. It can not be connected to any-
thing other than V
CC2
, nor can any component be placed on this node
(i.e. decoupling capacitor).
11
DCS OUT
RF output for the DCS band. This is a 50
output. The output load line
matching is contained internal to the package.
12
VCC2
Controlled voltage input to DCS driver stage. This voltage is part of the
power control function for the module. This node must be connected to
V
CC
out
Pkg
Base
GND
Preliminary
2-266
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Pin Out
VCC
2
DCS IN
BAND SELECT
TX EN
VBATT
VREG
VRAMP
GSM IN
VC
C2
GSM OUT
VCC
PCS OUT
10.0000
PIN #1
10.0000
Preliminary
2-267
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Application Schematic
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
10
11
12
1
3
2
6
5
4
9
8
7
50
strip
50
strip
50
strip
50
strip
DCS/PCS IN
BAND SELECT
TX ENABLE
VBATT
VREG
VRAMP
GSM IN
DCS/PCS OUT
GSM OUT
180
180
15 k
**
** Used to filter noise and spurious from base band.
10
11
12
1
3
2
6
5
4
9
8
7
50
strip
50
strip
50
strip
50
strip
BAND SELECT
TX ENABLE
VBATT
VREG
VRAMP
3.3
F*
1 nF*
*Not required in most applications
GND
P1
1
CON1
DCS/PCS IN
GSM IN
DCS/PCS OUT
GSM OUT
** Used to filter noise and spurious from base band.
180
15 k
**
VCC
P2
1
CON1
P2-1
180
Preliminary
2-268
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Theory of Operation
Overview
The RF3110 is a triple-band GSM/DCS/PCS power
amplifier module that incorporates an indirect closed
loop method of power control. This simplifies the
phone design by eliminating the need for the compli-
cated control loop design. The indirect closed loop is
fully self contained and required does not require loop
optimization. It can be driven directly from the DAC out-
put in the baseband circuit.
Theory of Operation
The indirect closed loop is essentially a closed loop
method of power control that is invisible to the user.
Most power control systems in GSM sense either for-
ward power or collector/drain current. The RF3110
does not use a power detector. A high-speed control
loop is incorporated to regulate the collector voltages
of the amplifier while the stages are held at a constant
bias. The V
RAMP
signal is multiplied and the collector
voltages are regulated to the multiplied V
RAMP
voltage.
The basic circuit is shown in the following diagram.
By regulating the power, the stages are held in satura-
tion across all power levels. As the required output
power is decreased from full power down to 0dBm, the
collector voltage is also decreased. This regulation of
output power is demonstrated in Equation 1 where the
relationship between collector voltage and output
power is shown. Although load impedance affects out-
put power, supply fluctuations are the dominate mode
of power variations. With the RF3110 regulating collec-
tor voltage, the dominant mode of power fluctuations is
eliminated.
(Eq. 1)
There are several key factors to consider in the imple-
mentation of a transmitter solution for a mobile phone.
Some of them are:
Effective efficiency (
eff
)
Current draw and system efficiency
Power variation due to Supply Voltage
Power variation due to frequency
Power variation due to temperature
Input impedance variation
Noise power
Loop stability
Loop bandwidth variations across power levels
Burst timing and transient spectrum trade offs
Harmonics
Talk time and power management are key concerns in
transmitter design since the power amplifier has the
highest current draw in a mobile terminal. Considering
only the power amplifier's efficiency does not provide a
true picture for the total system efficiency. It is impor-
tant to consider effective efficiency which is repre-
sented by
EFF
.
(
EFF
considers the loss between the
PA and antenna and is a more accurate measurement
to determine how much current will be drawn in the
application).
EFF
is defined by the following relation-
ship (Equation 2):
(Eq. 4)
Where Pn is the sum of all positive and negative RF
power, P
IN
the input power and P
DC
is the delivered
DC power. In dB the formula becomes (Equation 3):
(Eq. 3)
RF IN
TX ENABLE
RF OUT
H(s)
VRAMP
TX ENABLE
VBATT
P
dBm
10
2 V
CC
V
SAT
(
)
2
8 R
LOAD
10
3
-------------------------------------------
log
=
E FF
P
N
P
IN
n
1
=
m
P
DC
-------------------------------- 100
=
E FF
10
P
PA
P
LOS S
+
10
------------------------------
10
P
IN
10
--------
V
BAT
I
BAT
10
-------------------------------------------------
=
Preliminary
2-269
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Where P
PA
is the output power from the PA, P
LOSS
the
insertion loss, P
IN
the input power to the PA and P
DC
the delivered DC power.
The RF3110 improves the effective efficiency by mini-
mizing the P
LOSS
term in the equation. A directional
coupler may introduce 0.4dB to 0.5dB loss to the tran-
sit path. To demonstrate the improvement in effective
efficiency consider the following example:
Conventional PA Solution:
RF3110 Solution:
The RF3110 solution improves effective efficiency 5%.
Output power does not vary due to supply voltage
under normal operating conditions if V
RAMP
is suffi-
ciently lower than V
BATT
. By regulating the collector
voltage to the PA the voltage sensitivity is essentially
eliminated. This covers most cases where the PA will
be operated. However, as the battery discharges and
approaches its lower power range the maximum output
power from the PA will also drop slightly. In this case it
is important to also decrease V
RAMP
to prevent the
power control from inducing switching transients.
These transients occur as a result of the control loop
slowing down and not regulating power in accordance
with V
RAMP
.
The switching transients due to low battery conditions
are regulated by incorporating the following relation-
ship limiting the maximum V
RAMP
voltage (Equation 2).
Although no compensation is required for typical bat-
tery conditions, the battery compensation required for
extreme conditions is covered by the relationship in
Equation 4. This should be added to the terminal soft-
ware.
(Eq. 4)
Note: Output power is limited by battery voltage. The
relationship in Equation 4 does not limit output power.
Equation 4 limits the V
RAMP
voltage to correspond with
the battery voltage.
Due to reactive output matches, there are output power
variations across frequency. There are a number of
components that can make the effects greater or less.
The components following the power amplifier often
have insertion loss variation with respect to frequency.
Usually, there is some length of microstrip that follows
the power amplifier. There is also a frequency
response found in directional couplers due to variation
in the coupling factor over frequency, as well as the
sensitivity of the detector diode. Since the RF3110
does not use a directional coupler with a diode detec-
tor, these variations do not occur.
Input impedance variation is found in most GSM power
amplifiers. This is due to a device phenomena where
C
BE
and C
CB
(C
GS
and C
SG
for a FET) vary over the
bias voltage. The same principle used to make varac-
tors is present in the power amplifiers. The junction
capacitance is a function of the bias across the junc-
tion. This produces input impedance variations as the
Vapc voltage is swept. Although this could present a
problem with frequency pulling the transmit VCO off
frequency, most synthesizer designers use very wide
loop bandwidths to quickly compensate for frequency
variations due to the load variations presented to the
VCO.
The RF3110 presents a very constant load to the VCO.
This is because all stages of the RF3110 are run at
constant bias. As a result, there is constant reactance
at the base emitter and base collector junction of the
input stage to the power amplifier.
P
PA
= +33 dBm
P
IN
= +6 dBm
P
LOSS
= -0.4 dB
V
BAT
= 3.5 V
I
BAT
= 1.1 A
EFF
= 47.2%
P
PA
= +33 dBm
P
IN
= +6 dBm
P
LOSS
= 0 dB
V
BAT
= 3.5 V
I
BAT
= 1.1 A
EFF
= 51.72%
V
RAM P
3
8
--- V
BAT T
0.18
+
Preliminary
2-270
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Noise power in PA's where output power is controlled
by changing the bias voltage is often a problem when
backing off of output power. The reason is that the gain
is changed in all stages and according to the noise for-
mula (Equation 5),
(Eq. 5)
the noise figure depends on noise factor and gain in all
stages. Because the bias point of the RF3110 is kept
constant the gain in the first stage is always high and
the overall noise power is not increased when decreas-
ing output power.
Power control loop stability often presents many chal-
lenges to transmitter design. Designing a proper power
control loop involves trade-offs affecting stability, tran-
sient spectrum and burst timing.
In conventional architectures the PA gain (dB/ V) varies
across different power levels, and as a result the loop
bandwidth also varies. With some power amplifiers it is
possible for the PA gain (control slope) to change from
100dB/V to as high as 1000dB/V. The challenge in this
scenario is keeping the loop bandwidth wide enough to
meet the burst mask at low slope regions which often
causes instability at high slope regions.
The RF3110 loop bandwidth is determined by internal
bandwidth and the RF output load and does not
change with respect to power levels. This makes it eas-
ier to maintain loop stability with a high bandwidth loop
since the bias voltage and collector voltage do not vary.
An often overlooked problem in PA control loops is that
a delay not only decreases loop stability it also affects
the burst timing when, for instance the input power
from the VCO decreases (or increases) with respect to
temperature or supply voltage. The burst timing then
appears to shift to the right especially at low power lev-
els. The RF3110 is insensitive to a change in input
power and the burst timing is constant and requires no
software compensation.
Switching transients occur when the up and down
ramp of the burst is not smooth enough or suddenly
changes shape. If the control slope of a PA has an
inflection point within the output power range or if the
slope is simply to steep it is difficult to prevent switch-
ing transients. Controlling the output power by chang-
ing the collector voltage is as earlier described based
on the physical relationship between voltage swing and
output power. Furthermore all stages are kept con-
stantly biased so inflection points are nonexistent.
Harmonics are natural products of high efficiency
power amplifier design. An ideal class "E" saturated
power amplifier will produce a perfect square wave.
Looking at the Fourier transform of a square wave
reveals high harmonic content. Although this is com-
mon to all power amplifiers, there are other factors that
contribute to conducted harmonic content as well. With
most power control methods a peak power diode
detector is used to rectify and sense forward power.
Through the rectification process there is additional
squaring of the waveform resulting in higher harmon-
ics. The RF3110 address this by eliminating the need
for the detector diode. Therefore the harmonics com-
ing out of the PA should represent the maximum power
of the harmonics throughout the transmit chain. This is
based upon proper harmonic termination of the trans-
mit port. The receive port termination on the T/R switch
as well as the harmonic impedance from the switch
itself will have an impact on harmonics. Should a prob-
lem arise, these terminations should be explored.
The RF3110 incorporates many circuits that had previ-
ously been required external to the power amplifier.
The shaded area of the diagram below illustrates those
components and the following table itemizes a compar-
ison between the RF3110 Bill of Materials and a con-
ventional solution:
Note: Output power is limited by battery voltage. The
relationship in Equation 4 does not limit output power.
Equation 4 limits V
RAMP
to correspond with the battery
voltage.
F
TOT
F1
F2
1
G1
----------------
F3
1
G1 G2
-------------------
+
+
=
Component
Conventional
Solution
RF3110
Power Control ASIC
$0.80
N/A
Directional Coupler
$0.20
N/A
Buffer
$0.05
N/A
Attenuator
$0.05
N/A
Various Passives
$0.05
N/A
Mounting Yield
(other than PA)
$0.12
N/A
Total
$1.27
$0.00
Preliminary
2-271
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
1
2
3
4
5
6
7
14
13
12
11
10
9
8
From DAC
*Shaded area eliminated with Indirect Closed Loop using RF3110
Preliminary
2-272
RF3110
Rev A0 010921
2
PO
W
E
R
A
M
P
LI
FI
E
R
S
Evaluation Board Layout
Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-layer
PDF 
ZIP