2-689
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT
SiGe Bi-CMOS
RF IN
RF OUT
VCC1
NC
N
C
VMODE
NC
VREG
NC
GND
VCC2
VCC2
VCC2
NC
NC
NC
16
15
14
13
1
2
3
4
8
7
6
5
9
10
11
12
Bias
RF3163
3V 900MHZ LINEAR POWER
AMPLIFIER MODULE
3V CDMA/AMPS Cellular Handset
3V CDMA2000/1XRTT Cellular Handset
3V CDMA2000/1X-EV-DO US-Cellular
Handset
Spread-Spectrum System
The RF3163 is a high-power, high-efficiency linear ampli-
fier module specifically designed for 3V handheld sys-
tems. The device is manufactured on an advanced third
generation GaAs HBT process, and was designed for use
as the final RF amplifier in 3V IS-95/CDMA 2000
1X/AMPS handheld digital cellular equipment, spread-
spectrum systems, and other applications in the 824MHz
to 849MHz band. The RF3163 has a digital control line
for low power applications to lower quiescent current. The
RF3163 is assembled in a 16-pin, 3mmx3mm, QFN
package.
Input Internally Matched@50
Output Internally Matched
28dBm Linear Output Power
41% Peak Linear Efficiency
-51dBc ACPR @ 885kHz
55% AMPS Efficiency
RF3163
3V 900MHz Linear Power Amplifier Module
RF3163 PCBA
Fully Assembled Evaluation Board
0
Rev A0 040730
3.00
-B-
3.00
-A-
0.10 C
0.10 C
0.10 C
0.10 C
SCALE:
NONE
SEATING
PLANE
-C-
0.05
0.00
0.08 C
0.10 C
1.00
0.80
0.50 TYP.
1.45
+0.10
-0.15
1.45
+0.10
-0.15
0.30
0.18
TYP.
0.50
0.30
TYP.
0.10
C A B
M
Shaded areas represent pin 1.
Dimensions in mm.
Package Style: QFN, 16-Pin, 3x3
2-690
RF3163
Rev A0 040730
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage (RF off)
+8.0
V
Supply Voltage (P
OUT
31dBm)
+5.2
V
Control Voltage (V
REG
)
+3.9
V
Input RF Power
+10
dBm
Mode Voltage (V
MODE
)
+3.9
V
Operating Temperature
-30 to +110
C
Storage Temperature
-40 to +150
C
Moisture Sensitivity Level
(IPC/JEDEC J-STD-20)
MSL 2 @ 260C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
High Power Mode
(V
MODE
Low)
T=25
o
C Ambient, V
CC
=3.4V, V
REG
=2.8V,
V
MODE
=0V, and P
OUT
=28dBm for all
parameters (unless otherwise specified).
Operating Frequency Range
824
849
MHz
Linear Gain
26.0
28.5
dB
Second Harmonics
-35
-30
dBc
Third Harmonics
-40
-30
dBc
Maximum Linear Output
28
Linear Efficiency
36
41
%
Maximum I
CC
455
515
mA
ACPR @ 885kHz
-51
-46
dBc
ACPR @ 1.98MHz
-58
-55
dBc
Input VSWR
2:1
Stability in Band
6:1
No oscillation>-70dBc
Stability out of Band
10:1
No damage
Noise Power
-133
dBm/Hz
At 45MHz offset.
Low Power Mode
(V
MODE
High)
T=25
o
C Ambient, V
CC
=3.4V, V
REG
=2.8V,
V
MODE
=2.8V, and P
OUT
=18dBm for all
parameters (unless otherwise specified).
Operating Frequency Range
824
849
MHz
Linear Gain
21
24
dB
Maximum Linear Output
18
Maximum I
CC
125
mA
P
OUT
=16dBm
ACPR @885kHz
-51
-46
dBc
ACPR @1.98MHz
-61
-56
dBc
Input VSWR
2:1
Output VSWR Stability
6:1
No oscillation>-70dBc
10:1
No damage
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
2-691
RF3163
Rev A0 040730
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
FM Mode
T=25
o
C Ambient, V
CC
=3.4V, V
REG
=2.8V,
V
MODE
=0V, and P
OUT
=31dBm for all
parameters (unless otherwise specified).
Operating Frequency Range
824
849
MHz
AMPS Maximum Output Power
31
dBm
AMPS Efficiency
48
55
%
AMPS Gain
24
28
AMPS Second Harmonics
-35
-30
dBc
AMPS Third Harmonics
-40
-30
dBc
Power Supply
Supply Voltage
3.2
3.4
4.2
V
High Gain Idle Current
55
80
mA
V
MODE
=low and V
REG
=2.8V
Low Gain Idle Current
45
70
mA
V
MODE
=high and V
REG
=2.8V
V
REG
Current
4.5
5.5
mA
V
MODE
=high
V
MODE
Current
250
uA
RF Turn On/Off Time
6
uS
DC Turn On/Off Time
40
uS
Total Current (Power Down)
0.2
5.0
uA
V
REG
Low Voltage
0
0.5
V
V
REG
High Voltage
(Recommended)
2.75
2.8
2.95
V
V
REG
High Voltage
(Operational)
2.7
3.0
V
V
MODE
Voltage
0
0.5
V
High Gain Mode
2.0
2.8
V
Low Gain Mode
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RF3163
Rev A0 040730
Pin
Function
Description
Interface Schematic
1
NC
No connection. Do not connect this pin to any external circuit.
2
VREG
Regulated voltage supply for amplifier bias circuit. In power down
mode, both V
REG
and V
MODE
need to be LOW (<0.5V).
3
VMODE
For nominal operation (High Power mode), V
MODE
is set LOW. When
set HIGH, devices are biased lower to improve efficiency.
4
RF IN
RF input internally matched to 50
. This input is internally AC-coupled.
5
VCC1
First stage collector supply. A 2200pF and 4.7
F decoupling capacitor
are required.
6
NC
No connection. Do not connect this pin to any external circuit.
7
NC
No connection. Do not connect this pin to any external circuit.
8
GND
Ground connection.
9
VCC2
Output stage collector supply. Please see the schematic for required
external components.
10
VCC2
Same as pin 9.
11
VCC2
Same as pin 9.
12
RF OUT
RF output. Internally AC-coupled.
13
NC
No connection. Do not connect this pin to any external circuit.
14
NC
No connection. Do not connect this pin to any external circuit.
15
NC
No connection. Do not connect this pin to any external circuit.
16
NC
No connection. Do not connect this pin to any external circuit.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
2-693
RF3163
Rev A0 040730
Evaluation Board Schematic
16
15
14
13
1
2
3
4
8
7
6
5
9
10
11
12
Bias
C3
2200 pF
C30
4.7
F
VREG
VMODE
C40
4.7
F
50
strip
J1
RF IN
VCC1
C20
4.7
F
C3
2200 pF
L*
C10
4.7
F
C1
2200 pF
VCC2
50
strip
J2
RF OUT
GND
P1-3
VCC1
P1-5
VCC2
GND
GND
P1
1
2
3
4
5
CON5
P2
1
2
3
4
5
CON5
GND
P2-3
VREG
GND
GND
P2-5
VMODE
*
The current rating for the inductor needs to be 1A.
One example is Toko 0603 multilayer inductor with the
value of 1.8 nH (Toko part number LL1608-F1N8S).
The value of the inductor can be from 1.5nH to 2.2nH.
Different values of the inductor will give slight shift on
the tradeoff between efficiency and ACPR.
2-694
RF3163
Rev A0 040730
Electrostatic Discharge Sensitivity
Human Body Model (HBM)
Figure 3 shows the HBM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A114.
Machine Model (MM)
Figure 4 shows the MM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A115.
16
15
14
13
1
2
3
4
8
7
6
5
9
10
11
12
>2000 V NC
2000 V VREG
2000 V VMODE
2000 V RF IN
2000 V VC
C1
2000 V N
C
>2000 V N
C
GN
D
2000 V VCC2
2000 V VCC2
750 V VCC2
750 V RF OUT
>
2
000 V NC
750 V NC
>
2
000 V NC
800 V NC
Figure 3. ESD Level - Human Body Model
16
15
14
13
1
2
3
4
8
7
6
5
9
10
11
12
>300 V NC
200 V VREG
200 V VMODE
200 V RF IN
150 V VCC1
200 V NC
>
300 V NC
GND
200 V VCC2
200 V VCC2
275 V VCC2
250 V RF OUT
>300 V
NC
250 V NC
>300 V
NC
250 V NC
Figure 4. ESD Level - Machine Model
2-695
RF3163
Rev A0 040730
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is
3
inch to 8
inch gold over 180
inch nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 0.64 x 1.28 (mm)
D = 1.50 (mm) Sq.
Dimensions in mm.
A
D
A
A
A
B
B
B
B
C
A
B
B
B
B
Pin 8
Pin 12
Pin 1
Pin 16
1.50 Typ.
0.50 Typ.
0.50 Typ.
0.55 Typ.
0.75 Typ.
0.55 Typ.
1.00 Typ.
0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
2-696
RF3163
Rev A0 040730
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the
device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating
routing strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Pin 8
Pin 12
Pin 1
Pin 16
A
C
A
A
A
B
B
B
B
A
A
A
A
B
B
B
B
1.50 Typ.
0.50 Typ.
0.50 Typ.
0.55 Typ.
0.75
0.55 Typ.
0.75
1.50 Typ.
A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 1.60 (mm) Sq.
Dimensions in mm.
Figure 2. PCB Solder Mask Pattern (Top View)
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