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BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
I
2
C BUS compatible serial EEPROM
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W /
BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W /
BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
The BR24C01A-W, BR24C02-W, and BR24C04-W series are 2-wire (I
2
C BUS type) serial EEPROMs which are
electrically programmable.
I
2
C BUS is a registered trademark of Philips.
!
!
!
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Applications
VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches
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Features
1) 128
8bits (1k) serial EEPROM.
(BR24C01A-W / AF-W / AFJ-W / AFV-W)
256
8bits (2k) serial EEPROM.
(BR24C02-W / F-W / FJ-W / FV-W)
512
8bits (4k) serial EEPROM.
(BR24C04-W / F-W / FJ-W / FV-W)
2) Two wire serial interface.
3) Operating voltage range : 2.7V
5.5V
4) Low current consumption
Active (at 5V) : 1.5mA (Typ.)
Standby (at 5V) : 0.1
A (Typ.)
5) Auto erase and auto complete functions can be used
during write operations.
6) Page write function.
BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes
BR24C02-W / F-W / FJ-W / FV-W : 8 bytes
BR24C04-W / F-W / FJ-W / FV-W : 16 bytes
7) DATA security
Write protect feature
Inhibit to WRITE at low V
CC
8) Noise filters at SCL and SDA pins.
9) Address can be incremented automatically during
read operations.
10) Compact packages.
11) Rewriting possible up to 100,000 times
12) Data can be stored for ten years without corruption.
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Absolute maximum ratings (Ta = 25
C)
Parameter
Symbol
Limits
Unit
Applied voltage
-
0.3
~
+
6.5
V
Power dissipation
mW
Storage temperature
-
65
~
+
125
C
Operating temperature
C
Input voltage
-
V
-
40
~
+
85
V
CC
-
0.3
~V
CC
+
0.3
Pd
Tstg
Topr
300(SSOP
-
B8)
1
800(DIP8)
450(SOP8, SOP
-
J8)
2
3
1 Reduced by 3.0mW for each increase in Ta of 1
C over 25
C.
2 Reduced by 4.5mW for each increase in Ta of 1
C over 25
C.
3 Reduced by 8.0mW for each increase in Ta of 1
C over 25
C.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!
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Recommended operating conditions (Ta = 25
C)
Parameter
Symbol
Limits
Unit
Power supply voltage
V
V
Input voltage
V
IN
V
V
CC
0
~V
CC
2.7
~5.5 (WRITE)
2.7
~5.5 (READ)
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!
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Block diagram
BR24C01A-W / AF-W / AFJ-W / AFV-W
1kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START
STOP
7bits
7bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
V
CC
LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
BR24C02-W / F-W / FJ-W / FV-W
2kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START
STOP
8bits
8bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
V
CC
LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
BR24C04-W / F-W / FJ-W / FV-W
4kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START
STOP
9bits
9bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
V
CC
LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
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Pin descriptions
Pin name
Function
A0, A1, A2
Slave address setting pin
SCL
Serial data clock
SDA
Serial data input / output
WP
Write protect pin
V
CC
Power supply
GND
Ground
An open drain output requires a pull-up resistor.
Slave address setting pin
SCL
SDA
WP
Write protect pin
Power supply
GND
Ground
Pin name
Function
Serial data clock
Serial data input / output
A0, A1, A2
V
CC
An open drain output requires a pull-up resistor.
Pin name
A0
N.C.
SCL
SDA
WP
Write protect pin
Power supply
GND
Ground
Function
A1, A2
Slave address setting pin
Serial data clock
Serial data input / output
V
CC
An open drain output requires a pull-up resistor.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!
!
!
Electrical characteristics
DC characteristics (unless otherwise noted, Ta =
-40 to + 85 C, V
CC
= 2.7 to 5.5V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
V
IH
-
-
V
V
IL
-
-
0.3V
CC
V
V
OL
-
-
0.4
V
Input leakage current
I
LI
-
1
A
V
IN
=
0V
~V
CC
Output leakage current
I
LO
-
1
-
1
-
1
A
operatingcurrent dissipation
I
CC
-
2.0
mA
Standby current
I
SB
-
-
-
2.0
A
0.7V
CC
-
-
I
OL
=
3.0mA(SDA)
V
CC
=
5.5V, f
SCL
=
400kHz
A0, A1, A2
=
GND, WP
=
GND
V
OUT
=
0V
~V
CC
Input high level voltage
Input low level voltage
Output low level coltage
V
CC
=
5.5V, SDA
SCL
=
V
CC
Not designed for radiation resistance.
Operating timing characteristics (unless otherwise noted, Ta =
-40 to + 85 C, V
CC
= 2.7 to 5.5V)
Parameter
Symbol
Vcc
=
5V
10%
Vcc
=
3V
10%
Unit
f
SCL
kHz
t
HIGH
Noise erase valid time (SCL / SDA pins)
t
I
s
Data clock HIGH time
SCL frequency
s
Data clock LOW time
t
LOW
s
SDA / SCL rise time
t
R
s
SDA / SCL fall time
t
F
s
Start condition hold time
t
HD
: STA
s
Start condition setup time
t
SU
: STA
s
Input data hold time
t
HD
: DAT
ns
Input data setup time
t
SU
: DAT
ns
Output data delay time
t
PD
s
Output data hold time
t
DH
s
Stop condition setup time
t
SU
: STO
s
Bus open time before start of transfer
t
BUF
s
t
WR
Min.
-
0.6
-
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
0.05
-
0.3
0.3
-
-
-
-
0.9
-
-
-
10
Min.
-
4.0
-
4.7
-
-
4.0
4.7
0
250
0.2
0.2
4.7
4.7
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
100
-
0.1
-
1.0
0.3
-
-
-
-
3.5
-
-
-
10
ms
Internal write cycle time
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!
!
!
Timing charts
t
BUF
t
DH
t
PD
t
HIGH
t
HD
:
STA
t
LOW
t
F
t
R
SDA
SDA
SCL
START BIT
STOP BIT
SCL
SDA
Data is read on the rising edge of SCL.
Data is output in synchronization with the falling edge of SCL.
t
SU
: DAT
t
HD
: DAT
t
SU
: STO
t
HD
: STA
t
SU
: STA
(output)
(input)
Fig.1 Synchronized data input / output timing
ACK
D0
(n address)
t
WR
SDA
SCL
Start condition
Stop condition
Write data
Fig.2 Write cycle timing
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!
!
!
Circuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from
LOW to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(4) Device addressing
BR24C01A-W / AF-W / AFJ-W / AFV-W, BR24C02-W / F-W / FJ-W / FV-W
1) Make sure the slave address is output from the master immediately after the start condition.
2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is
fixed at "1010".
3) The next three bits of the slave address (A2, A1, A0 ... device address) are used to select the device. This IC
can address up to eight devices on the same bus.
4) The lowermost bit of the slave address (R / W ... READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 ... Write
(Random read word address setting is also 0)
R / W set to 1 ... Read
A2
A1
A0
1010
R / W
BR24C04-W / F-W / FJ-W / FV-W
1) Make sure the slave address is output from the master in continuation with the start condition.
2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is
fixed at "1010".
3) The next two bits of the slave address (A2, A1, ... device address) are used to select the device. This IC can
address up to four devices on the same bus.
4) The next bit of the slave address (PS ... Page Select) is used to select the page. As shown below, it can write to
or read from any of the 256 words in the two pages in memory.
PS set to 0 ... Page 1 (000 to 0FF)
PS set to 1 ... Page 2 (100 to 1FF)
5) The lowermost bit of the slave address (R / W ... READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 ... Write
(Random read word address setting is also 0)
R / W set to 1 ... Read
A2
A1
PS
1010
R / W
(5) Write protect (WP)
When WP pin set to V
CC
(High level), write protect is set by all address. When WP pin set to GND (Low level),
enable to write to all address. Either control this pin or connect to GND (or V
CC
). It is inhibited from being left
unconnected.
(6) ACK signal
The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer
is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data
output (
-COM when a write or read command of the slave address input ; this IC when reading data).
For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is
sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address
input,
-COM when a read command data output).
The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8
bits).
When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight
bits of data (word address and write data).
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