sames

SA9203/5

PDS039-SA9203/5-001

REV. A

20-08-96

FEATURES

Six (SA9203) or three (SA9205) 8-Bit
I/O Ports

Each bit of one port independently
programmable as input or output

Five (SA9203) or two (SA9205)
remaining ports can be individually
configured as input or output. (Direction
applicable to all 8 pins of each port.)

One 8-Bit port programmable as either
atched or transparent inputs

Supports byte-wide and bit-wide I/O
port addressing modes on all ports

Readback of all control and port
registers

Interfaces directly with multiplexed
address and data bus microprocessors/
microcontrollers

Internal address latch

Single +5V power supply

Low power CMOS

Completely static operation

TTL-level compatibility

4491

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6/3 X 8 PORT EXPANDER

DESCRIPTION

The SAMES SA9203/5 Port Expander is a
CMOS device suited to microprocessor
based applications requiring input/output
port expansion. The device interfaces very
simply to any microcontroller/micro-
processor with a multiplexed address/data
bus structure.

The SA9203 includes 8 independently
programmable I/O pins for Port A and Port
B to F (5 ports) independently programmable
as I/O. It is packaged in a PCB efficient 68
pin PLCC package. The SA9205 includes
8 independently programmable I/O pins for
Port A with Port B and Port C as indepen-
dently programmable I/O, packaged in a
cost effective 44 pin PLCC package.

FIGURE 1: PIN CONNECTION FOR
SA9203

SA9203

D R - 0 1 2 6 6

4
5

PB
PB

33 34

29 30

STB

1
2
3

5
6

PA
PA
PA

PA
PA

13
14

D D

RST

INT

ALE

PE 6

41 42

36 37 38 39

PE
PE 0

45
44

66 65 64

PF
PF 0

PF 6

PE 7

V DD

PF 7

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FIGURE 2: BLOCK DIAGRAM FOR SA9203

FIGURE 3: PIN CONNECTION FOR SA9205

Inter

DR-01267

face

AD(7:0

CON

PRTB

CON

PRTA

�
�

INT

RST

ALE
CS
RD

STB

POR

PE(7:

PF(7:

PD(7:

POR

PC(7:

PA(7:

PB(7:

SA9205

PA 0

DR-01268

ALE

INT

STB

RST

PC1

PC 5

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ABSOLUTE MAXIMUM RATINGS*

(All voltages are with respect to VSS)

Parameter

Symbol

Min

Max

Unit

Supply Voltage

-V

7,0

Voltage on any pin

-0.3

+0.3

Current at any pin

100

Storage Temperature

STG

-40

+125

�C

Operating Temperature

+70

�C

* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only. Functional operation of the device
at these or any other condition above those indicated in the operational sections of this
specification, is not implied. Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability.

FIGURE 4: BLOCK DIAGRAM FOR SA9205

Inter-

face

D R - 0 1 2 6 9

AD(7:0)

CON

PRTA

CON.

PRTBC

�
�

INT

RST

W R

ALE

STB

PORT

PC(7:0)

PA(7:0)

PB(7:0)

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ELECTRICAL CHARACTERISTICS

(All measurements with respect to VSS, at 25�C, unless otherwise specified)

Parameters

Symbol

Min

Typ Max

Unit

Condition

Supply Voltage

4.75

5.0 5.25

Static Current

DDS

�A

VDD = 5.0V
(See Note1)

Dynamic Current

DDD

VDD = 5.0V

Input High Voltage

2.0

VDD = 5.0V

Input Low Voltage

1.0

VDD = 5.0V

Output High Voltage

4.5

4.7

VDD = 5.0V

= 5mA

Output Low Voltage

0.25 0.5

VDD = 5.0V

= 5mA

Input Leakage Current

<1.0 3.0

�A

VDD = 5.0V

Tristate Leakage Current

<1.0 3.0

�A

VDD = 5.0V

Note 1:

All inputs tied to VDD or VSS with outputs not loaded.

Measurements made after RST applied.

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Pin

Type Designation

Description

18,52

VDD

+5V Supply Input

1,35

VSS

0V ground Reference

61..68

I/O

AD0..AD7

3-state address/data lines that interface with the CPU
lower 8-bit address/data bus. The 8-bit address is
latched into the SA9203 internal address latch on the
falling edge of ALE. The 8-bit data is respectively
written into and read out of the SA9203 on WR and RD
signals.

N/C

Not connected.

Active low input signal used to select the device.

ALE

This control signal latches the address on the AD0..7
lines on the falling edge of ALE.

Input low on this line enables the data bus buffers.

Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.

INT

If enabled via A.6, this output will be set (active edge
polarity programmed by D6 and output polarity
programmed via D7 of the Port B-F direction control
register) after data has been latched into PORT A.

RST

Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).

STB

Input data on PORT A pins will be latched when STB is
active and transparent otherwise (polarity programmed
by D5 of the Port B-F direction control register)

10..17

I/O

PA0..PA7

8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin. In addition,each pin of PORT
A selected as an input can be programmed to be
latched or transparent.

19..26

I/O

PB0..PB7

8 general purpose I/O pins comprising PORT B. All 8
pins are programmed to be either latched outputs or
transparent inputs.

27..34

I/O

PC0..PC7

Identical to PORT B

36..43

I/O

PD0..PD7

Identical to PORT B

44..51

I/O

PE0..PE7

Identical to PORT B

53..60

I/O

PF0..PF7

Identical to PORT B

PIN DESCRIPTION for SA9203

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Pin

Type Designation

Description

2,35

VDD

+5V Supply Input

1,23

VSS

0V ground Reference

40..44

I/O

AD0..AD7

N/C

Not connected.

Active low input signal used to select the device.

ALE

This control signal latches the address on the AD0..7
lines on the falling edge of ALE.

Input low on this line enables the data bus buffers.

Input low on this line causes the data on the address/
data bus to be written to the I/O ports and, control
registers.

INT

RST

Input low on this line resets the chip and all internal
registers and all ports to input mode (The register
contents after a reset pulse will be described later).

STB

Input data on PORT A pins will be latched when STB is
active and transparent otherwise (polarity programmed
by D5 of the Port B-F direction control register)

14..21

I/O

PA0..PA7

8 general purpose I/O pins comprising PORT A. This
port supports individual input or latched output
configuration of each pin . In addition,each pin of
PORT A selected as an input can be programmed to be
latched or transparent.

22,

I/O

PB0..PB7

8 general purpose I/O pins comprising PORT B. All 8

24.30

pins are programmed to be either latched outputs or
transparent inputs.

31..39

I/O

PC0..PC7

Identical to PORT B

PIN DESCRIPTION for SA9205

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FUNCTIONAL DESCRIPTION

The SA9203 contains the following:

�

Six 8-bit general purpose I/O ports programmable to be either byte or bit addressable.

�

Two control registers for configuring the device. These control registers can be read
back.

�

An internal address latch for accessing a multiplexed CPU address/data bus.

�

The SA9203 appears to the CPU as a peripheral device occupying 256 bytes of
memory space. Certain locations in the memory map are occupied by the six I/O
ports and two control registers.

The SA9203 supports two basic I/O port addressing modes, via; byte-addressing and
bit-addressing. Any of the six I/O ports can be configured as byte-addressable /or bit-
addressable. In bit-addressing, individual bits of any I/O port can be addressed
independently. In a bit- addressing CPU read operation, D0 contains valid data while
D1..D7 should be ignored. In a bit-addressing CPU write operation, D0 will be written
to the addressed output pin while D1..D7 will be ignored. The Address Memory map
is shown in Figure 5. The bit-addressing mode applies to both the I/O ports and the
control registers. The SA9205 is a three port device with operation is identical to the
SA9203.

FIGURE 5: Address Memory Map

CR2 CR1 CR0 BM2 MB1 BM0

Bit mode address 0

Bit mode address 1

Bit mode address 2

Control register address 0

Control register address 1

Control register address 2

0: Interupt function disabled
1: Interupt function enabled

0: Bit mode addressing enabled
1: Byte mode addressing enabled

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FIGURE 6: PORT A Direction Control Register Address.

FIGURE 7: PORT B..F Direction Control Register / Strobe Control Register
Address

FIGURE 8: PORT Addresses

PORT

PORT A

PORT B

PORT C

PORT D *

PORT E *

PORT F *

* - n/a for the SA9205

FIGURE 9: Port Pin Addresses (Bit Mode Only).

PORT PIN

PORT A-F.0

PORT A-F.1

PORT A-F.2

PORT A-F.3

PORT A-F.4

PORT A-F.5

PORT A-F.6

PORT A-F.7

Note : PORT A-C for SA9205

CONTROL REGISTERS

FIGURE 10: PORT A Direction Control Register

R/W

PA.7

PA.6

PA.5

PA.4

PA.3

PA.2

PA.1

PA.0

D = 1 Port A Pin configured as output
D = 0 Port A Pin configured as input.

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FIGURE 11: PORT B-F Direction Control / Strobe Control Register Address

R/W R/W R/W R/W R/W R/W R/W R/W
D7

DF* DE* DD* DC

0: PORT B Configured as input
1: PORT B Configured as output

0: PORT C Configured as input
1: PORT C Configured as output

0: PORT D Configured as input

1: PORT D Configured as output

0: PORT E Configured as input

1: PORT E Configured as output

0: PORT F Configured as input

1: PORT F Configured as output

0: PORT A data latched when
STB low and transparent when
STB high.

1 - Port A data latched when
STB high and transparent when
STB low.

0 - Interupt output (INT) set on
the rising edge of STB.

1 - Interupt output (INT) set on
the falling edge of STB.

0: Interupt output active High

1: Interupt output active low

* n/a for the SA9205

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INT
This active high output (default after reset) operates as follows:
When disabled (via A6), INT remains reset. On either the rising or trailing edge of STB
(programmable via D6 of Port B-F direction control register), INT is set. INT remains
set until Port A (or any bit of PORT A if in bit- addressing mode) is read by the
microprocessor at which point INT is reset, remaining so until the next active edge of
STB. (See figure 14 for timing diagram). The output polarity of INT is programmed via
D7 of the Port B- F dirction control register (See Figure 11).

RST
This active low reset signal resets the contents of all registers to zero. Sets all ports to
input mode and the bi-directional data/address bus to input. A valid RST signal is
specified as an active low pulse of 100ns minimum duration.

CS
The active low CS signal is internally latched by the trailing edge of ALE.

TIMING DIAGRAMS

FIGURE 12: �P Read Waveforms

RDE

DR-01270

ALE

AD -8/A

ADDRESS

RDF

t RD

t CC

DATA VALID

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FIGURE 16: �P Read Waveforms Latched Output

Table 1: AC Characteristics for �P Interface1 - TA = 0�C to 70�C, VDD = 5V 10%

Symbol Parameter

Min

Max

Units

Address to Latch Setup Time

Address Hold Time after Latch

Latch to READ/WRITE Control

Valid Data Out Delay from READ Control

Latch to Data Out Valid

Address Stable to Data Out Valid

100

Latch Enable Width

RDF

Data Bus Float after READ

READ/WRITE Control to Latch Enable

CLL

WRITE Control to Latch Enable

READ/WRITE Control Width

Data in to WRITE Setup Time

Data in Hold Time after WRITE

Recovery Time between READ/WRITE

RDE

Data Bus Enable from READ Control

FIGURE 15: I/O Port Waveforms Transparent Output

DATA BUS *

DR 01273

INPUT

DATA VALID

OUTPUT

DR-01274

DATA BUS *

DATA VALID

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Table 2: A.C. Characteristics for I/O Ports

Symbol Parameter

Min

Max

Units

Port Input Setup Time

Port Input Hold Time

Strobe Width

100

Strobe to INT Set

100

READ to INT Reset

100

PSS

Port Setup Time to Strobe

PHS

Port Hold Time After Strobe

120

WRITE to Port Output

Note 1: Timing parameters are preliminary and subject to change.

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South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888,

33 Eland Street,

Lynn East,

Koedoespoort Industrial Area,

0039

Pretoria,

Republic of South Africa,

Republic of South Africa

Tel:

012 333-6021

Tel:

Int +27 12 333-6021

Fax:

012 333-8071

Fax:

Int +27 12 333-8071

Disclaimer:

The information contained in this document is confidential and proprietary to South African Micro-

Electronic Systems (Pty) Ltd ("SAMES) and may not be copied or disclosed to a third party, in whole or in part,
without the express written consent of SAMES. The information contained herein is current as of the date of
publication; however, delivery of this document shall not under any circumstances create any implication that the
information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to
inform any recipient of this document of any changes in the information contained herein, and SAMES expressly
reserves the right to make changes in such information, without notification,even if such changes would render
information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any
circuit designed by reference to the information contained herein, will function without errors and as intended by
the designer.

Электронный компонент: SA9205