The ADC1256X is a CMOS 12bit analog-to-digital
converter (ADC).

It converts the analog input signal

into 12bit binary digital codes at a maximum
sampling rate of 20MHz.
The device is a monolithic ADC with an on-chip,
high-performance, sample-and-hold Amplifier (SHA)
and current reference.

The structure allows both

differential and single-ended input.

Resolution : 12bit

Maximum Conversion Rate : 20MHz

Package Type : 48TSSOP
Power Supply : 2.5V
Power Consumption : 115mW (typical)
Reference Voltage : 1.75V, 0.75V (dual reference)
Input Range : ±1V (differential)
Differential Linearity Error : ±1.0 LSB (Max)
Integral Linearity Error : ±3.0 LSB (Max)
Signal to Noise & Distortion Ratio : 62dB (Typ.)
Digital Output : CMOS Level
Operating Temperature Range : 0ºC

~ 70

ºC

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

High Definition TV (HDTV)
Video Applications
CCD Imaging (Copiers, Scanners, Cameras)
Medical Imaging
Digital Communications

TYPICAL APPLICATIONS

12BIT 20MSPS ADC

ADC1256X

SAMSUNG ELECTRONICS Co. LTD

Ver 1.1 (February. 2000)
No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this
datasheet is subject to change without any notice.

SHA

MDAC2
GAIN=8

MDAC3
GAIN=8

MDAC1

GAIN=8

FLASH

DIGITAL CORRECTION LOGIC

Common Mode
Level Generator

Clock

Generator

MAIN

BIAS

VDD25A1

VSS25A1

VBBA1

VDD25A2

VSS25A2

VBBA2

CML

SPEEDUP

ITEST

STBY

CKIN

AINT

AINC

REFTOP1

REFTOP

REFBOT

REFBOT1

DO[11:0]

[MSB:LSB]

SEC ASIC

ADC1256X

12BIT 20MSPS ADC

ANALOG

CORE PIN DESCRIPTION

NAME

I/O TYPE

I/O PAD

PIN DESCRIPTION

REFTOP1

piar50_abb

Reference Top Sense (1.75V)

REFTOP

pia_abb

Reference Top Force (1.75V)

REFBOT

pia_abb

Reference Bottom Force (0.75V)

REFBOT1

piar50_abb

Reference Bottom Sense (0.75V)

CML

pia_abb

Common Mode Level (Test Pin)

VDD25A1

vdd2t_abb

Analog Power (2.5V)

VBBA1

vbb_abb

Analog Sub Bias

VSS25A1

vss2t_abb

Analog Ground

AINT

piar50_abb

Analog Input +
(Input Range : 0.75V ~ 1.75V)

AINC

piar50_abb

Analog Input -
(Input Range : 0.75V ~ 1.75V)

SPEEDUP

picc_abb

VDD=Speed up, Normal (

20MHz)

GND=Speed down (

15MHz)

ITEST

pia_abb

open=use internal bias point

STBY

picc_abb

VDD=power saving (standby),
GND=normal

CKIN

picc_abb

Sampling Clock Input

D[11:0]

poa_abb

Digital Output

VBBA2

vbb_abb

Digital Sub Bias

VSS25A2

vss2t_abb

Digital GND

VDD25A2

vdd2t_abb

Digital Power (2.5V)

I/O TYPE ABBR.

AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output

AP : Analog Power
AG : Analog Ground
DP : Digital Power
DG : Digital Ground

AB : Analog Bidirection
DB : Digital Bidirection

adc1256x

AINC

ITEST STBY

CKIN

AINT

REFTOP1

REFTOP

REFBOT

REFBOT1

SPEEDUP

CML

VDD25A1

VSS25A1 VBBA1 VDD25A2

VSS25A2

VBBA2

DO[11:0]

[MSB:LSB]

2/12

SEC ASIC

ADC1256X

12BIT 20MSPS ADC

ANALOG

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Supply Voltage

VDD

3.3

Analog Input Voltage

AINT/AINC

VSS to VDD

Digital Input Voltage

CLK

VSS to VDD

Reference Voltage

REFTOP/REFBOT/

REFTOP1/REFBOT1

VSS to VDD

Storage Temperature Range

Tstg

-40 to 125

ºC

Operating Temperature Range

Topr

0 to 70

ºC

NOTES
1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to

ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is
applied with the other values kept within the following operating conditions and function operation under any of
these conditions is not implied.

2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5Kohm resistor (Human body model)

RECOMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDD25A1
VDD25A2
VDD25A3

2.3

2.5

2.7

Reference Input Voltage

REFTOP

REFBOT

1.75
0.75

Analog Input Voltage

AINT

AINC

(differential)

Operating Temperature

Toper

ºC

NOTES

It is strongly recommended that all the supply pins (VDD25A1, VDD25A2, VDD25A3) be powered from the same

source to avoid power latch-up.

3/12

SEC ASIC

ADC1256X

12BIT 20MSPS ADC

ANALOG

DC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Differential

Nonlinearity

DNL

0.8

LSB

REFTOP=1.75V

REFBOT=0.75V

Integral

Nonlinearity

INL

1.2

LSB

REFTOP=1.75V

REFBOT=0.75V

Offset

Voltage

OFF

REFTOP=1.75V

REFBOT=0.75V

(Converter Specifications : VDD25A1=VDD25A2=VDD25A3=2.5V, VSS25A1=VSS25A2=VSS25A3=0V,

Toper=25ºC, REFTOP=1.75V, REFBOT=0.75V unless otherwise specified)

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Maximum

Conversion Rate

MHz

AIN=AINT-AINC

Dynamic Supply

Current

IVDD

fc=20MHz

(without system load)

Signal-to-Noise &

Distortion Ratio

SNDR

AIN=1MHz

(Conversion Specifications : VDD25A1=VDD25A2=VDD25A3=2.5V, VSS25A1=VSS25A2=VSS25A3=0V,

Toper=25ºC, REFTOP=1.75V, REFBOT=0.75V unless otherwise specified)

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ADC1256X

12BIT 20MSPS ADC

ANALOG

FUNCTIONAL DESCRIPTION

1. The ADC1256X is a CMOS four step pipelined

Analog-to-Digital Converter. It contains four 4-bit
flash A/D Converters and three multiplying D/A
Conveters. The 4-bit flash ADC is composed of
2

-1 latching comparators, and multiplying DAC is

composed

2×(2

+1)

capacitors

and

two

fully-differential amplifiers.

2. The ADC1256X operates as follows. During the

first "L" cycle of external clock the analog input
data is sampled, and the input is held from the
rising edge of the external clock, which is fed to
the first 4-bit flash ADC, and the first multiplying
DAC. Multiplying DAC reconstructs a voltage
corresponding to the first 4-bit ADC's output, and
finally amplifies a residue voltage by 2

. The

second and third 4-bit flash ADC, and MDAC are
worked as same manner. Finally amplified residue
voltage at the third multiplying DAC is fed to the
last 4-bit flash ADC decides final 4-bit digital code.

3. ADC1256X has the error correction scheme, which

handles the output from mismatch in the first,
second, third and fourth flash ADC.

MAIN BLOCK DESCRIPTION

1. SHA

SHA (Sample-and-Hold Amplifier) is the circuit that

samples the analog input signal and hold that value
until next sample-time. It is good as small as its
different value between analog input signal and
output signal. SHA amp gain is higher than 70dB
at 20MHz conversion rate, its settling-time must be
shorten than 18ns with less than 1/2 LSB error
voltage at 12bit resolution. This SHA is consist of
fully differential op amp, switching tr. and sampling
capacitor. The sampling clock is non-overlapping
clock (Q1, Q2) and sampling capacitor value is
about 3.0pF. SHA uses independent bias to protect
interruption of any other circuit. SHA amp is
designed that open-loop dc gain is higher than
70dB, phase margin is higher than 60 degrees. Its

input block is designed to be the rail-to-rail
architecture using complementary different pair.

2. FLASH

The 4-bit flash converters compare analog signal

(TAH output) with reference voltage, and that
results transfer to MDAC and digital correction
logic

block.

realized

fully

differential

comparators

15EA.

Considering

self-offset,

dynamic feed through error, it should distinguish
40mV at least. First, the comparators charge the
reference voltage at the sampling capacitors before
transferred SHA output.That operation is performed
on the phase of Q2, and discharging on the phase
of Q1. That is, the comparators compare relative
different values dual input voltage with dual
reference voltage. Its output during Q1 operation is
stored at the pre-latch block by Q1P.

3. MDAC

MDAC is the most important block at this ADC

and it decides the characteristics. MDAC is consist
of two stage op amp, selection logic and capacitor
array (c_array). c_array's compositions are the
capacitors to charge the analog input and and the
reference voltage, switches to control the path.
Selection logic controls the c_array internal switches
. If Q1 is high, selection's output are all low, the
switches of tsw1 are off, the switches of tsw2 are
all on. Therefore the capacitors of c_array can
charge analog input values held at SHA.

7/12

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ADC1256X

12BIT 20MSPS ADC

ANALOG

PACKAGE CONFIGURATION

NOTES
1. NC denotes "No Connection".

Digital II

Analog

ADC1256X

REFTOP1

REFTOP

REFBOT

REFBOT1

CML

VDD25A1

VBBA1

VSS25A1

AINT

AINC

SPEEDUP

ITEST

STBY

VDD25A3

VSS25A3

CKIN

TEST1

TEST2

VDD25A2

VSS25A2

VBBA2

NC
NC

DO[11]
DO[10]

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]
DO[1]

DO[0]

TRIST

50ohm

10u

0.1u

10u

0.1u

10u

0.1u

10u

0.1u

10u

0.1u

10u

Digital I

9/12

SEC ASIC

ADC1256X

12BIT 20MSPS ADC

ANALOG

PACKAGE PIN DESCRIPTION

NOTES
1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively

No.

NAME

I/O

TYPE

PIN DESCRIPTION

CONFIGURATION

REFTOP1

Reference Top Sence (1.75V)

REFTOP

Reference Top Force (1.75V)

REFBOT

Reference bottom Force (0.75V)

REFBOT1

Reference bottom Sense (0.75V)

CML

Common Mode Level (Test Pin)

6, 7

VDD25A1

Analog Power (2.5V)

VBBA1

Analog Sub Bias

9, 10

VSS25A1

Analog Ground

AINT

Analog Input +

AINC

Analog Input -

SPEEDUP

VDD=Normal (

20MHz)

GND=Speed Down (

15MHz)

ITEST

open=use internal bias circuit

STBY

VDD=Power saving (Standby),
GND=Normal

VDD25A3

PAD Power (2.5V)

VSS25A3

PAD Ground

CKIN

Sampling Clock Input

TEST1

Monitoring (TEST) Cell Pin1,
GND=Normal

TEST2

Monitoring (TEST) Cell Pin2,
GND=Normal

TRIST

Tristate Buffer Input
VDD=High Impedance,
GND=Normal

DO[0]

Digital Output (LSB)

28~37

DO[1:10]

Digital Output

DO[11]

Digital Output (MSB)

VBBA2

Digital Sub Bias

45, 46 VSS25A2

Digital GND

47, 48 VDD25A2

Digital Power (2.5V)

REFTOP

VBBA1

TEST1

TEST2

ADC1256X

REFTOP1

REFBOT

CML

VDD25A1

VSS25A1

AINT

AINC

SPEEDUP

ITEST

STBY

VDD25A3

VSS25A3

CKIN

VDD25A2

VSS25A2

VBBA2

DO[11]

DO[10]

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

TRIST

REFBOT1

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ADC1256X

12BIT 20MSPS ADC

ANALOG

USER GUIDE

1. Input Range

- If you want to using the single-ended input, you should use he input range as below.

AINT : 0.25V ~ 2.25V,
AINC : 1.25V.

- If you want to using the differential input, you should use the input range as below.

AINT : 0.75V ~ 1.25V,
AINC : 0.75V ~ 1.25V.

AIN : AINT-AINC

2. Speed Up

The initial target speed of ADC1256X is 20MHz.

If you want speed down (about 15MHz), you should connect the SPEEDUP port to 'LOW'.

And it can save the total power consumption about 10 ~ 15%.

3. Power Consumption Optimization

Yon can optimize the power consumption, as control the ITEST voltage level precisely .

11/12

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ADC1256X

12BIT 20MSPS ADC

ANALOG

FEEDBACK REQUEST

ADC Specification

Parameter

Min

Typ

Max

Unit

Remarks

Supply voltage

Reference Input voltage

Analog Input voltage

Vpp

Operating temperature

ºC

Integral non-linearity error

LSB

Differential non-linearity error

LSB

Offset voltage error

(Bottom)

Offset voltage error

(Top)

Maximum conversion rate

MSPS

Dynamic supply current

Power dissipation

Signal-to-noise ratio

Digital output format

(Provide detailed description

& timing diagram)

- What do you want to choose as power supply voltages?

- What resolution do you need for ADC?

- How about conversion speed(data in

data out)?

- How many cycles do exist during the latency of ADC (pipelined delay)?
- What's the input range? And then what do you need between single input and differential input?

- Could you explain external/internal pin configurations as required?

Specially requested function list :

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