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BW0405XB

GENERAL DESCRIPTION

This product is SD Digital-To-Analog Converter for digital audio System (CDP). The product contains Serial-to-
Parallel Converter and Compensation Filter, Digital Volume Attenuator by the MICOM Interface, De-Emphasis
Filter, FIR filter, Sinc Filter, digital sigma-delta modulator, analog postfilter, AIF (Anti-Image-Filter). The normal
input and output channels provides 95dB SNR (Signal to Noise Ratio) over in band (20kHz).

The product employs the 1bit 4th-order sigma-delta architecture with 16bit resolution, over sampling of 64X. And
analog postfilter with low clock sensitivity and linear phase, filters the shaping-nosie and outputs analog voltage
with high resolution. An on-chip reference voltage is included to allow single supply operations.

FEATURES

-- 16bit SD Digital-To-Analog Converter

-- On-Chip Analog Postfilter

-- Filtered Line-Level Outputs, Linear Phase Filtering

-- On-Chip Voltage Reference

-- 90dB SNR

-- Sampling Rate 32KHz/44.1kHz/48KHz

-- Input Rate 1Fs or 2Fs by Normal Mode/Double Mode Selection

-- Zero Input Detection Mute

-- On-Chip Compensation Filter

-- Input Volume Attenuator by the MICOM Interface

-- On-Chip De-Emphasis Filter

(32KHz/44.1KHz/48KHz)

-- On-Chip 4 times oversampling Digital Filter

-- Low Clock Jitter Sensitivity

-- Single 3.3V ~ 2.5V Power Supply

APPLICATIONS

CD Player, Portable CD Player, CD-ROM, Video-CD, Mini-Disk, DVD etc

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FUNCTIONAL BLOCK DIAGRAM

DAC

Analog

Postfilter

Sinc Filter

Sigma-Delta

Modulator

Compensation

Filter

De-emphsis

FIR Filter

Anti-Imaging

Filter

Timing Generation

Voltage

Reference

S/P

Converter

Attenuator

SDATA
BCK
LRCK
ZDENL

AOUTL

VREF

VHALF

IREF

AOUTR

MICOM Interface

VDDD VSSD

VDDA VSSA

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EMBEDDED CORE BLOCK DIAGRAM

MSCK
BCK
LRCK
SDATA

AOUTL

VHALF

AOUTR

ZDENL

DEEM
DN
MUTEL
PDL
RSTB

Audio Processor

(DSP)

bw0405xb

SDIAG

SERRORB

OFS64

ODSL

ODSR

BISTONP
TSEL
IFS64
IADSL
IADSR

MUX_SEL

External

Inputs

These are test pins for internal blocks of the core.
So you don't need the internal test mode.
Make the test control pins disable ('L') state and
Output and bidirectional pins leave foalting.

MCLK

MLD

MDATA

FSEL<1:0>

IDNUM<7:0>

IREF

VSSD

External

VREF

EMBEDDED CORE USER GUIDE

-- Digital serial data input and clock input refer to digital input format.

-- Digital control pins inform refer to pin description.

-- Micom I/F pin inform refer to micom interface. IDNUM<7:0> are ID number setting pins for micom Interface.

-- External application of analog output pins refer to application circuit.

-- If you want to test only embedded analog core block (Sigma-Delta DAC), you can do it just adding the 4 pins to

supply digital serial input data (LRCK, BCK, SDATA, MSCK) and MUX block.

-- Analog power (VDDA,VSSA) and digital power (VDDD, VSSD) should be seperated.

-- VBB pin should be connected to analog ground.

-- Two pads should be dedicated to analog power (VDDA, VSSA)

-- If you need not use test mode for the testability of internal core block, you make internal core block test pins

disable state. (Test Input pins are 'L' state and Test output, bidirection pins leave floating)

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CORE PIN DESCRIPTION

Symbol

I/O

Type

I/O

Pad

Description

Power

Supply

Pins

VDDD

vdd3t_bb

Digital

Supply

VSSD

vsst_bb

Digital

Ground

VDDA

vdd3t_bb

Analog

Supply

VSSA

vsst_bb

Analog

Ground

Digital

Pins

MSCK

picc_bb

Master

Clock

Input.

384Fs

Clock

BCK

picc_bb

Bit

Clock

Input.

(32Fs

64Fs)

LRCK

picc_bb

Sample

Rate

Clock

Input.

(Fs

2Fs)

SDATA

picc_bb

Serial

Digital

Input

MCLK

picc_bb

Micom

Interface

Clock

Input

MLD

picc_bb

Micom

Interface

Command

load

Input

(When

low,load)

MDATA

picc_bb

Micom

Interface

Command

Data

Input

DEEM

picc_bb

De-Emphasis

On/Off.

"H"

enabled.

"L"

disabled.

picc_bb

Input

Rate

Select.

High

Double(2Fs)

Mode,

Low

Normal(Fs)

Mode.

MUTEL

picc_bb

Analog

Output

Mute.

"L"

enabled

ZDENL

picc_bb

Zero Input Detection Enable. "L" is enabled. "H" is disabled

FSEL<1:0>

picc_bb

De-Emphasis Sampling Frequency Mode Select
FSEL<1:0> Sampling Frequency
H H 48KHz
H L 32KHz
L H 48KHz
L L 44.1KHz

IDNUM<7:0>

picc_bb

Micom Interface ID Number setting Input

PDL

picc_bb

Power

Down.

"L"

enabled

RSTB

picc_bb

Reset

Input.

"L"

Enabled

Analog

Pins

AOUTL

poa_bb

Analog

Output

for

L-CH

AOUTR

poa_bb

Analog

Output

for

R-CH

VHALF

poar50_bb Reference

Voltage

Output

for

Bypass

VREF

poar50_bb Reference Voltage Output for Bypass

Core

Internal

Block

Test

Pins

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CORE PIN DESCRIPTION (Continued)

Symbol

I/O

Type

I/O

Pad

Description

BISTONP

picc_bb

Memory

Bist

Test

Mode.

"H"

enabled

TSEL

picc_bb

Test

for

Analog

Postfilter

Input

Selection

IFS64

picc_bb

64X

Sampling

Clock

Input

for

Analog

Postfilter

(When

TSEL=H)

IADSL

picc_bb

Inputs

for

Analog

Postfilter

L-CH

(When

TSEL=H)

IADSR

picc_bb

Inputs

for

Analog

Postfilter

R-CH

(When

TSEL=H)

SDIAG

pot2_bb

Test

Output

for

embeded

memory

BIST

(BIST_ON="H")

SERRORB

pot2_bb

Test

Output

for

Embeded

memory

BIST

(BIST_ON="H")

OFS64

pot2_bb

64X

Sampling

Clock

output

for

Digital

sigma-delta

Modulator

ODSL

pot2_bb

L-CH

Output

for

Digital

sigma-delta

Modulator.

ODSR

pot2_bb

R-CH

Output

for

Digital

sigma-delta

Modulator.

IREF

poa_bb

Test

for

Analog

Supply

Current

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

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CORE CONFIGURTION

bw0405xb

Used Power:

(VDDD VSSD VDDA VSSA)

MSCK
BCK

LRCK
SDATA

ZDENL

MCLK

MLD
MDATA

FSEL<1:0>
IDNUM<7:0>

DEEM

DN
MUTEL

PDL
RSTB

BISTONP

TSEL

IFS64
IADSL

IADSR

AOUTL
AOUTR

VHALF

VREF

IREF

SDIAG
SERRORB

OFS64
ODSL

ODSR

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Values

Unit

Supply Voltage

VDDD,VDDA

-0.15 ~ 3.8

Voltage on Any Digital Pin

Vin

VSSD-0.15 to VDDD+0.15

Storage Temperature Range

Tstg

-45 to +125

RECOMMENDED OPERATING CONDITIONS

Charateristics

SYMBOL

MIN

TYP

MAX

UNITS

Supply Voltage

VDDD
VDDA

2.3

2.5

3.6

Operating Temp.

Topr

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ELECTRICAL CHARACTERISTICS

(VDDD,VDDA=2.5V, Temp=25

C, Fs=44.1kHz, Signal Frequency=20-20kHz, Cload of AoutL, AoutR=10pF)

Parameter

Min

Typ

Max

Units

Resolution

bits

SNR

<1>

THD

<2>

0.005

0.01

SND(THD+Noise)

<3>

Dynamic Range

<4>

Reference Voltage Ouput

0.5 x VDDA

Frequency Responce

0.1

0.5

Analog Output

Voltage Range

0.75 x VDDA

Vpp

Load Impedance

10k

Digital Filter

Pass Band Ripple

0.0072

Stop Band Attenuation

62.7

Pass Band

0.45

Power Supply

Analog Current

Digital Current

Power Dissipation

17.5

22.5

Power Down Current

0.1

NOTES:
1.

1kHz 0dB Sinewave Input, EIAJ

1kHz -3dB Sinewave Input

1kHz 0dB Sinewave Input, (Not EIAJ)

1kHz -60dB Sinewve Input, and then measured data + 60dB

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AC TIMING CHARACTERISTICS

(VDDD=2.5V, VSSD=0V, Temp=25

Characteristics

Symbol

Min

Typ

Max

Unit

MSCK Frequency

Fmck

16.9344

MHz

BCK Frequency (Normal/Doube Mode)

Fbck

1.4112 / 2.8224

(Normal / Double)

MHz

MSCK Rising and LRCK Edge Dealay

Tmld

MSCK Risng and LRCK Edge Setup Time

Tmlst

BCK Rising and LRCK Edge Dealay

Tbld

BCK Risng and LRCK Edge Setup Time

Tblst

SDATA and BCK Rising Setup Time

Tsbst

BCK Ring and SDATA Hold Time

Tbsht

1/Fbck

0.5 VDDD

MSCK

BCK

0.5 VDDD

1/Fmck

LRCK

0.5 VDDD

Tmld

Tmlst

MSCK

SDATA

0.5 VDDD

LRCK

0.5 VDDD

Tbld

Tblst

Tsbst

Tbsht

BCK

Figure 1. Timing Chart

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CLOCK INPUT AND SERIAL INPUT DATA INFORM (FS=44.1KHZ)

DN is normal and double mode selection control pin. Refer to the following table for clock input inform.

Table 1. Input Clock Informs

Normal

Mode

(DN='Low')

Double

Mode

(DN='High')

LRCK

44.1kHz

88.2kHz

MSCK

16.9344MHz

BCK

1.4112MHz

2.8224MHz

Serial input data (SDATA) is MSB fisrt at falling edge triggered of BCK.

LSB

LRCK

BCK

SDATA

R-CH DATA

L-CH DATA

MSB

LSB+1

LSB+2

MSB-1 MSB-2

...

LSB

MSB

LSB+1

LSB+2

MSB-1 MSB-2

...

Figure 2. Digital Input Data Format

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MICOM INTERFACE (DIGITAL ATTENUATION)

This

product

can

the

function

digital

attenuation

whenever

receives

thd

MDATA,

MLD,

MCLK

signals

form

the

MICOM.

When

the

14-bit

serial

data

applied

the

MDATA,

MCLK,

MLD

the

form

Fig3,

according

the

data

digital

attenuation

accomplished.

The

lower

eight

LSBs

should

5D(LSB

First

Format-Hex)

and

according

the

upper

bits(LSB

First

Format-Bin)

the

attenuation

level

can

adjusted.

(see

Table1)

When

RSTB

low

state

the

latch

circuitry

for

setting

the

attenuation

level

becomes

reset

and

the

attenuation

level

0dB.

this

instance,

because

the

digital

filter

circuit

gets

stop

operation

the

act

attenuation

impossible.

addition,

whenever

MDATA

not

carried,

MCLK

must

'HIGH'

state.

case

attenuation

fuction

needed,

MDATA

should

'L',

MCLK

and

MLD

should

'H.

Don't

Care

MCLK

MDATA

MLD

Don't

Care

Over 550ns needed

MSB

LSB

MSB

LSB

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

Figure 3. MICOM Interface Timing Chart

FSEL<1:0> is de-emphasis sampling frequency mode selection control pin. Refer to the following table for function
inform.

Table 2. De-Emphasis Sampling Frequency Mode Selection

FSEL<1>¡¬ FSEL<0>

"High"

"Low"

"High"

48kHz

32kHz

"Low"

48KHz

44.1KHz

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Table 3. Digital Attenuation Level

MDATA

Attenuation

MDATA

Attenuation

MSB ~ LSB MSB ~ LSB

ID7 ~ ID0 M5 M4 M3 M2 M1 M0

Level (dB)

MSB ~ LSB MSB ~ LSB

ID7 ~ ID0 M5 M4 M3 M2 M1 M0

Level (dB)

IDNUM<7:0> 0 0 0 0 0 0
IDNUM<7:0> 0 0 0 0 0 1
IDNUM<7:0> 0 0 0 0 1 0
IDNUM<7:0> 0 0 0 0 1 1

-0.28
-0.42
-0.56

IDNUN<7:0> 1 0 0 0 0 0
IDNUN<7:0> 1 0 0 0 0 1
IDNUN<7:0> 1 0 0 0 1 0
IDNUN<7:0> 1 0 0 0 1 1

-6.30
-6.58
-6.88
-7.18

IDNUN<7:0> 0 0 0 1 0 0
IDNUN<7:0> 0 0 0 1 0 1
IDNUN<7:0> 0 0 0 1 1 0
IDNUN<7:0> 0 0 0 1 1 1

-0.71
-0.86
-1.01
-1.16

IDNUN<7:0> 1 0 0 1 0 0
IDNUN<7:0> 1 0 0 1 0 1
IDNUN<7:0> 1 0 0 1 1 0
IDNUN<7:0> 1 0 0 1 1 1

-7.50
-7.82
-8.16
-8.52

IDNUN<7:0> 0 0 1 0 0 0
IDNUN<7:0> 0 0 1 0 0 1
IDNUN<7:0> 0 0 1 0 1 0
IDNUN<7:0> 0 0 1 0 1 1

-1.32
-1.48
-1.64
-1.80

IDNUN<7:0> 1 0 1 0 0 0
IDNUN<7:0> 1 0 1 0 0 1
IDNUN<7:0> 1 0 1 0 1 0
IDNUN<7:0> 1 0 1 0 1 1

-8.89
-9.28
-9.68

-10.10

IDNUN<7:0> 0 0 1 1 0 0
IDNUN<7:0> 0 0 1 1 0 1
IDNUN<7:0> 0 0 1 1 1 0
IDNUN<7:0> 0 0 1 1 1 1

-1.97
-2.14
-2.32
-2.50

IDNUN<7:0> 1 0 1 1 0 0
IDNUN<7:0> 1 0 1 1 0 1
IDNUN<7:0> 1 0 1 1 1 0
IDNUN<7:0> 1 0 1 1 1 1

-10.55
-11.02
-11.51
-12.04

IDNUN<7:0> 0 1 0 0 0 0
IDNUN<7:0> 0 1 0 0 0 1
IDNUN<7:0> 0 1 0 0 1 0
IDNUN<7:0> 0 1 0 0 1 1

-2.68
-2.87
-3.06
-3.25

IDNUN<7:0> 1 1 0 0 0 0
IDNUN<7:0> 1 1 0 0 0 1
IDNUN<7:0> 1 1 0 0 1 0
IDNUN<7:0> 1 1 0 0 1 1

-12.60
-13.20
-13.84
-14.54

IDNUN<7:0> 0 1 0 1 0 0
IDNUN<7:0> 0 1 0 1 0 1
IDNUN<7:0> 0 1 0 1 1 0
IDNUN<7:0> 0 1 0 1 1 1

-3.45
-3.66
-3.87
-4.08

IDNUN<7:0> 1 1 0 1 0 0
IDNUN<7:0> 1 1 0 1 0 1
IDNUN<7:0> 1 1 0 1 1 0
IDNUN<7:0> 1 1 0 1 1 1

-15.30
-16.12
-17.04
-18.06

IDNUN<7:0> 0 1 1 0 0 0
IDNUN<7:0> 0 1 1 0 0 1
IDNUN<7:0> 0 1 1 0 1 0
IDNUN<7:0> 0 1 1 0 1 1

-4.30
-4.53
-4.76
-5.00

IDNUN<7:0> 1 1 1 0 0 0
IDNUN<7:0> 1 1 1 0 0 1
IDNUN<7:0> 1 1 1 0 1 0
IDNUN<7:0> 1 1 1 0 1 1

-19.22
-20.56
-22.14
-24.08

IDNUN<7:0> 0 1 1 1 0 0
IDNUN<7:0> 0 1 1 1 0 1
IDNUN<7:0> 0 1 1 1 1 0
IDNUN<7:0> 0 1 1 1 1 1

-5.24
-5.49
-5.75
-6.02

IDNUN<7:0> 1 1 1 1 0 0
IDNUN<7:0> 1 1 1 1 0 1
IDNUN<7:0> 1 1 1 1 1 0
IDNUN<7:0> 1 1 1 1 1 1

-26.58
-30.10
-36.12

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FUNCTIONAL DESCRIPTION

Compensation Filter

De-emphasis/

FIR Filter

Sinc Filter

Modulator

SC-Postfilter

Anti-Image

Filter

SDATA

BCK

LRCK

ZDENL

AoutL

4Fs/8Fs

16bits

64Fs

1bit

DEEM

FSEL<1:0>

IDNUM<7:0>

1Fs/2Fs

16bits

S/P Converter

Attenuator

MCLK

MDATA

MLD

AoutR

MUTEL

Figure 4. Funtional Block Diagram

Fig4 is the 1bit 4th order sigma-delta DAC block daigram. S/P Converter converts serial 16bit input data to parallel
16bit data. Digital input data is attenuated by MICOM interface pin control. Compensation Filter compensates gain
droop in Passband by Sinc Filter and Sigma-Dellta Modulator Signal Transfer Function. De-emphasis Block de-
emphasizes pre-emphasised input data to emphssize high frequency in audible band. FIR Filter perfroms 4X
interpolation. And it outputs 4Fs(DN='Low') rate data or 8Fs(DN='High') rate data by variabled input data rate. It
also removes the images of the input signal that are present at multiples of the input sample frequency. And Sinc
filter makes the constant 64Fs rate data by 16 times or 8 times upsampling FIR Filter output data according to
DN(Double/Normal Mode) Pin Selection. This operation intorduces a sinc function responce on the resulting
frequency spectrum, which greatly attenuates the energy of images at the multifules of 4Fs(or 8Fs).

Digital sigma-delta modulator of bit-stream type has the IFL (Inverse-Follower-Leader) topology, and it performs a
noise-shaping function. The modulator shapes the quantization noise by suppressing its in-band component and
pushes the noise energy of outside the band-of-interest without deteriorating the audio input signal. The 64 times
oversampled 1-bit PDM outputs from the modulator drives a analog postfilter.

The analog postfilter comprises SC-postfilter, anti-imaging filter. The SC-postfilter removes the quantization noise
shaped to out-of-band by digital sigma-delta modulator. This analog filter has the good clock jitter characteristc and
very linear characteristic. And following the CTF(continuous time filter) removes the sampling images and makes
the high resolution analog output.

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Analog pins and digital pins must be seperated, Analog pins should be located on the analog ground plane and
digital pins should be located on the digital ground plane. Analog ground and digital ground connection is
recommended to only one path through ferrite bead like Fig5. Supply bypass capacitors should be located as close
as possible to chip. Small bypass capacitor (0.1uF) should be positioned first to chip than large bypass capacitor
(10uF).

Reference (VHALF, VREF) bypass capacitors (Fig6) should be located as close as possible to chip.

L-CH Output

1uF

100k

AOUTL

R-CH Output

1uF

100k

AOUTR

Figure 7. Ananlog output application

FIg7 is simple high pass filter circuit for analog output. It performs ac-coupling for analog output signal from analog
common level to analog ground. Recommended component values are 1uF and 100k

User Guide

-- This analog Core Verilog behavioral-modeling will be supplied.

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FEEDBACK REQUEST

Sigma-Delta

DAC

Specification

We appreciate your interest in our products. If you have further questions, please specify in the attached form.
Thank you very much.

Parameter

Min

Typ

Max

Unit

Remarks

supply voltage

Max master clock frequency

Operating temperature

Sampling Frequency

Dynamic range

Total harmonic distortion

Signal-to-noise ratio

Input format resolution
(Serial/Parallel interface)

Bit

Channel

Mono Stereo

Power dissipation

Full scale output voltage range

Vpp

Group delay

sec

Phase linearity deviation for
passband region

(Deg)

Peak-to-peak frequency
response ripple for passband
region

-- Could you explain external/internal pin configurations as required?

-- Specially requested function list:

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