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BW1009L

GENERAL DESCRIPTION

The BW1009L is a CMOS 12-bit analog-to-digital converter (ADC). It converts the analog input signal into 12-bit
binary digital codes at a maximum sampling rate of 20MHz.

The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current
reference. The structure allows both differential and single-ended input.

TYPICAL APPLICATIONS

-- High Definition TV (HDTV)

-- Video Applications

-- CCD Imaging (Copiers, Scanners, Cameras)

-- MedicalImaging

-- Digital Communications

FEATURES

-- Resolution: 12-bit

-- Maximum Conversion Rate: 20MHz

-- Package Type: 48TSSOP

-- Power Supply: 3.3V

-- Power Consumption: 150mW (typical)

-- Reference Voltage: 2V, 1V (dual reference)
-- Input Range: 0.5V - 2.5V (2.0V

P-P

)

-- Differential Linearity Error:

1.0 LSB

-- Integral Linearity Error:

2.0 LSB

-- Signal to Noise & Distortion Ratio: 62dB

-- Digital Output: CMOS Level

-- Operating Temperature Range: 0

C - 70

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BW1009L

CORE PIN DESCRIPTION

Name

I/O Type

I/O PAD

Pin Description

REFTOP1

piar50_bb

Reference Top Sense (2.0V)

REFTOP

pia_bb

Reference Top Force (2.0V)

REFBOT

pia_bb

Reference Bottom Force (1.0V)

REFBOT1

piar50_bb

Reference Bottom Sense (1.0V)

VDDA

vdda

Analog Power (3.3V)

VBBA

vbba

Analog Sub Bias

VSSA

vssa

Analog Ground

AINT

piar50_bb

Analog Input +
(Input Range: 1.0V - 2.0V)

AINC

piar50_bb

Analog Input
(Input Range: 1.0V - 2.0V)

SPEEDUP

picc_bb

VDD=Speed up, Normal (

20MHz)

GND=Speed down (

15MHz)

STBY

picc_bb

VDD=power saving (standby),
GND=normal

CKIN

picc_bb

Sampling Clock Input

D[11:0]

pot4_bb

Digital Output

VBBD

vbba

Digital Sub Bias

VSSD

vssd

Digital GND

VDDD

vddd

Digital Power (3.3V)

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

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BW1009L

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Supply Voltage

VDD

4.5

Analog Input Voltage

AINT/AINC

VSS to VDD

Digital Input Voltage

CKIN

VSS to VDD

Reference Voltage

REFTOP/REFBOT/

REFTOP1/REFBOT1

VSS to VDD

Storage Temperature Range

Tstg

-45 to 150

Operating Temperature Range

Topr

0 to 70

NOTES
1.

Absolute

maximum

rating

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDDD
VDDA
VDDR

3.15

3.3

3.45

Reference Input Voltage

REFTOP
REFBOT

2.0
1.0

Analog Input Voltage

AINT

AINC

0.5

1.5

2.5

Operating Temperature

Toper

NOTE: It

strongly recommended that all the supply pins (VDDA, VDDD, VDDR) be powered from the same source to

avoid power latch-up.

BW1009L

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DC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Differential

Nonlinearity

DNL

0.8

LSB

REFTOP=2V
REFBOT=1V

Integral

Nonlinearity

INL

1.2

2.5

LSB

REFTOP=2V
REFBOT=1V

Offset

Voltage

OFF

LSB

REFTOP=2V
REFBOT=1V

NOTE: Converter Specifications: VDDA=VDDD=VDDR=3.3V, VSSA=VSSD=VSSR=0V,

Toper=25

C, REFTOP=2V, REFBOT=1V unless otherwise specified

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Maximum

Conversion Rate

MHz

AIN=AINT-AINC

Dynamic Supply

Current

IVDD

fc=20MHz

(without system load)

Total Harmonic

Distortion

THD

-68

-62

AIN=1MHz

Signal-to-Noise &

Distortion Ratio

SNDR

AIN=1MHz

NOTE: Converter Specifications: VDDA=VDDD=VDDR=3.3V, VSSA=VSSD=VSSR=0V,

Toper=25

C, REFTOP=2V, REFBOT=1V unless otherwise specified

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BW1009L

I/O CHART

Index

AINT Input (V)

AINC Input (V)

Digital Output

0.5000 ~ 0.5005

1.5

0000 0000 0000

1LSB=0.488mV

0.5005 ~ 0.5010

1.5

0000 0000 0001

REFTOP=2.0V

0.5010 ~ 0.5015

1.5

0000 0000 0010

REFBOT=1.0V

2047

1.4995 ~ 1.5000

1.5

0111 1111 1111

2048

1.5000 ~ 1.5005

1.5

1000 0000 0000

2049

1.5005 ~ 1.5010

1.5

1000 0000 0001

4093

2.4985 ~ 2.4990

1.5

1111 1111 1101

4094

2.4990 ~ 2.4995

1.5

1111 1111 1110

4095

2.4995 ~ 2.5000

1.5

1111 1111 1111

TIMING DIAGRAM

DO[11:0]

CKIN

AINT

Input Sampling Period

BW1009L

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CORE EVALUATION GUIDE

1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP

back-end circuit.

2. The reference voltages may be biased internally through resistor divider.

BW1009L

REFBOT1

REFBOT

REFTOP

REFTOP1

AINC

AINT

CKIN

SPE

EDUP

STB

DO[11:0]

Digital Mux

HOST

DSP

CORE

Bidrectional

PAD

(ADC Function Test &

Externally Forced Digital Input)

D[11:0]

VBB

VSS

VBB

VSS

VDD

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BW1009L

PACKAGE CONFIGURATION

REFTOP1

REFTOP

REFBOT

REFBOT1

CML

VDDA

VBBA

VSSA

AINT

AINC

SPEEDUP

ITEST

STBY

VDDR

VSSR

CKIN

TEST1

TEST2

VDDD

VSSD

VBBD

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

0.1u

TRIST

DO[11]

DO[10]

10u

0.1u

10u

0.1u

10u

0.1u

10u

0.1u

10u

BW1009L

Digital I

Analog

Digital II

0.1u

10u

NOTE: NC denotes "No Connection".

BW1009L

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PACKAGE PIN DESCRIPTION

Number

Name

I/O Type

Pin Description

REFTOP1

Reference Top Sense (2.0V)

REFTOP

Reference Top Force (2.0V)

REFBOT

Reference bottom Force (1.0V)

REFBOT1

Reference bottom Sense (1.0V)

CML

Internal Bias Point

6, 7

VDDA

Analog Power (3.3V)

VBBA

Analog Sub Bias

9, 10

VSSA

Analog Ground

AINT

Analog Input +

AINC

Analog Input

SPEEDUP

VDD=Normal (

20MHz)

GND=Speed Down (

15MHz)

ITEST

open=use internal bias circuit

STBY

VDD=Power saving (Standby),
GND=Normal

VDDR

PAD Power (3.3V)

VSSR

PAD Ground

CKIN

Sampling Clock Input

TEST1

Monitoring (TEST) Cell Pin1,
GND=Normal

TEST2

Monitoring (TEST) Cell Pin2,
GND=Normal

TRIST

Tristate Buffer Input
VDD=High Impedance,
GND=Normal

DO[0]

Digital Output (LSB)

28~37

DO[1:10]

Digital Output

DO[11]

Digital Output (MSB)

VBBD

Digital Sub Bias

45, 46

VSSD

Digital GND

47, 48

VDDD

Digital Power (3.3V)

NOTE: I/O

TYPE

and

denote

PAD

Power

and

PAD

Ground

respectively.

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BW1009L

PACKAGE PIN DESCRIPTION (Continued)

Configuration

REFTOP1

REFTOP

REFBOT

REFBOT1

CML

VDDA

VBBA

VSSA

AINT

AINC

SPEEDUP

ITEST

STBY

VDDR

VSSR

CKIN

TEST1

TEST2

VDDD

VSSD

VBBD

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

TRIST

DO[11]

DO[10]

BW1009L

BW1009L

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USER GUIDE

1. Input Range

-- If you want to use the single-ended input, you should use the input range as below.

AINT: 0.5V ~ 2.5V,

AINC: 1.5V.

-- If you want to use the differential input, you should use the input range as below.

AINT: 1.0V ~ 2.0V,
AINC: 1.0V ~ 2.0V.
AIN: AINT - AINC

2. Speed Up

The initial target speed of BW1009L is 20MHz. If you want speed down (about 15MHz), you should connect
the SPEEDUP port to 'LOW'. And it can save the total power consumption about 10 ~ 15%.

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BW1009L

PHANTOM CELL INFORMATION

BW1009L

VDD

REF

OT1

REF

OP1

REF

VDD

VSS

VBB

VSS

VDD

VBBA
VSSA

AINC

AINT

SPEEDUP

STBY

CKIN

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

DOU

]

[10]

[11]

BW1009L

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PHANTOM CELL INFORMATION (Continued)

Pin Name

Pin Usage

Pin Layout Guide

VDDA

External

- Do not merge the analog powers with another power from other

VSSA

External

blocks.

VBBA

External

- Use good power and ground source on board.

VDDD

External

VSSD

External

VBBD

External

AINT, AINC

External/Internal

- Do not overlap with digital lines.
- Maintain the shortest path to pads.

REFTOP,

REFTOP1

External/Internal

- Maintain the larger width and the shorter length as far as the pads.
- Separate from all other digital lines.

REFBOT,

REFBOT1

External/Internal

SPEEDUP

External/Internal

- Separate from all other analog signals

CKIN

External/Internal

STBY

External/Internal

ADO[11]

External/Internal

- Separated from the analog clean signals if possible.

ADO[10]

External/Internal

ADO[9]

External/Internal

ADO[8]

External/Internal

ADO[7]

External/Internal

ADO[6]

External/Internal

ADO[5]

External/Internal

ADO[4]

External/Internal

ADO[3]

External/Internal

ADO[2]

External/Internal

ADO[1]

External/Internal

ADO[0]

External/Internal

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BW1009L

FEEDBACK

REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic cheking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog Power Supply Voltage

Digital Power Supply Voltage

Bit Resolution

Bit

Reference Input Voltage

Analog Input Voltage

Vpp

Operating Temperature

Integral Non-linearity Error

LSB

Differential Non-linearity Error

LSB

Bottom Offset Voltage Error

Top Offset Voltage Error

Maximum Conversion Rate

MSPS

Dynamic Supply Current

Power Dissipation

Signal-to-noise Ratio

Pipeline Delay

CLK

Digital Output Format (Provide detailed
description & timing diagram)

1. Between single input-output and differential input-output configurations, which one is suitable for your system

and why?

2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason

to prefer some type of configuration.

3. Freely list those functions you want to be implemented in our ADC, if you have any.

BW1009L

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HISTORY CARD

Version

Date

Modified Items

Comments

ver 1.0

Original version published (preliminary)

ver 1.1

ver 1.2

ver 1.3

ver 1.4

ver 1.5

1999.07

Release the formal datasheet

ver 1.6

02.04.29

Add the pin information to the phantom cell information

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