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BW1254X

GENERAL DESCRIPTION

bw1254x is a CMOS 14bit analog-to-digital converter (ADC). It converts the analog input signal into 14bit binary
digital codes at a maximum sampling rate of 10MHz.

The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current
reference and voltage reference. The structure allows both differential and single-ended input.

TYPICAL APPLICATIONS

-- Imaging (Copiers, Scanners, Cameras)

-- Medical Instruments

-- Digital Communication Systems

-- uADSL System

FEATURES

-- Resolution : 14bit

-- Maximum Conversion Rate : 10MHz

-- Package Type : 48TSSOP

-- Power Supply : 3.3V

-- Power Consumption : 120mW (typical)

-- Reference Voltage : Internal reference or 2V, 1V (dual reference)

-- Input Range : 0.5V ~ 2.5V (2.0V

P-P

)

-- Differential Linearity Error : ±0.7 LSB

-- Integral Linearity Error : ±1.5 LSB

-- Signal to Noise & Distortion Ratio : 72dB

-- Total Harmonic Distortion : 80dB

-- Out of Range Indicator

-- Digital Output : CMOS Level

-- Operating Temperature Range : 0

C ~ 70

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BW1254X

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

REFTOP

piar10_bb

Reference Top Output/Force (2.0V)

REFBOT

piar10_bb

Reference Bottom Output/Force (1.0V)

BGR

piar10_bb

BGR output (1.23V)

CML

piar10_bb

Internal Bias

CML1

piar10_bb

Internal Bias

VDDA1

vdda

Analog Power (3.3V)

VBBA1

vbba

Analog Sub Bias

VSSA1

vssa

Analog Ground

AINT

piar10_bb

Analog Input +
(Input Range : 1.0V ~ 2.0V)

AINC

piar10_bb

Analog Input -
(Input Range : 1.0V ~ 2.0V)

ITEST

pia_bb

open=use internal bias point

STBY

picc_bb

VDD=power saving (standby), GND=normal

CKIN

picc_bb

Sampling Clock Input

D[13:0]

poa_bb

Digital Output

ORI

poa_bb

Out of Range Indicator

VBBA2

vbba

Digital Sub Bias

VSSA2

vssd

Digital GND

VDDA2

vddd

Digital Power (3.3V)

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AP: Analog Power

-- AG: Analog Ground

-- DP: Digital Power

-- DG: Digital Ground

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

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BW1254X

ABSOLUTE MAXIMUM RATINGS

Characteristics

Symbol

Value

Unit

Supply Voltage

VDD

4.5

Analog Input Voltage

AINT/AINC

VSS to VDD

Digital Input Voltage

CLK

VSS to VDD

Storage Temperature Range

Tstg

-45 to 150

Operating Temperature Range

Topr

0 to 70

NOTE:
1.

Absolute

maximum

rating

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDDA1
VDDA2
VDDA3

3.15

3.3

3.45

Analog Input Voltage

AINT

AINC

0.5

1.5

2.5

Operating Temperature

Toper

NOTE: It

strongly

recommended

that

all

the

supply

pins

(VDDA1,

VDDA2,

VDDA3)

powered

from

the

same

source

avoid

power

latch-up.

BW1254X

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DC ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Differential

Nonlinearity

DNL

0.7

LSB

Internal Voltage Reference

REFTOP=2V
REFBOT=1V

Integral

Nonlinearity

INL

1.5

LSB

Internal Voltage Reference

REFTOP=2V
REFBOT=1V

Offset

Voltage

OFF

REFTOP=2V
REFBOT=1V

NOTE: Converter

Specifications

VDDA1=VDDA2=VDDA3=3.3V,

VSSA1=VSSA2=VSSA3=0V,

Toper=25

REFTOP=2V,

REFBOT=1V

unless

otherwise

specified.

ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Test Condition

Maximum

Conversion Rate

MHz

AIN=AINT-AINC

Dynamic Supply

Current

IVDD

fc=10MHz

(without system load)

Signal-to-Noise &

Distortion Ratio

SNDR

AIN=1MHz,

Differential Input

Total Harmonic

Distortion

THD

AIN=1MHz,

Differential Input

NOTE: It

strongly

recommended

that

all

the

supply

pins

(VDDA1,

VDDA2,

VDDA3)

powered

from

the

same

source

avoid

power

latch-up.

BW1254X

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m 14-BIT 10MSPS ADC

FUNCTIONAL DESCRIPTION

1. The BW1254X is a CMOS four step pipelined Analog-to-Digital Converter. It contains 5-bit flash A/D

Converters, 4bit, two 3bit flash A/D converters and three multiplying D/A Convertors. The N-bit flash ADC is
composed of 2N-1 latched comparators, and multiplying DAC is composed of 2*(2N+1) capacitors and two
fully-differential amplifiers.

2. The BW1254X operates as follows. During the first "L" cycle of external clock the analog input data is

sampled, and the input is held from the rising edge of the external clock, which is fed to the first 5-bit flash
ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 5-bit
ADC's output, and finally amplifies a residue voltage by 24. The second and third flash ADC, and MDAC are
worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit
flash ADC decides final 3-bit digital digital code.

3. BW1254X has the error correction scheme, which handles the output from mismatch in the first, second, third

and fourth flash ADC.

MAIN BLOCK DESCRIPTION

1. SHA

SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until
next sample-time. It is good as small as its different value between analog input signal and output signal. SHA
amp gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less
than 1/2 LSB error voltage at 14bit resolution. This SHA is consist of fully differential op amp, switching tr. and
sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is
about 4pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is designed that
open-loop dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to
be the rail-to-rail architecture using complementary different pair.

2. FLASH

The 5-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer
to MDAC and digital correction logic block. It is realized fully differential comparators of 31EA. Considering
self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the
reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the
phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values
dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by
Q1P.

3. MDAC

MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage
op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the
analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array
internal switches. If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2
are all on. Therefore the capacitors of c_array can charge analog input values held at SHA.

BW1254X

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PACKAGE CONFIGURATION

BW1254X

BGR

REFTOP

REFBOT

CML

CML1

VDDA1

VBBA1

VSSA1

AINT

AINC

ITEST

STBY

VDDA3

VSSA3

VDDA2

VSSA2

VBBA2

CKIN

DO[13]

DO[12]

DO[11]

DO[10]

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

ORI

TRIST

10u

0.1u

10u

0.1u

10u

0.1u

10u

0.1u

10u

0.1u

10u

Digital I

Digital II

Analog

0.1u

10u

0.1u

10u

NOTE: NC denotes "No Connection".

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BW1254X

PACKAGE PIN DESCRIPTION

Pin No.

Name

I/O Type

Pin Description

BGR

Reference Voltage Output

REFTOP

Reference Top Output/Force

REFBOT

Reference bottom Output/Force

CML

Internal Bias

CML1

Internal Bias

6, 7

VDDA1

Analog Power (3.3V)

VBBA1

Analog Sub Bias

9, 10

VSSA1

Analog Ground

AINT

Analog Input +

AINC

Analog Input -

ITEST

open=use internal bias circuit

STBY

VDDA=Power saving (Standby),
GNP=Normal

VDDA3

PAD Power (3.3V)

VSSA3

PAD Ground

TRIST

Tri-state Buffer Input
VDD=High Impedance,
GND=Normal

ORI

Out of Range Indicator
Normal='Low'
Out of Range='High'

DO[0]

Digital Output (LSB)

28~39

DO[1:12]

Digital Output

DO[13]

Digital Output (MSB)

CKIN

Sampling Clock Input

VBBA2

Digital Sub Bias

45, 46

VSSA2

Digital GND

47, 48

VDDA2

Digital Power (3.3V)

NOTE: I/O

TYPE

and

denote

PAD

Power

and

PAD

Ground

respectively.

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BW1254X

USER GUIDE

1. Input Range

If you want to using the single-ended input, you should use he input range as below.

AINT: 0.5V ~ 2.5V,
AINC: 1.5V.

If you want to using the differential input, you should use the input range as below.

AINT: 1.0V ~ 2.0V,
AINC: 1.0V ~ 2.0V.
AIN: AINT - AINC

If you want to changing input range (AIN span), you can force reference voltages.

AIN span = -REF ~ +REF
REF = REFTOP - REFBOT

2. Power Consumption/Speed Optimization

Yon can optimize the power consumption, as control the ITEST voltage level precisely .
You can optimize the ADC's speed also, as control the ITEST voltage level.

BW1254X

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PHANTOM CELL INFORMATION

-- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design

methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.

bw1254x

14bit 10MSPS ADC

VB
B

VS
S
A

VD
DA

VB
B

VS
S
A

VD
DA

CML1

RETOP

CKIN

CML

STBY

VDDD

DO
[
0
]

DO
[
1
]

DO
[
2
]

DO
[
3
]

DO
[
4
]

DO
[
5
]

DO
[
6
]

DO
[
7
]

DO
[
8
]

DO
[
9
]

OR
I

ES
T

REFBOT

BGR

VSSD

VBBD

DO[

1
0
]

DO[

1
1
]

DO[

1
2
]

DO[

1
3
]

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m 14-BIT 10MSPS ADC

BW1254X

PHANTOM CELL INFORMATION (Continued)

Pin Name

Pin Usage

Pin Layout Guide

VDDA

External

- Maintain the large width of lines as far as the pads.

VSSA

External

- place the port positions to minimize the length of power lines.

VBBA

External

- Do not merge the analog powers with anoter power from other

VDDD

External

blocks.

VSSD

External

- Use good power and ground source on board.

VBBD

External

AINT

External/Internal

- Do not overlap with digtal lines.
- Maintain the shotest path to pads.

AINC

External/Internal

CKIN

External/Internal

- Separate from all other analog signals

REFTOP

External/Internal

- Maintain the larger width and the shorter length as far as the pads.
- Separate from all other digital lines.

REFBOT

External/Internal

CML

External/Internal

- Separate from all other digital lines.

CML1

External/Internal

BGR

External/Internal

ITEST

External/Internal

STBY

External/Internal

ORI

External/Internal

- Separated from the analog clean signals if possible.
- Do not exceed the length by 1,000um.

DO[13]

External/Internal

DO[12]

External/Internal

DO[11]

External/Internal

DO[10]

External/Internal

DO[9]

External/Internal

DO[8]

External/Internal

DO[7]

External/Internal

DO[6]

External/Internal

DO[5]

External/Internal

DO[4]

External/Internal

DO[3]

External/Internal

DO[2]

External/Internal

DO[1]

External/Internal

DO[0]

External/Internal

BW1254X

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FEEDBACK REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog Power Supply Voltage

Digital Power Supply Voltage

Bit Resolution

Bit

Reference Input Voltage

Analog Input Voltage

Vpp

Operating Temperature

Integral Non-linearity Error

LSB

Differential Non-linearity Error

LSB

Bottom Offset Voltage Error

Top Offset Voltage Error

Maximum Conversion Rate

MSPS

Dynamic Supply Current

Power Dissipation

Signal-to-noise Ratio

Pipeline Delay

CLK

Digital Output Format
(Provide detailed description &
timing diagram)

1. Between single input-output and differential input-output configurations, which one is suitable for your system

and why?

2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason

to prefer some type of configuration.

3. Freely list those functions you want to be implemented in our ADC, if you have any.

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