PGA

Voice Signal Interface Codec

cod0413x_pci

SEC ASIC

ANALOG

GENERAL DESCRIPTION

This IP core has been developing for AFE

(Analog-front-end) function of voice signal processing
with 14bit 8KHz voice codec.

The core consists of 14bit linear monolithic PCM

CODEC/transmit and receive band-pass filters utilizing
the sigma-delta A/D and D/A conversion architecture.

It offers a number of programmable functions

accessed through a serial control channel that easily
interfaces to any classical micro controller.

This IP core is suitable for digital mobile phones, as

cellular and cordless phones, or any battery powered
equipment.

FEATURES

Analog 2.5Volt Operation

Linear 14bit Codec

3 Mic Inputs (2 Differential and 1 Single)

3 Analog Outputs 32ohm Driver (2 Differential

and 1 Single)

Mic Volume 0dB ~ 22.5dB & 20dB Gain On/Off

Speaker Volume 0dB ~ -30dB

Side-tone -12.5dB ~ -27.5dB

Serial Data Input, Output Format

Control Register Interface for u-Controller

APPLICATIONS

digital mobile phones

cellular and cordless phones

ADC

DAC

MIC1P
MIC1N
MIC2P
MIC2N
MIC3

AOUT1P
AOUT1N

AOUT2P
AOUT2N

AOUT3

SOUT
SIN

CONTROL

VREF

REFERENCE

CSB
WRB
RDB
A[8:0]
DIN[7:0]

MIC VOLUME

0dB~22.5dB

1.5dB Step

ISS[1:0]

TGN[3:0]

SIDETONE AMP

-12.5dB~-27.5dB

-1dB Step

OSS[1:0]

RGN[3:0]

SPEAKER VOLUME

0dB~-30dB

-2.dB Step

AVDD25A1

AVDD25A3

AVDD25A2

AVDD25A4

STEN

PGA

IREF

(Test Pin)

SGN[3:0]

20dB

On/Off

X10

PORSB

MCLK
FS

AVDD25A5

AVDD25A6

FUNCTIONAL BLOCK DIAGRAM

DOUT[7:0]

REN

AVSS25A1

AVSS25A3

AVSS25A2

AVSS25A4

AVSS25A5

AVSS25A6

AVDD25A7

AVDD25A8

AVSS25A7

AVSS25A8

AVDD25D

AVSS25D

VABB

1 / 13

Ver 1.4 (Apr 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third
parties that may result from its use. The content of this datasheet is subject to change without any notice.

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

PIN NAME

Type

I/O Type

FUNCTION

Power Pins

AVDD25A1

vdd2t_abb

Analog Power Supply 1 (2.5V)

AVSS25A1

vss2t_abb

Analog Ground 1

AVDD25A2

vdd2t_abb

Analog Power Supply 2 (2.5V)

AVSS25A2

vss2t_abb

Analog Ground 2

AVDD25A3

vdd2t_abb

Analog Power Supply 3 (2.5V)

AVSS25A3

vss2t_abb

Analog Ground 3

AVDD25A4

vdd2t_abb

Analog Power Supply 4 (2.5V)

AVSS25A4

vss2t_abb

Analog Ground 4

AVDD25A5

vdd2t_abb

Analog Power Supply 5 (2.5V)

AVSS25A5

vss2t_abb

Analog Ground 5

AVDD25A6

vdd2t_abb

Digital Power Supply 6 (2.5V)

AVSS25A6

vss2t_abb

Digital Ground 6

AVDD25A7

vdd2t_abb

Analog Power Supply 7 (2.5V)

AVSS25A7

vss2t_abb

Analog Ground 7

AVDD25A8

vdd2t_abb

Analog Power Supply 8 (2.5V)

AVSS25A8

vss2t_abb

Analog Ground 8

AVDD25D

vdd2t_abb

Digital Power Supply (2.5V)

AVSS25D

vss2t_abb

Digital Ground

VABB

vbb_abb

Analog Ground

Analog Pins

MIC1P

pia_abb

Mic Input 1 Positive

MIC1N

pia_abb

Mic Input 1 Negative

MIC2P

pia_abb

Mic Input 2 Positive

MIC2N

pia_abb

Mic Input 2 Negative

MIC3

pia_abb

Mic Input 3 (Single Input)

AOUT1P

poa_abb

Differential Output 1 Positive

AOUT1N

poa_abb

Differential Output 1 Negative

AOUT2P

poa_abb

Differential Output 2 Positive

AOUT2N

poa_abb

Differential Output 2 Negative

AOUT3

poa_abb

Single Output

VREF

poa_abb

Reference Output

VCOMDR

poa_abb

tied to VREF pin

VCOMDT

poa_abb

tied to VREF pin

VCOMR

poa_abb

tied to VREF pin

VCOMT

poa_abb

tied to VREF pin

VREFMR

poa_abb

tied to Analog Ground pin

VREFMT

poa_abb

tied to Analog Ground pin

VREFPR

poa_abb

tied to VREF pin

VREFPT

poa_abb

tied to VREF pin

IREF

poa_abb

Analog Current Control (Test Pin). If this pin is not used, it may be left floating state.

CORE PIN DIAGRAM

I/O TYPE ABBR.

AI : Analog Input

DI : Digital Input

AO : Analog Output

DO : Digital Output

AB : Analog Bidirectional

DB : Digital Bidirectional

AP : Analog Power

AG : Analog Ground

DP : Digital Power

DG : Digital Ground

2 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

3 / 13

Power Group :

AVDD25A1 (AVDD25A1,AVDD25A2,AVDD25A3,AVDD25A4,AVDD25A5,AVDD25A6,AVDD25A8)

AVDD25A2 (AVDD25A7)

AVDD25D (AVDD25D)

Digital Pins

SOUT

pot2_abb

ADC Serial Data Ouput

SIN

picc_abb

DAC Serial Data Input

MCLK

picc_abb

Master Clock Input

picc_abb

Frame Sync Pulse Input

PORSB

picc_abb

Power-On-Reset and Reset Control Input (Low Active)

CSB

picc_abb

Chip Select (Low Active)

WRB

picc_abb

Write Enable (Low Active)

RDB

picc_abb

Read Enable (Low Active)

A[8:0]

picc_abb

Control Register Address

DIN[7:0]

picc_abb

Control Register Data Input (WR is Enabled)

DOUT[7:0]

pot2_abb

Control Register Data Output (RD is Enabled)

CORE CONFIGURATION

cod0413x_pci

SIN

MCLK

MIC1P

MIC1N

MIC2P

MIC2N

MIC3

AOUT1P
AOUT1N

PORSB

CSB

WRB

RDB

A[8:0]

DIN[7:0]

AOUT2P
AOUT2N
AOUT3
SOUT
VREF

IREF

2
5
A

S
S
2
5
A

DOUT[7:0]

VCOMDR
VCOMDT
VCOMR
VCOMT
VREFMR
VREFMT
VREFPR
VREFPT

S
S
2
5
A

S
S
2
5
D

2
5
A

2
5
D

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Characteristic

Symbol

Value

Unit

Supply Voltage

AVDD25A1
AVDD25A2

AVDD25D

3.3

Analog Input Voltage

AVSS25A1 to AVDD25A1
AVSS25A2 to AVDD25A2

Digital Input Voltage

AVSS25D to AVDD25D

Digital Output Voltage

, V

AVSS25D to AVDD25D

Storage Temperature Range

Tstg

-45 to 125

ºC

ABSOLUTE MAXIMUM RATINGS

NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.

Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.

2. All voltages are measured with respect to VSS unless otherwise specified.

3. 100pF capacitor is discharged through a 1.5K

resistor (Human body model)

4. This core has initial calibration time for about 3m second from rising edge of PORSB.

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

AVDD25A1,AVDD25A2,

AVDD25D

2.375

2.5

2.625

Supply Voltage Difference

AVDD25A1, AVDD25A2,

AVDD25D

-0.1

0.0

0.1

Digital Input Voltage

2.25

2.5

2.75

Analog Input Voltage

1.6

Vpp

Operating Temperature

Topr

-40

ºC

NOTES

1. It is strongly recommended that all the supply pins (AVDD25A1, AVDD25A2, AVDD25D) be powered from the same

source to avoid power latch-up.

AC ELECTRICAL CHARACTERISTICS

(Measurement Bandwidth is 20Hz~4KHz. Full scale input sine wave 1KHz, FS=8KHz, @AVDD25A1=2.5V, AVDD25A2=2.5V,
AVDD25D=2.5V Ta=55ºC,Unless otherwise specified.)

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Resolution

Bits

Sampling rate

KHz

ADC Characteristics

* Signal to Distortion Ratio

0dB Input : Linear

Offset Error

Input Voltage Range

1.6

Vpp

DAC Characteristics

* Signal to Distortion Ratio

0dB Input : Linear

Offset Error

Output Voltage Range

1.6
3.2

-
-

Vpp
Vpp

Differential

4 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Power Supply

Power consumption

(Operating Mode)

Analog

Digital

6.5
0.5

-
-

mA
mA

No load

Power consumption

(Power down mode)

TRANS-MISSION CHARACTERISTICS

(Measurement Bandwidth is 60Hz~4KHz. Full scale, FS=8KHz, @AVDD25A1=2.5V, AVDD25A2=2.5V, AVDD25D=2.5V

Ta=55ºC,,Unless otherwise specified.)

Characteristics

Test Condition

Min

Typ

Max

Unit

Transmit Gain Variation with
Frequency

Relative to 1000Hz
f = 60Hz

f = 200Hz
f = 300Hz

f = 400Hz ~ 3000Hz
f = 3400Hz]

f = 4000Hz
f = 8000Hz

-
-

-7.9

-1.5
-0.6

-0.2
-1.1

-17.8
-62.8

dB
dB

Receive Gain Variation with
Frequency

Relative to 1000Hz
f = 60Hz

f = 200Hz
f = 300Hz

f = 400Hz ~ 3000Hz
f = 3400Hz]

f = 4000Hz

-
-

0.6

-
-

-8.2

-1.4
-0.6

-0.2
-0.7

-17.8

dB
dB

Transmit Delay

f = 60hz ~ 3000Hz

750

Receive Delay

f = 60Hz ~ 3000Hz

750

CONTROL CLOCKS CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

MCLK Frequency

Fmclk

2.048

MHz

MCLK Duty Cycle (H/L)

McDuty

50:50

FS Frequency

Fsync

KHz

MCLK Falling and FS SetUp

TsuI

MCLK Falling and FS Hold

ThdI

MCLK Rising and SOUT Delay

Tdsdout

MCLK Falling and SIN SetUp

Tsusin

MCLK Falling and SIN Hold

Thdsin

WR Rising and A[8:0] SetUp

Tsuwra

WR Rising and A[8:0] Hold

Thdwra

WR Rising and DIN[7:0] SetUp

Tsuwrd

WR Rising and DIN[7:0] Hold

Thdwrd

RD Falling and A[8:0] SetUp

Tsurda

RD Rising and A[8:0] Hold

Thdrda

RD Falling and DOUT[8:0] Delay

Tdrdf

RD Rising and DOUT[8:0] Delay

Tdrdr

5 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Timing Diagram

Serial Data Interface

Control Register Interface

WRB

RDB

A[8:0]

Tsuwra

Thdwra

Tsurda

Thdrda

Tdrdr

Tdrdf

Thdwrd

Tsuwrd

DIN[7:0]

DOUT[7:0]

A[8:0]

Write Mode

Read Mode

MCLK

SIN

Tsui

Thdi

Fmclk

"L"

"H"

LSBit

Tsusin

MSBit

Thdsin

MCLK

SOUT

Serial Output Format

Tsui

Fmclk

"L"

"H"

LSBit

Tdsdout

MSBit

Thdi

McDuty

Serial Input Format

CSB

(Low)

CSB

(Low)

PORSB

(High)

PORSB

(High)

6 / 13

Note : Of the data written on the registers, the control signals(OSS, STEN, RGN)

for Tx path are assigned at the rising edge of the internal signal RXZC.

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Programmable Functions

Control Register Mapping Table

ADDRESS

FUNCTION

DATA[7:0]

A[8:0]

0D0h

Status

INIT

0D1h

Power Management

PW[2]

PW[1]

PW[0]

0D2h

Path Select

ISS[1]

ISS[0]

STEN

OSS[1]

OSS[0]

REN

0D3h

Mic Volume

T20DB

TGN[3]

TGN[2]

TGN[1]

TGN[0]

0D4h

Speaker Volume

RGN[3]

RGN[2]

RGN[1]

RGN[0]

0D5h

Sidetone Volume

SGN[3]

SGN[2]

SGN[1]

SGN[0]

0D6h

Miscellaneous

CALDIS

DLB

0D7h

Test Path

TLBM

DIBYP MOBYP

AMOPI

ABYP

ALBM

DLBM

Status Register (0D0H); Read Only

FUNCTION

INIT

0
1

Under Initializing

Initialize Done

Power Management (0D1H)

FUNCTION

PW[2]

PW[1]

PW[0]

0
0
0
0
1

0
0
1
1
x

0
1
0
1
x

All Power Down (*)

Standby Mode

Rx Power Up, Tx Power Down
Tx Power Up, Rx Power Down

All Power Up

Path Selection (0D2H)

FUNCTION

ISS[1]

ISS[0]

STEN

OSS[1] OSS[0]

REN

0
0
1
1

0
1
0
1

All Muted (*)

MIC1P, MIC1N Selected

MIC2P, MICT2N Selected

MIC3 Selected

0
1

Sidetone Disabled (*)

Side Tone Enabled

0
1

Receive path Disaable (*)

Receive path Enable

0
0
1
1

0
1
0
1

All Muted (*)

AOUT1P, AOUT1N Selected
AOUT2P, AOUT2N Selected

AOUT3 Selected

7 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Mic volume control register (0D3H)

FUNCTION

T20DB

TGN[3] TGN[2] TGN[1] TGN[0]

0
1

0dB Selected (*)

20dB Selected

0
0

0
1

0dB Selected (*)

1.5dB Selected

22.5dB Selected

Speaker Volume Control Register (0D4H)

FUNCTION

RGN[3] RGN[2] RGN[1] RGN[0]

0
0

0
1

0dB Selected (*)

-2dB Selected

-30dB Selected

Sidetone Volume Control Register (0D5H)

FUNCTION

SGN[3] SGN[2] SGN[1] SGN[0]

0
0

0
1

-12.5dB Selected (*)

-13.5dB Selected

-27.5dB Selected

Miscellaneous Control Register (0D6H)

FUNCTION

CALDIS

DBYP

0
1

Calibration Function Enabled (*)

Calibration Function Disabled

0
1

Serial Data Loop Back Disabled (*)

Serial Data Loop Back Enabled

Test Mode Control Register (0D7H)

FUNCTION

TLBM DIBYP

MOBY

AMOPI ABYP

ALBM

DLBM

0
1

ADC/DAC Loop Mode disabled (*)

ADC/DAC Loop Mode enabled

Digital Decimator Filter Input

Bypass Disabled (*)

Digital Decimator Filter Input

Bypass Enabled

8 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Digital Modulator Output Bypass

Disabled (*)

Digital Modulator Ourput Bypass

Enabled

Analog Moulator Output / Postfilter

Input Bypass Disabled (*)

Analog Moulator Output / Postfilter

Input Bypass Enabled (*)

Analog Bypass Disabled (*)

Analog Bypass Enabled

0
1

Analog Loop Back Disabled (*)

Analog Loop Back Enabled

0
1

Digital Loop Back Disabled (*)

Digital Loop Back Enabled

Power Down/Up Management Guide

cod0413x_pci is capable of operating at required power when no activity is required. The State of power

down/up is controlled by the Power Management Register(0D1H).

Normal Operation

(All Power Up)

Standby Mode

Rx Power Up

Tx Power Down

Tx Power Up

Rx power Down

All Power Down

The above figure illustrates one example procedure a complete power down/up of cod0413x_pci.
From normal operation sequential writes to the Power Management Register are preformed to power down/up

cod0413x_pci a piece at a time

9 / 13

VREF

VCOMR
VREFPR
VCOMDR

VCOMDT

VREFPT

VCOMT

VREF

CHIP

Lead Frame

REFERENCE VOLTAGE & POWER LINE CONNECTION

Layout Guide

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

10 / 13

AVDD25A2

AVDD25A7(W=45um)

Lead Frame

AVSS25A2

AVDD25D(W=10um)

AVSS25A7(W=45um)

Lead Frame

AVDD25A6(W=10um)

AVDD25A1

AVDD25A1(W=20um)
AVDD25A2(W=20um)
AVDD25A3(W=10um)
AVDD25A4(W=10um)
AVDD25A5(W=20um)

AVDD25A8(W=9um

AVSS25A1

AVSS25A1(W=20um)

AVSS25A2(W=20um)
AVSS25A3(W=10um)
AVSS25A4(W=10um)
AVSS25A5(W=20um)

AVSS25A8(W=9um)

VABB(W=10um)

VREFMT(W=2.4um)

VREFMR(W=2.2um)

AVDD25D

Lead Frame

AVSS25D(W=10um)

AVSS25A6(W=10um)

AVSS25D

Lead Frame

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

Pin Name

Pin

Usage

Pin Layout Guide

AVDD25A6 External

- Maintain the large width of lines as

far as the pads.

- Place the port positions to minimize

the length of power lines.

- Do not merge the analog powers with

anoter power from other blocks.

- Use good power and ground source

on board.

AVSS25A6

External

AVDD25A7 External

AVSS25A7

External

AVDD25A8 External

AVSS25A8

External

AVDD25D

External

AVSS25D

External

VABB

External

MIC1P

External

- Do not overlap with digtal lines.

- Maintain the shotest path to pads.

MIC1N

External

MIC2P

External

MIC2N

External

MIC3

External

AOUT1P

External

AOUT1N

External

AOUT2P

External

AOUT2N

External

AOUT3

External

VREF

External

- Maintain the larger width and the

shorter length as far as the pads.

- Separate from all other digital lines.

VCOMDR

External

VCOMDT

External

VCOMR

External

VCOMT

External

VREFPR

External

VREFPT

External

VREFMR

External

VREFMT

External

IREF

External

SOUT

External/

Internal

SIN

External/

Internal

MCLK

External/

Internal

- Separate from all other analog signals

External/

Internal

PORSB

External/

Internal

CSB

External/

Internal

WRB

External/

Internal

RDB

External/

Internal

A[8:0]

External/

Internal

DIN[7:0]

External/

Internal

DOUT[7:0] External/

Internal

MIC3

MIC2P

MIC1P

MIC1N

MIC2N

VCOMT

VREFMT

VREFPT

VCOMDT

AVSS25A3

AVDD25A3

AVDD25A4

VREF

AVSS25A4

VCOMDR

VREFPR

VREFMR

IREF

VCOMR

AOUT3

AOUT2P

AOUT2N

AOUT1P

AOUT1N

S
S
2
5
D

2
5
A

2
5
D

S
S
2
5
A

2
5
A

S
S
2
5
A

2
5
A

S
S
2
5
A

2
5
A

S
S
2
5
A

2
5
D

S
S
2
5
D

cod0413x_pci

14b 8k voice codec

2
5
A

S
S
2
5
A

CSB

A[8:0]

WRB

RDB

DIN[7:0]

DOUT[7:0]

PORSB

SIN

SOUT

11 / 13

Phantom cell

Pin Name

Pin

Usage

Pin Layout Guide

AVDD25A1 External

- Maintain the large width of lines as

far as the pads.

- Place the port positions to minimize

the length of power lines.

- Do not merge the analog powers with

anoter power from other blocks.

- Use good power and ground source on

board.

AVSS25A1

External

AVDD25A2 External

AVSS25A2

External

AVDD25A3 External

AVSS25A3

External

AVDD25A4 External

AVSS25A4

External

AVDD25A5 External

AVSS25A5

External

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

NOTES
1. If SOUT is externally shorted with SIN, The CODEC is achieved to loop-back test mode(ADC->DAC).
2. If end users want to test CODEC in integrated chip, The above pin must be extracted to the PAD.
3. The analog power/ground must be separated from digital power/ground.
4. Power typical value :

AVDD25A1 = AVDD25A2 =AVDD25D= 2.5V, AVSS25A1 = AVSS25A2 =AVSS25D= 0.0V

LOCATION

DESCRIPTION

0.1uF TANTALUM CAPACITOR

10uF CERAMIC CAPACITOR

0.47uF CERAMIC CAPACITOR

RESISTOR

CORE EVALUATION GUIDE

12 / 13

AVDD25A1

AVSS25A1

AVDD25A2

AVSS25A2

SELECT

PORSB

CSB

WRB

RDB

SOUT

SIN

MCLK

A[8:0]

DIN[7:0]

cod0413x_pci

TEST PATH

MAIN PATH

2.5V

AVDD25D

AVSS25D

2.5V

VREF

IREF

DOUT[7:0]

MIC1P

MIC1N

MIC2P

MIC2N

MIC3

AOUT1P

AOUT1N

AOUT2P

AOUT2N

AOUT3

SPEAKER

MIC

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

FEEDBACK REQUEST

It should be quite helpful to our CODEC core development if you specify your system requirements on CODEC
in the following characteristic checking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.

Could you explain external/internal pin configurations as required?

Specially requested function list :

1. What is your signal band to use, 3.6KHz? 4KHz? or 4.8KHz?
2. What is your analog in/output signal voltage swing? and what kind of format do your want as analog signal in/ouput:
single or differential format? If you can, Please let us know, what is your exact in/output signal spec.
3. What is your minimum S/N+D spec?
4. Do you want linear phase characteristic or you don't care on digital filter spec?

5. Could you give us exact design spec of speech codec? (For example, A-law, u-law and so on.)

13 / 13

cod0413x_pci

Voice Band Signal Interface

SEC ASIC

ANALOG

HISTORY CARD

Version

Date

Modified Items

Comments

Ver 1.0

'99.Nov. 1.Original version published

Ver 1.1

'00.Feb

1.REN signal (Path Selection) added
2.Power Grouping information

AVDD25A1 : AVDD25A1,AVDD25A2,AVDD25A3,AVDD25A4,

AVDD25A5,AVDD25A6,AVDD25A8

AVDD25A2 : AVDD25A7
AVDD25D : AVDD25D
AVSS25A1 : AVSS25A1,AVSS25A2,AVSS25A3,AVSS25A4,

AVSS25A5,AVSS25A6,AVSS25A8,VABB

AVSS25A2 : AVSS25A7
AVSS25D : AVSS25D

Ver 1.2

'00.Mar

1. Add Codec Bulk VABB to Pin List
2. Connect AVDD25A6, AVDD25D to Glue Logic Power.

Connect AVSS25A6, AVSS25D to Glue Logic Ground.

3. Add ADC1255X_PCI Digital/IO Power/GND

Connection Information to Layout Guide

Ver 1.3

'00.Jul

1. Layout Guide Changed

- Analog Power(AVDD25A1) is not shared with ADC analog Power
- Digital Power(AVDD25D) Pin, Digital Ground(AVSS25D) Pin

added

Ver 1.4

'02 Apr 1. Phantom cell added

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: cod0413x_pci

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: cod0413x_pci