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Электронный компонент: dac1252x

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DAC1252X
0.25

m 2.5V 8-bit 2MSPS DAC
1
GENERAL DESCRIPTION
DAC1252X is a CMOS 8BIT D/A converter for general application. This digital to analog converter has a R2R
structure. Its settling time is 500ns (Typical value).
FEATURES
-- Resolution:
8-BIT
-- Differential
Linearity
Error:
1.0
LSB
-- Integral
Linearity
Error:
1.0
LSB
-- Settling
Time:
500ns
-- Low
Power
Consumption:
890
A
-- Power
Down
Mode
-- Operation
Temperature
Range:
0
C
~
70
C
-- Power
Supply:
2.5V
Single
TYPICAL APPLICATIONS
-- Hard Disk Driver (HDD)
-- Battery Operated Instruments
-- Motor Control Systems
-- General Applications
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
2
FUNCTIONAL BLOCK DIAGRAM
D[7:0]
R2R
VRB
VRT
VOUT
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
AMP
_
+
PD
Ver 2.1 (Apr. 2002)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may result from its use. The content of this data sheet
is subject to change without any notice.
DAC1252X
0.25

m 2.5V 8-bit 2MSPS DAC
3
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
D[7:0]
DI
picc_abb
Digital Input Data (8BIT)
D[7]: MSB, D[0]: LSB
PD
DI
picc_abb
Power Down (Active Low)
VRT
AB
pia_abb
Voltage Reference Top
VRB
AB
pia_abb
Voltage Reference Bottom
VOUT
AO
poa_abb
Analog Voltage Output
AVDD25A
AP
vdd2t_abb
Analog Power (+2.5V)
AVSS25A
AG
vdd2t_abb
Analog Ground (0.0V)
AVDD25D
DP
vdd2t_abb
Digital Power (+2.5V)
AVSS25D
DG
vss2t_abb
Digital Ground (0.0V)
AVBB25A
AG
vbb_abb
Analog Sub Bias (0.0V)
I/O TYPE ABBR.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bidirectional
-- DB: Digital Bidirectional
-- AP: Analog Power
-- DP: Digital Power
-- AG: Analog Ground
-- DG: Digital Ground
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
4
CORE CONFIGURATION
VRT
VRB
D[7:0]
VOUT
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
PD
dac1252X
DAC1252X
0.25

m 2.5V 8-bit 2MSPS DAC
5
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply Voltage
VDD (AVDD25A,AVDD25D)
3.3
V
Analog Output Voltage
VOUT
AVSS25A to AVDD25A
V
Digital Input Voltage
D[7:0]
AVSS25D to AVDD25D
V
Reference Voltage
VRT
VRB
AVDD25A
AVSS25A
V
Operating Temperature Range
Topr
0 to 70
C
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure
to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is
not implied.
2. All voltages are measured with respect to VSS(AVSS25A or AVSS25D or AVBB25A) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k
resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
AVDD25A - AVSS25A
AVDD25D - AVSS25D
2.375
2.5
2.625
V
Supply Voltage Difference
AVDD25A - AVDD25D
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
-
0.0
-
-
2.5
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
-
0.7
VDD
-
-
0.3
VDD
-
V
Operating Temperature
Topr
0
-
70
C
NOTE: It is strongly recommended that to avoid power latch-up all the supply pins(AVDD25A,AVDD25D) be driven from the
same source.
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
6
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications: AVDD25A=AVDD25D=2.5V, AVSS25A=AVSS25D=AVBB25A=0V,PD=High,
Top=25
C, VRT=2.5V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Resolution
Bit
-
8
-
Bits
-
Differential Linearity Error
DLE
-
1.0
-
LSB
-
Integral Linearity Error
ILE
-
1.0
-
LSB
-
Zero Scale Error
1
V
ZSE
-
5
-
mV
VRT=2.5V , VRB=0.0V
Full Scale Voltage Error
2
V
FSE
-
5
-
mV
Maximum Output Voltage
Vo
MAX
-
2.499
-
V
Vo
MAX
=
VOUT(D[7:0]=High)
V
LSB
= Vo
MAX
/ 256
LSB Size
V
LSB
-
0.61
-
mV
EOT = VRT - AIN(254,255)
NOTES:
1.
V
ZSE
= VOUT(D[7:0]=Low) - VRB
2.
V
FSE
=VOUT(D[7:0]=High) - {(VRT-VRB)
255/256 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=AVSS25D=AVBB25A=0V, load cap=25pF
Top=25
C, PD=High, VRT=2.45V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Supply Current
Ivdd1
-
0.89
-
mA
Ivdd1 = I
VDD28AA0
+ I
AVDD25D
VRT=2.5V, VRB = 0.0V
Data Input: All Low or All High
Supply Current
Ivdd2
-
1.22
-
mA
Ivdd2 = I
AVDD25A
+
I
AVDD25D
Data Input: All Low or All High
Supply Current
(Power Down Mode)
Ivdd3
-
-
10
A
Ivdd3 = I
AVDD25A
+ I
AVDD25D
Data Rate = 2MHz
Load cap = 25pF, PWDN=LOW
Short Circuit Current
I
SC
-
12
-
mA
VOUT: AVSS25A or AVDD25A
Data Input: All High or All Low
Analog Output Delay
Td
-
65
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Rise
Time
Tr
-
100
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Analog Output Fall
Time
Tf
-
100
-
ns
Data Rate = 2MHz
Data: All HIGH
All LOW
Analog Output
Settling Time
Ts
-
500
-
ns
Data Rate = 2MHz
Data: All LOW
All HIGH
Power Down Off Time
Ton
-
500
-
ns
PD: HIGH
LOW
Power Down On Time
Toff
-
500
-
ns
PD: LOW
HIGH
DAC1252X
0.25

m 2.5V 8-bit 2MSPS DAC
7
TIMING DIAGRAM
DATA
VOUT
Td
00000000
11111111
50%
50%
VOUT
00000000
11111111
00000000
10%
90%
DATA
Tr
Tf
VOUT
00000000
11111111
00000000
50%
0.5LSB
DATA
Ts
PD
VOUT
Ton
50%
Toff
50%
0.5LSB
0.5LSB
0.0V
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within
1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The DAC1252X has a 8BIT R-string block, two decoders, two OP amps, and control block.
2. The digital outputs of two decoders decide the voltage level of R2R block.
V
VRT
VRB
2
(
* Dn)
Rstring
8
n
n 0
8
2
=
-
=
3. Normal Conditions: VRT=2.45V , VRB=0.05V, PD=Low
You can change the voltages of VRT and VRB to 2.5V and 0.0V , but the performance of DAC1252X will be
degraded.
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
8
CORE EVALUATION GUIDE
HOST
DSP
CORE
MUX
TEST PATH
8
8
8
Cc
Ct
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25A
2.5
V
GND
2.5
V
GND
Cc
Ct
Ct
Cc
Ct
Cc
2.45
V
GND
0.05
V
GND
D[11:0]
PD
VRT
VRB
VOUT
dac1252x
VOUT
Location
Description
Ct
10
F Tantalum Capacitor
Cc
0.1
F Ceramic Capacitor
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select the values of digital
inputs ( D[7:0] ).
See above figure. Only if it is, you can check the main function. (Linearity)
Normal Test Condition: VRT=2.45V, VRB=0.05V, PD=High
DAC1252X
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m 2.5V 8-bit 2MSPS DAC
9
PHANTOM CELL INFORMATION
AVBB25A
A
V
S
S
2
5
A
A
V
D
D
2
5
A
V
O
U
T
P
D
D
[
1
]
D
[
2
]
D
[
3
]
D
[
4
]
D
[
5
]
D
[
6
]
D
[
7
]
DAC1252X
D
[
0
]
VRT
VRB
AVSS25A
AVDD25A
AVDD25D
AVSS25D
Pin Name
Property
Pin Usage
Pin Layout Guide
D[7:0]
DI
Internal / External
1. Digital Input Signal lines must have same length to
reduce
propagation delay.
PD
DI
Internal / External
VRT
AB
Internal / External
1. Voltage reference lines (VRT / VRB) must be wide metal
to reduce voltage drop of metal lines.
2. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize
capacitive
coupling between the two signals.
VRB
AB
Internal / External
VOUT
AO
Internal / External
AVDD25A
AP
External
1. It is recommended that you use thick analog power
metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
AVSS25A
AG
External
AVDD25D
DP
External
AVSS25D
DG
External
AVBB25A
AG
External
NOTES:
1.
When the core block is connected to other blocks, it must be double guard-ring using N-well and P+ active to remove the
substrate and coupling noise. In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
10
PACKAGE CONFIGURATION
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AVDD25D
AVDD25D
AVSS25D
AVSS25D
NC
NC
NC
NC
NC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NC
NC
NC
NC
NC
VRB
VRB
AVBB25A
AVBB25A
NC
NC
NC
NC
NC
NC
NC
AVSS25A
AVSS25A
AVDD25A
AVDD25A
NC
NC
NC
NC
PD
VOUT
VOUT
NC
NC
VRT
VRT
Cc
Ct
L2
Cc
Ct
+
+
0.0V
2.5V
(VSS)
(VDD)
+
Ct
Cc
PD
VOUT
VRT
(2.45 V Typ.)
(0V in normal operation)
Ct
+
Cc
(0.05V Typ.)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
L3
L5
L4
DAC
1252X
Location
Description
Ct
10
F Tantalum Capacitor
Cc
0.1
F Ceramic Capacitor
L1~L5
Ferrite Bead ( 0.1mh )
DAC1252X
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m 2.5V 8-bit 2MSPS DAC
11
PACKAGE PIN DESCRIPTION
Name
Pin No
I/O Type
Pin Description
AVDD25D
1,2
DP
Digital Power (2.5V)
AVSS25D
3,4
DG
Digital Ground (0.0V)
D[7:0]
10~17
DI
Digital Input Data
VRB
23,24
AB
Voltage Reference Bottom (0.05V)
VRT
25,26
AB
Voltage Reference Top (2.45V)
VOUT
29,30
AO
Analog Voltage Output
PD
31
DI
Power Down Mode (High Active)
AVDD25A
36,37
AP
Analog Power (2.5V)
AVSS25A
38,39
AG
Analog Ground (0.0V)
AVBB25A
47,48
AB
Analog Sub Bias (0.0V)
NC
5,6,7,8,9,18,19
20,21,22,27
28,32,33,34
35,40.41,42,43
44,45,46
DO
No Connection
I/O TYPE ABBR.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bidirectional
-- DB: Digital Bidirectional
-- AP: Analog Power
-- DP: Digital Power
-- AG: Analog Ground
-- DG: Digital Ground
0.25

m 2.5V 8-bit 2MSPS DAC
DAC1252X
12
PC BOARD LAYOUT CONSIDERATION
1. PC BOARD CONSIDERATIONS
To minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled.
This trace length between groups of VDD (AVDD25A,AVDD25D) and VSS (AVSS25A,AVSS25D) pins should be
as short as possible so as to minimize inductive ringing.
2. SUPPLY DECOUPLING AND PLANES
For the decoupling capacitor between the power line and the ground line, 0.1uF ceramic capacitor is used in
parallel with a 10uF tantalum capacitor.
The digital power plane(AVDD25D) and analog power plane(AVDD25A) are connected through a ferrite bead,
and also the digital ground plane(AVSS25D) and the analog ground plane(AVSS25A). This ferrite bead should be
located within 3inches of the DAC1252X. The analog power plane supplies power to the DAC1252X of the analog
output pin and related devices.
DAC1252X
0.25

m 2.5V 8-bit 2MSPS DAC
13
FEEDBACK REQUEST
We appreciate your interest in out products. If you have further questions, please specify in the attached form.
Thank you very much.
Dc / Ac Electrical Characteristic
Characteristics
Min
Typ
Max
Unit
Remarks
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
C
Output Load Capacitor
pF
Output Load Resistor
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Voltage Output DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
V
Digital Input Format
Binary Code or 2's Complement Code
Current Output DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal
Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting
(RSET)
Pipeline Delay
sec
-- Do you want to Power down mode?
-- Do you want to Internal Reference Voltage (BGR)?
-- Which do you want to Serial Input TYPE or parallel Input TYPE?
-- Do you need 3.3V and 5V power supply in your system?
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m 2.5V 8-bit 2MSPS DAC
DAC1252X
14
HISTORY CARD
Version
Date
Modified Items
Comments
Ver 1.0
Aug.'98
Original version published
Ver 2.0
Feb.'00
Power Naming convention & Core layout Guide update
Ver 2.1
Apr.'02
Phantom Cell information update