DAC1264X_RA

0.18

m 3.3V 10-BIT 2MSPS DAC

GENERAL DESCRIPTION

The dac1264x_ra is a CMOS 10Bit D/A converter for general application. This digital to analog converter has a R-

string structure.

Its settling time is 400ns (Typical value).

FEATURES

-- Resolution : 10Bit
-- Differential Linearity Error :

1.0 LSB

-- Integral Linearity Error :

2.0 LSB

-- Settling Time : 400ns
-- Low Power Consumption : 3.0mA
-- Power Down Mode
-- Operation Temperature Range : 0

C 70

-- Power Supply : 3.3V Single

: 1.8V (for Digital Input)

TYPICAL APPLICATIONS

-- CD/DVD Servo
-- Motor Control Systems
-- General Applications

0.18

m 3.3V 10-BIT 2MSPS DAC

DAC1264X_RA

FUNCTIONAL BLOCK DIAGRAM

R-String

AINT

Level

Shifter

Two Decoders

Doutn

Doutm

3.3V
2.65V
1.65V
0.65V
0.0V

VTOP

VBOT

VRT

VHALF

VRB

Level

Shifter

PWDNB

AMP

AVDD33A AVSS33A

AVDD33D AVSS33D

AVBB

AVDD18D

VOUT

Slot Cell

Ver 1.7 (March 2003)

No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties

that may result from its use. The content of this datasheet is subject to change without any notice.

DAC1264X_RA

0.18

m 3.3V 10-BIT 2MSPS DAC

CORE PIN DESCRIPTION

Pin Name

I/O Type

I/O Pad

Pin Description

D[9:0]

picc_abb

Digital Input Data (10bit : 1.8V)
D[9] : MSB , D[0] : LSB

PWDNB

picc_abb

Power Down (Active Low : 1.8V)

VHALF

phia_abb

External Voltage Reference (1.65V)

VTOP

phia_abb

Voltage Reference Top (3.3V)

VBOT

phia_abb

Voltage Reference Bottom (0.0V)

VRT

phia_abb

Internal Voltage Reference Top (2.65V)

VRB

phia_abb

Internal Voltage Reference Bottom (0.65V)

VOUT

phoa_abb

Analog Voltage Output

AVDD33D

vdd3t_abb

Analog Power (+3.3V)

AVSS33D

vss3t_abb

Analog Ground (0.0V)

AVDD33A

vdd3t_abb

Digital Power (+3.3V)

AVSS33A

vss3t_abb

Digital Ground (0.0V)

AVBB

vbb3t_abb

Analog Sub Bias (0.0V)

AVDD18D

vdd1t_abb

Digital Power (+1.8V)

I/O Type Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bi-direction
-- DB: Digital Bi-direction
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground

DAC1264X_RA

0.18

m 3.3V 10-BIT 2MSPS DAC

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD (AVDD33A,AVDD33D)

4.5

Analog Output Voltage

VOUT

AVSS33A to AVDD33A

Digital Input Voltage

D[9:0]

AVSS33D to AVDD18D

Reference Voltage

VRT

VRB

AVDD33A

AVSS33A

Operating Temperature Range

Topr

0 to 70

NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.

Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value
is applied with the other values kept within the following operating conditions and function operation under any of these
conditions is not implied.

2. All voltages are measured with respect to VSS (AVSS33A or AVSS33D or AVBB) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k

resistor (Human body model)

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply Voltage

AVDD33A - AVSS33A

AVDD33D - AVSS33D

3.15

3.3

3.45

AVDD18D - AVSS33D

1.65

1.8

1.95

Supply Voltage Difference

AVDD33A - AVDD33D

-0.1

0.0

0.1

Reference Voltage

VRT

VRB

0.0

2.65

0.65

3.3

Digital Input 'Low' Voltage

Digital Input 'High' Voltage

VIL

VIH

0.7

VDD

0.3

VDD

Operating Temperature

Topr

NOTES:
1. It is strongly recommended that to avoid power latch-up all the supply pins(AVDD33A,AVDD33D) be driven from the

same source.

2. VDD

AVDD18D

0.18

m 3.3V 10-BIT 2MSPS DAC

DAC1264X_RA

DC ELECTRICAL CHARACTERISTICS

(Converter Specifications: AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V, AVDD18D=1.8V

PWDNB=High, Top=25

C, VRT=2.65V, VRB=0.65V unless otherwise specified.)

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Resolution

Bit

Bits

Differential Linearity Error

DLE

-1.0

0.2

+1.0

LSB

Integral Linearity Error

ILE

-2.5

1.6

+2.5

LSB

Zero Scale Error

(1)

ZSE

-15

+15

VTOP=3.3V , VRB=0.0V

Full Scale Voltage Error

(2)

FSE

-15

+15

(VRT and VRB are floated.)

Maximum Output Voltage

MAX

2.633 2.648 2.663

MAX

= VOUT(D[9:0]=High)

LSB Size

LSB

1.93

1.953

1.97

LSB

= (Vo

MAX

- VOUT(D[9:0]=Low))

/1023

NOTES:
1. V

ZSE

= VOUT(D[9:0] = Low) - VRB

2. V

FSE

= VOUT(D[9:0] = High) - {(VRT-VRB)

1023/1024 + VRB}

AC ELECTRICAL CHARACTERISTICS

(Converter Specifications : AVDD33D=AVDD33A=3.3V, AVSS33D=AVSS33A=AVBB=0V, AVDD18D=1.8V,

load cap=25pF load resistance=5k

, Top=25

C, VRT=2.65V, VRB=0.65V unless otherwise specified.)

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Supply Current

(Average Current)

Ivdd1

Ivdd1 = I

AVDD33A

+ I

AVDD33D

Data Input: All Low or All High

Supply Current

(Power Down Mode)

Ivdd2

Ivdd2 = I

AVDD33A

+ I

AVDD33D

Data Rate = 2MHz

PWDNB=LOW

Reference Current

VRT

0.75

Analog Output Delay

Data Rate = 2MHz

Data : All LOW

All HIGH

Analog Output Rise Time

100

Data Rate = 2MHz

Data : All LOW

All HIGH

Analog Output Fall Time

103

176

Data Rate = 2MHz

Data : All HIGH

All LOW

Analog Output
Settling Time

360

400

420

Data Rate = 2MHz

Data : All LOW ® All HIGH

Power Down On Time

Ton

PWDNB : HIGH

LOW

Power Down Off Time

Toff

300

PWDNB : LOW

HIGH

Glitch Energy

GLE

-0.1

0.1

nsV

Data Rate = 2MHz

Data : 0111111111

1111111111

Signal-to-Noise and

SNDR

-48

-56

-58

Data Rate = 2MHz

0.18

m 3.3V 10-BIT 2MSPS DAC

DAC1264X_RA

TIMING DIAGRAM

DATA

PWDNB

VOUT

Ton

50%

VOUT

50%

0000000000

1111111111

10%

0000000000

90%

1111111111

0000000000

DATA

VOUT

50%

0000000000

90%

1111111111

0000000000

DATA

VOUT

0.5LSB

Toff

50%

0.5LSB

0.0V

NOTES:
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within

1/2 LSB.

3. Output rise/fall time measured between the 10% and 90% points of full scale transition.

FUNCTIONAL DESCRIPTION

1. The dac1264x_ra has a 10bit R-string block, two decoders, and an OP amp.
2. The digital outputs of two decoders decide the voltage level of R-string block.

Rstring

VRT-VRB

n=0

x D[n]) + VRB

3. The voltages of VRT and VRB are internally generated by resistor strings.

(VTOP = 3.3V, VBOT = 0.0V then VRT = 2.65V, VRB = 0.65V)

For more accurate operations, you had better connect VRT and VRB with voltage sources instead of

connecting VTOP and VBOT with voltage sources. (VRT = 2.65V, VRB = 0.65V)

4. The VOUT pin is dependent of digital input values.
5. Power Down Mode reduces only analog currents (I

AVDD33A

) and reference current (I

VRT

) is always dissipated.

DAC1264X_RA

0.18

m 3.3V 10-BIT 2MSPS DAC

CORE EVALUATION GUIDE

VOUT

VHALF

D[9:0]

PWDNB

dac1264x_ra

VTOP

VBOT

VRT

VRB

VOUT

AVDD18D

AVBB

AVDD33A

AVSS33D

AVDD33D

AVSS33A

3.3V GND 3.3V GND

1.8V

1.65V 3.3V

GND 0.0V

GND

MUX

Test Path

Host

DSP

Core

Location

Description

10uF Tantalum Capacitor

0.1uF Ceramic Capacitor

TESTABLITITY

Whether you use MUX or the internal logic for testability, it is required to be able to select values of digital inputs

(D[9:0]).

See above figure. Only if it is, you can check the main function. (Linearity)

For more accurate operations, you had better connect VRT and VRB with voltage sources instead of connecting

VTOP and VBOT with voltage sources.

(VRT = 2.65V , VRB = 0.65V)

0.18

m 3.3V 10-BIT 2MSPS DAC

DAC1264X_RA

PHANTOM CELL INFORMATION

dac1264x_ra

AVDD33A
VASS33A
AVBB

VHALF

AVDD33D
VASS33D
AVDD18D

D[9]

D[8]

D[7]

D[6]

D[5]

D[4] D[3]

D[2]

D[1

D[0]

VRB

VBOT

VTOP

VRT

PWDNB

VOUT

Pin Name

Property

Pin Usage

Pin Layout Guide

D[9:0]

Internal/External 1. Digital Input Signal lines must have same length to reduce

PWDNB

Internal/External propagation delay.

VRT

Internal/External 1. Voltage reference lines (VRT/VRB and VTOP/VBOT)

must be wide metal to reduce voltage drop of metal lines.

VRB

Internal/External 2. If you use VRT and VRB, VTOP and VBOT may be

disconnected and vice versa.

VTOP

External

3. VOUT signal should not be crossed by any signals and

should not run next to digital signals to minimize capacitive

VBOT

External

coupling between the two signals.

VOUT

Internal/External

AVDD33A

External

1. It is recommended that you use thick analog power metal.

AVSS33A

External

When connected to PAD, the path should be kept as short

AVDD33D

External

as possible.

AVSS33D

External

2. Digital power and analog power are separately used.

AVBB

External

AVDD18D

External

NOTES:
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and P+ active to remove
the

substrate and coupling noise. In that case, the power metal should be connected to PAD directly.

2. The Bulk power is used to reduce the influence of substrate noise.

DAC1264X_RA

0.18

m 3.3V 10-BIT 2MSPS DAC

FEEDBACK REQUEST

We appreciate your interest in out products. If you have further questions, please specify in the attached form.

Thank you very much.

DC / AC Electrical Characteristic

Characteristics

Min

Typ

Max

Unit

Remarks

Supply Voltage

Power dissipation

Resolution

Bits

Analog Output Voltage

Operating Temperature

Output Load Capacitor

Output Load Resistor

Integral Non-Linearity Error

LSB

Differential Non-Linearity Error

LSB

Maximum Conversion Rate

MHz

Voltage Output DAC

Characteristics

Min

Typ

Max

Unit

Remarks

Reference Voltage TOP

BOTTOM

Analog Output Voltage Range

Digital Input Format

Binary Code or 2's Complement Code

Current Output DAC

Characteristics

Min

Typ

Max

Unit

Remarks

Analog Output Maximum Current

Analog Output Maximum Signal

Frequency

kHz

Reference Voltage

External Resistor for Current

Setting(RSET)

Pipeline Delay

sec

-- Do you want to Power down mode?
-- Do you want to Internal Reference Voltage(BGR)?
-- Which do you want to serial input data type or parallel input data type?
-- Do you need 3.3V and 5V power supply in your system?

0.18

m 3.3V 10-BIT 2MSPS DAC

DAC1264X_RA

HISTORY CARD

Version

Date

Modified Items

Comments

Ver 1.0

00.09

Preliminary Version

Ver 1.1

01.03.15

Page 1 : block diagram is modified (AVSS33A

AVSS33D)

Ver 1.2

01.03.28

Version Updated

page 8 :

(Output Load Resistor)

Ver 1.3

01.04.12

Version Updated

page 8 : Interal

Internal

Ver 1.4

01.10.05

Version Updated

1.8V pin for digital input is added. (block diagram, symbol,

spec..etc)

Core layout guide is added.

Ver 1.5

01.11.02

Version Updated

page 7 : Layout guide is modified.

Ver 1.6

02.05.13

Version Updated
page 3 : Absolute Maximum Rating is modified.
page 4 : Test result is added.
page 5 : Functional description is modified.
page 6 : Diagram is modified.
page 8 : Diagram is modified.
page 9 : Question is modified.

Ver1.7

03.03.06

Version Updated

Page 1 : Application is modified.

Page 4 : 1111111111

1000000000

Page 8 : Diagram is modified.

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