K4S161622D-TI/E

CMOS SDRAM

Rev 1.2 Jan '03

The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG

s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.

3.3V power supply

· LVTTL compatible with multiplexed address
· Dual banks operation
· MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
· All inputs are sampled at the positive going edge of the system
clock
·

Burst Read Single-bit Write operation

DQM for masking

Auto & self refresh

· 15.6us refresh duty cycle (2K/32ms)

· Extended temperature range : -25

C to +85

· Industrial temperature range : -40

C to +85

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

512K x 16Bit x 2 Banks Synchronous DRAM

ORDERING INFORMATION

K4S161622D-TI* : Industrial, Normal
K4S161622D-TE* : Extended, Normal

Part NO.

MAX Freq.

Interface Package

K4S161622D-TI/E50

200MHz

LVTTL

TSOP(II)

K4S161622D-TI/E55

183MHz

K4S161622D-TI/E60

166MHz

K4S161622D-TI/E70

143MHz

K4S161622D-TI/E80

125MHz

K4S161622D-TI/E10

100MHz

* Samsung Electronics reserves the right to change products or specification without notice.

Bank Select

Data Input Register

512K x 16

Sen

s
e AMP

Output Buf

f
er

I/O Cont

rol

Column Decoder

Latency & Burst Length

Programming Register

Address Regi

ster

Row

Buf

f
er

Refresh Counter

Ro
w Decoder

Co
l. Buf

f
er

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

RAS

CAS

L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

Timing Register

K4S161622D-TI/E

CMOS SDRAM

Rev 1.2 Jan '03

DQ0
DQ1

SSQ

DQ2
DQ3

DDQ

DQ4
DQ5

SSQ

DQ6
DQ7

DDQ

LDQM

CAS
RAS

A10/AP

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

PIN CONFIGURATION (TOP VIEW)

DQ15
DQ14
V

SSQ

DQ13
DQ12
V

DDQ

DQ11
DQ10
V

SSQ

DQ9
DQ8
V

DDQ

N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

~ A

/AP

Address

Row / column addresses are multiplexed on the same pins.
Row address : RA

~ RA

, column address : CA

~ CA

Bank Select Address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write Enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

L(U)DQM

Data Input/Output Mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

Power Supply/Ground

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Data Output Power/Ground

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

N.C/RFU

No Connection/
Reserved for Future Use

This pin is recommended to be left No Connection on the device.

K4S161622D-TI/E

CMOS SDRAM

Rev 1.2 Jan '03

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, Extended T

= -25 to +85

C , Industrial T

= -40 to +85

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0

3.3

3.6

Input logic high votlage

2.0

3.0

DDQ

+0.3

Input logic low voltage

-0.3

0.8

Output logic high voltage

2.4

= -2mA

Output logic low voltage

0.4

= 2mA

Input leakage current

-10

Note :

CAPACITANCE

= 3.3V, T

= 23

C, f = 1MHz, V

REF

=1.4V

200

mV)

Pin

Symbol

Min

Max

Unit

Clock

CLK

RAS, CAS, WE, CS, CKE, L(U)DQM

Address

ADD

~ DQ

OUT

1. V

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between V

and V

DC1

0.1 + 0.01

Decoupling Capacitance between V

DDQ

and V

SSQ

DC2

0.1 + 0.01

1. V

and V

DDQ

pins are separated each other.

All V

pins are connected in chip. All V

DDQ

pins are connected in chip.

2. V

and V

SSQ

pins are separated each other

All V

pins are connected in chip. All V

SSQ

pins are connected in chip.

Note :

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