1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 1 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
Document Title
1Mx36 & 2Mx18-Bit Pipelined NtRAM
TM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
1.0
1.1
2.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
History
1. Initial document.
1. Add 165FBGA package
1. Update JTAG scan order
2. Speed bin merge.
From K7N3236(18)09M to K7N3236(18)01M
3. AC parameter change.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20
1. Change pin out for 165FBGA
- x18/x36 ; 11B => from A to NC , 2R ==> from NC to A
1. Insert pin at JTAG scan order of 165FBGA in connection with
pin out change
- x18/x36 ; insert Pin ID of 2R to BIT number of 69
1. Add Icc, Isb, Isb1 and Isb2 values.
1. Final datasheet release.
1. Change the Stand-by current (Isb)
Before After
Isb - 25 : 120 170
- 22 : 110 160
- 20 : 100 150
- 16 : 90 140
- 15 : 90 140
- 13 : 90 140
Isb1 : 90 110
Isb2 : 80 100
1. Delete the 119BGA package
2. Delete the 225MHz and 150MHz speed bin
Draft Date
May. 10. 2001
Aug. 29. 2001
Dec. 31. 2001
Feb. 14. 2002
Apr. 20. 2002
May. 10. 2002
Sep. 26. 2002
Oct. 17, 2003
Nov. 18, 2003
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 2 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
32Mb NtRAM(Flow Through / Pipelined) Ordering Informa
tion
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
PKG
Temp
2Mx18
K7M321825M-QC75
FlowThrough
3.3
7.5ns
Q:100TQFP
F:165FBGA
C
(Commercial
Temperature
Range)
K7N321801M-Q(F)C25/20/16/13
Pipelined
3.3
250/200/167/133MHz
K7N321845M-Q(F)C25/20/16/13
Pipelined
2.5
250/200/167/133MHz
1Mx36
K7M323625M-QC75
FlowThrough
3.3
7.5ns
K7N323601M-Q(F)C25/20/16/13
Pipelined
3.3
250/200/167/133MHz
K7N323645M-Q(F)C25/20/16/13
Pipelined
2.5
250/200/167/133MHz
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 3 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
1Mx36 & 2Mx18-Bit Pipelined NtRAM
TM
The K7N323601M and K7N321801M are 37,748,736-bits
Synchronous Static SRAMs.
The N tRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N323601M and K7N321801M are implemented with
SAMSUNG
s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no da ta-
contention .
A interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
100-TQFP-1420A .
165FBGA(11x15 ball aray) with body size of 15mmx17mm.
FAST ACCESS TIMES
PARAMETER
Symbol -25
-20
-16
-13
Unit
Cycle Time
tCYC
4.0
5.0
6.0
7.5
ns
Clock Access Time
tCD
2.6
3.2
3.5
4.2
ns
Output Enable Access Time
tOE
2.6
3.2
3.5
4.2
ns
W E
B W
x
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or
DQa
0
~ DQb
8
ADDRESS
ADDRESS
REGISTER
C
O
N
T
R
O
L
L
O
G
I
C
A
0
~A
1
36 or 18
DQPa ~ DQPd
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
O
N
T
R
O
L
R
E
G
I
S
T
E
R
K
A [0:19]or
A [0:20]
LBO
A
2
~A
19
or
A
2
~A
20
A
0
~A
1
(x=a,b,c,d or a,b)
1Mx36, 2Mx18
MEMORY
ARRAY
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 4 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
A
6
A
7
C
S
1
C
S
2
B
W
d
B
W
c
B
W
b
B
W
a
C
S
2
V
D
D
V
S
S
C
L
K
W
E
C
K
E
O
E
A
D
V
A
1
8
A
1
7
A
8
8
1
A
9
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
A
1
6
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
1
9
N
.
C
.
V
D
D
V
S
S
N
.
C
.
N
.
C
.
A
0
A
1
A
2
A
3
A
4
A
5
3
1
L
B
O
PIN NAME
Note :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
19
ADV
W E
CLK
CKE
CS
1
CS
2
CS
2
B Wx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,43,
44,45,46,47,48,49,50,
81,82,83,84,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
38,39,42
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7N323601M(1Mx36)
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 5 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
A
6
A
7
C
S
1
C
S
2
B
W
b
B
W
a
C
S
2
V
D
D
V
S
S
C
L
K
W
E
C
K
E
O
E
A
D
V
A
1
9
A
1
8
A
8
8
1
A
9
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
A
1
7
A
1
6
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
2
0
N
.
C
.
V
D
D
V
S
S
N
.
C
.
N
.
C
.
A
0
A
1
A
2
A
3
A
4
A
5
3
1
L
B
O
K7N321801M(2Mx18)
N
.
C
.
N
.
C
.
PIN NAME
N
OTE
:
A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
20
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BW x(x=a,b)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50,
80,81,82,83,84,99,100
85
88
89
87
98
97
92
93,94
86
64
31
V
DD
V
SS
N.C.
DQa
0
~a
8
DQb
0
~b
8
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 6 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
165-PIN FBGA PACKAGE CONFIGURATIONS
(TOP VIEW)
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
(x=a,b,c,d)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
V
DD
V
SS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
V
DDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
K7N323601M(1Mx36)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CS 1
BW c
BWb
CS2
CKE
ADV
A
A
NC
B
NC
A
CS2
BWd
BWa
CLK
WE
OE
A
A
NC
C
DQPc
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPb
D
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
E
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
F
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
G
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
H
NC
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
J
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
K
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
L
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
M
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
N
DQPd
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
DQPa
P
NC
NC
A
A
TDI
A
1
*
TDO
A
A
A
NC
R
LBO
A
A
A
TMS
A
0
*
TCK
A
A
A
A
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 7 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
(x=a,b)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
V
DD
V
SS
N.C.
DQa
DQb
DQPa, Pb
V
DDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
165-PIN FBGA PACKAGE CONFIGURATIONS
(TOP VIEW)
K7N321801M(2Mx18)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CS 1
BWb
NC
CS2
CKE
ADV
A
A
A
B
NC
A
CS2
NC
BWa
CLK
WE
OE
A
A
NC
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPa
D
NC
DQb
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQa
E
NC
DQb
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQa
F
NC
DQb
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQa
G
NC
DQb
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQa
H
NC
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
J
DQb
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
NC
K
DQb
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
NC
L
DQb
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
NC
M
DQb
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
NC
N
DQPb
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
NC
P
NC
NC
A
A
TDI
A
1
*
TDO
A
A
A
NC
R
LBO
A
A
A
TMS
A
0
*
TCK
A
A
A
A
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 8 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
FUNCTION DESCRIPTION
The K7N323601M and K7N321801M are NtRAM
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAM
TM
latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS
1
, CS
2
, CS
2
)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS
1
, CS
2
, CS
2
) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. B W[d:a] can be used for byte write operation. The pipe-
lined NtRAM
TM
uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE
(Linear Burst, LBO=Low)
Note
: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 9 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
STATE DIAGRAM FOR NtRAM
TM
BEGIN
WRITE
BURST
WRITE
BEGIN
READ
WRITE
DS
REA
D
BURST
READ
DS
WR
ITE
DS
READ
DS
RE
AD
D
S
W
RI
TE
B
U
R
S
T
DESELECT
B
U
R
S
T
R
EA
D
B
U
R
S
T
W
R
IT
E
READ
WRITE
BURST
BURST
Notes :
1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
COMMAND
ACTION
DS
DESELECT
READ
BEGIN READ
WRITE
BEGIN WRITE
BURST
BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 10 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
SYNCHRONOUS TRUTH TABLE
Notes :
1. X means "Don
t Care". 2. The rising edge of clock is symbolized by (
).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS
1
CS
2
CS
2
ADV
WE
BWx
O E
CKE
CLK
ADDRESS ACCESSED
Operation
H
X
X
L
X
X
X
L
N/A
Not Selected
X
L
X
L
X
X
X
L
N/A
Not Selected
X
X
H
L
X
X
X
L
N/A
Not Selected
X
X
X
H
X
X
X
L
N/A
Not Selected Continue
L
H
L
L
H
X
L
L
External Address
Begin Burst Read Cycle
X
X
X
H
X
X
L
L
Next Address
Continue Burst Read Cycle
L
H
L
L
H
X
H
L
External Address
NOP/Dummy Read
X
X
X
H
X
X
H
L
Next Address
Dummy Read
L
H
L
L
L
L
X
L
External Address
Begin Burst Write Cycle
X
X
X
H
X
L
X
L
Next Address
Continue Burst Write Cycle
L
H
L
L
L
H
X
L
N/A
NOP/Write Abort
X
X
X
H
X
H
X
L
Next Address
Write Abort
X
X
X
X
X
X
X
H
Current Address
Ignore Clock
WRITE TRUTH TABLE
(x36)
Notes :
1. X means "Don
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
).
WE
BWa
BWb
BW c
BW d
OPERATION
H
X
X
X
X
READ
L
L
H
H
H
WRITE BYTE a
L
H
L
H
H
WRITE BYTE b
L
H
H
L
H
WRITE BYTE c
L
H
H
H
L
WRITE BYTE d
L
L
L
L
L
WRITE ALL BYTEs
L
H
H
H
H
WRITE ABORT/NOP
TRUTH TABLES
WRITE TRUTH TABLE
(x18)
Notes :
1. X means "Don
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
).
WE
BWa
BWb
OPERATION
H
X
X
READ
L
L
H
WRITE BYTE a
L
H
L
WRITE BYTE b
L
L
L
WRITE ALL BYTEs
L
H
H
WRITE ABORT/NOP
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 11 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
ASYNCHRONOUS TRUTH TABLE
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don
t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
*Note :
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V
DD
Supply Relative to V
SS
V
DD
-0.3 to 4.6
V
Voltage on Any Other Pin Relative to V
SS
V
IN
-0.3 to V
DD
+0.3
V
Power Dissipation
P
D
1.6
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
T
OPR
0 to 70
C
Storage Temperature Range Under Bias
T
BIAS
-10 to 85
C
OPERATING CONDITIONS at 3.3V I/O
(0
C
T
A
70
C)
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.465
V
V
DDQ
3.135
3.3
3.465
V
Ground
V
SS
0
0
0
V
CAPACITANCE*
(T
A
=25
C, f=1MHz)
*Notes :
Sampled not 100% tested.
Parameter
Symbol
Test Condition
TYP
Max
Unit
Input Capacitance
C
IN
V
IN
=0V
-
5
pF
Output Capacitance
C
OUT
V
OUT
=0V
-
7
pF
OPERATING CONDITIONS at 2.5V I/O
(0
C
T
A
70
C)
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.465
V
V
DDQ
2.375
2.5
2.9
V
Ground
V
SS
0
0
0
V
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 12 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
DC ELECTRICAL CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0
C to +70
C)
Notes :
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.3V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
Input Leakage Current(except ZZ)
I
IL
V
DD
=Max ; V
IN
=V
SS
to V
DD
-2
+2
A
Output Leakage Current
I
OL
Output Disabled, V
out
=V
SS
to V
DDQ
-2
+2
A
Operating Current
I
CC
Device Selected, I
OUT
=0mA,
ZZ
V
IL ,
Cycle Time
t
CYC
Min
-25
-
460
mA
1,2
-20
-
410
-16
-
360
-13
-
310
Standby Current
I
SB
Device deselected, I
OUT
=0mA,
ZZ
V
IL
, f=Max, All Inputs
0.2V or
V
DD
-0.2V
-25
-
170
mA
-20
-
150
-16
-
140
-13
-
140
I
SB1
Device deselected, I
OUT
=0mA,
ZZ
0.2V,
f=0, All Inputs=fixed (V
DD
-0.2V or
-
110
mA
I
SB2
Device deselected, I
OUT
=0mA,
ZZ
V
DD
-0.2V, f=Max, All Inputs
V
IL
or
V
IH
-
100
mA
Output Low Voltage(3.3V I/O)
V
OL
I
OL
=8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
V
OH
I
OH
=-4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
V
OL
I
OL
=1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
V
OH
I
OH
=-1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
V
IL
-0.3*
0.8
V
Input High Voltage(3.3V I/O)
V
IH
2.0
V
DD
+0.3**
V
3
Input Low Voltage(2.5V I/O)
V
IL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
V
IH
1.7
V
DD
+0.3**
V
3
(V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=3.3V+0.165/-0.165V or V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=2.5V+0.4V/-0.125V, T
A
=0to70
C)
TEST CONDITIONS
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3.0V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
V
DDQ
/2
Output Load
See Fig. 1
V
SS
V
IH
V
SS-
1.0V
20% t
CYC
(MIN)
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 13 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
AC TIMING CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0 to 70
C)
Notes :
1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature t
LZC
is more than t
HZC.
The specs as shown do not imply bus contention because t
LZC
is a Min. parameter that is worst case at totally different test conditions
(0
C,3.465V) than t
H Z C
, which is a Max. parameter(worst case at 70
C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER
SYMBOL
-25
-20
-16
-13
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Cycle Time
t
CYC
4.0
-
5.0
-
6.0
-
7.5
-
ns
Clock Access Time
t
CD
-
2.6
-
3.2
-
3.5
-
4.2
ns
Output Enable to Data Valid
t
OE
-
2.6
-
3.2
-
3.5
-
4.2
ns
Clock High to Output Low-Z
t
LZC
1.5
-
1.5
-
1.5
-
1.5
-
ns
Output Hold from Clock High
t
OH
1.5
-
1.5
-
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
-
2.6
-
3.0
-
3.0
-
3.5
ns
Clock High to Output High-Z
t
HZC
-
2.6
-
3.0
-
3.0
-
3.5
ns
Clock High Pulse Width
t
CH
1.7
-
2.0
-
2.2
-
3.0
-
ns
Clock Low Pulse Width
t
CL
1.7
-
2.0
-
2.2
-
3.0
-
ns
Address Setup to Clock High
t
AS
1.2
-
1.4
-
1.5
-
1.5
-
ns
CKE Setup to Clock High
t
CES
1.2
-
1.4
-
1.5
-
1.5
-
ns
Data Setup to Clock High
t
DS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Write Setup to Clock High (WE, BW
X
)
t
WS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
t
ADVS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
t
CSS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Address Hold from Clock High
t
AH
0.3
-
0.4
-
0.5
-
0.5
-
ns
CKE Hold from Clock High
t
CEH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Data Hold from Clock High
t
DH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Write Hold from Clock High (WE , BW
X
)
t
WH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
t
ADVH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.3
-
0.4
-
0.5
-
0.5
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
2
-
2
-
cycle
Output Load(B),
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
353
/
1538
5pF*
+3.3V for 3.3V I/O
319
/
1667
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50
RL=50
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
/+2.5V for 2.5V I/O
30pF*
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 14 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during t
PUS
, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
Current during SLEEP MODE
ZZ
V
IH
I
SB2
60
mA
ZZ active to input ignored
t
PDS
2
cycle
ZZ inactive to input sampled
t
PUS
2
cycle
ZZ active to SLEEP current
t
ZZI
2
cycle
ZZ inactive to exit SLEEP current
t
RZZI
0
K
t
PDS
ZZ setup cycle
t
RZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
t
ZZI
t
PUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON
T CARE
I
SB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 15 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V
SS
to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V
DD
through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
0
1
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE
:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to V
SS
when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0
Instruction
TDO Output
Notes
0
0
0 EXTEST
Boundary Scan Register
1
0
0
1 IDCODE
Identification Register
3
0
1
0 SAMPLE-Z
Boundary Scan Register
2
0
1
1 BYPASS
Bypass Register
4
1
0
0 SAMPLE
Boundary Scan Register
5
1
0
1 RESERVED Do Not Use
6
1
1
0 BYPASS
Bypass Register
4
1
1
1 BYPASS
Bypass Register
4
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 16 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
Note
: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don
t care).
BIT
PIN ID(x18)
PIN ID(x36)
40
6A
6A
41
5B
5B
42
5A
5A
43
4A
4A
44
4B
4B
45
3B
3B
46
3A
3A
47
2A
2A
48
2B
2B
49
1B
1B
50
1A
1A
51
1C
1C
52
1D
1D
53
1E
1E
54
1F
1F
55
1G
1G
56
2D
2D
57
2E
2E
58
2F
2F
59
2G
2G
60
1J
1J
61
1K
1K
62
1L
1L
63
1M
1M
64
1N
2J
65
2K
2K
66
2L
2L
67
2M
2M
68
2J
1N
69
2R
2R
70
1R
1R
71
3P
3P
72
3R
3R
73
4R
4R
74
4P
4P
75
6P
6P
76
6R
6R
BIT
PIN ID(x18)
PIN ID(x36)
1
6N
6N
2
8P
8P
3
8R
8R
4
9R
9R
5
9P
9P
6
10P
10P
7
10R
10R
8
11R
11R
9
11P
11P
10
11H
11H
11
11N
11N
12
11M
11M
13
11L
11L
14
11K
11K
15
11J
11J
16
10M
10M
17
10L
10L
18
10K
10K
19
10J
10J
20
11G
11G
21
11F
11F
22
11E
11E
23
11D
11D
24
11C
10G
25
10F
10F
26
10E
10E
27
10D
10D
28
10G
11C
29
11A
11A
30
11B
11B
31
10A
10A
32
10B
10B
33
9A
9A
34
9B
9B
35
8A
8A
36
8B
8B
37
7A
7A
38
7B
7B
39
6B
6B
BOUNDARY SCAN EXIT ORDER
ID REGISTER DEFINITION
Part
Revision Number
(31:28)
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit(0)
1Mx36
0000
01000 00100
XXXXXX
00001001110
1
2Mx18
0000
01001 00011
XXXXXX
00001001110
1
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
Boundary Scan
1Mx36
3 bits
1 bits
32 bits
76 bits
2Mx18
3 bits
1 bits
32 bits
76 bits
SCAN INFORMATION (165 FBGA )
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 17 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
JTAG DC OPERATING CONDITIONS
NOTE
: The input level of SRAM pin is to follow the SRAM DC specification
.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V
DD
3.135
3.3
3.465
V
Input High Level ( 3.3V I/O / 2.5V I/O )
V
IH
2.0 / 1.7
-
V
DD
+0.3
V
Input Low Level ( 3.3V I/O / 2.5V I/O )
V
IL
-0.3
-
0.8 / 0.7
V
Output High Voltage( 3.3V I/O / 2.5V I/O )
V
OH
2.4 / 2.0
-
-
V
Output Low Voltage( 3.3V I/O / 2.5V I/O )
V
OL
-
-
0.4 / 0.4
V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
Note
TCK Cycle Time
t
CHCH
50
-
ns
TCK High Pulse Width
t
CHCL
20
-
ns
TCK Low Pulse Width
t
CLCH
20
-
ns
TMS Input Setup Time
t
MVCH
5
-
ns
TMS Input Hold Time
t
CHMX
5
-
ns
TDI Input Setup Time
t
DVCH
5
-
ns
TDI Input Hold Time
t
CHDX
5
-
ns
SRAM Input Setup Time
t
SVCH
5
-
ns
SRAM Input Hold Time
t
CHSX
5
-
ns
Clock Low to Output Valid
t
CLQV
0
10
ns
JTAG AC TEST CONDITIONS
Parameter
Symbol
Min
Unit
Note
Input High/Low Level( 3.3V I/O , 2.5V I/O )
V
IH
/V
IL
3.0/0 , 2.5/0
V
Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )
TR/TF
1.0/1.0 , 1.0/1.0
ns
Input and Output Timing Reference Level
V
DDQ
/2
V
TCK
TMS
TDI
PI
t
CHCH
t
MVCH
t
CHMX
t
CHCL
t
CLCH
t
DVCH
t
CHDX
t
CLQV
TDO
(SRAM)
t
SVCH
t
CHSX
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 18 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
C
l
o
c
k
C
K
E
A
d
d
r
e
s
s
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
O
u
t
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
R
E
A
D
C
Y
C
L
E
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
W
E
=
L
,
a
n
d
B
W
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
t
C
H
t
C
L
t
C
E
S
t
C
E
H
t
A
S
t
A
H
A
1
A
2
A
3
t
W
S
t
W
H
t
C
S
S
t
C
S
H
t
O
E
t
H
Z
O
E
t
L
Z
O
E
t
C
D
t
O
H
t
H
Z
C
Q
3
-
4
Q
3
-
3
Q
3
-
2
Q
3
-
1
Q
2
-
4
Q
2
-
3
Q
2
-
2
Q
2
-
1
Q
1
-
1
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
t
A
D
V
S
t
A
D
V
H
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 19 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
W
R
T
E
C
Y
C
L
E
C
l
o
c
k
A
d
d
r
e
s
s
W
R
I
T
E
C
S
A
D
V
D
a
t
a
I
n
t
C
H
t
C
L
A
2
A
3
D
2
-
1
D
1
-
1
D
2
-
2
D
2
-
3
D
2
-
4
D
3
-
1
D
3
-
2
D
3
-
3
O
E
D
a
t
a
O
u
t
t
D
S
t
D
H
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
C
K
E
A
1
D
3
-
4
t
C
E
S
t
C
E
H
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
W
E
=
L
,
a
n
d
B
W
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
Q
0
-
4
t
H
Z
O
E
Q
0
-
3
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 20 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
S
I
N
G
L
E
R
E
A
D
/
W
R
I
T
E
C
l
o
c
k
A
d
d
r
e
s
s
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
I
n
t
C
H
t
C
L
t
D
S
t
D
H
D
a
t
a
O
u
t
A
2
A
4
A
5
D
2
t
O
E
t
L
Z
O
E
Q
1
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
C
K
E
t
C
E
S
t
C
E
H
A
1
A
3
A
7
A
6
Q
3
Q
4
Q
7
Q
6
D
5
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
W
E
=
L
,
a
n
d
B
W
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
A
9
A
8
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 21 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
C
K
E
O
P
E
R
A
T
I
O
N
C
l
o
c
k
A
d
d
r
e
s
s
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
I
n
t
C
H
t
C
L
D
a
t
a
O
u
t
A
1
A
2
A
3
A
4
A
5
t
C
E
S
t
C
E
H
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
C
K
E
t
D
S
t
D
H
D
2
Q
4
Q
1
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
W
E
=
L
,
a
n
d
B
W
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
t
C
D
t
L
Z
C
t
H
Z
C
Q
3
A
6
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 22 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
C
S
O
P
E
R
A
T
I
O
N
C
l
o
c
k
A
d
d
r
e
s
s
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
I
n
t
C
H
t
C
L
D
a
t
a
O
u
t
A
1
A
2
A
3
A
4
A
5
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
C
K
E
D
5
Q
4
t
C
E
S
t
C
E
H
Q
1
Q
2
t
O
E
t
L
Z
O
E
D
3
t
C
D
t
L
Z
C
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
W
E
=
L
,
a
n
d
B
W
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
t
H
Z
C
t
D
H
t
D
S
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 23 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
PACKAGE DIMENSIONS
0.10 MAX
0~8
22.00
0.30
20.00
0.20
16.00
0.30
14.00
0.20
1.40
0.10
1.60 MAX
0.05 MIN
(0.58)
0.50
0.10
#1
(0.83)
0.50
0.10
100-TQFP-1420A
0.65
0.30
0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
1Mx36 & 2Mx18 Pipelined NtRAM
TM
- 24 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
165 FBGA PACKAGE DIMENSIONS
C
Side View
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
F
A
H
G
B
Bottom View
Top View
A
B
D
E
E
Symbol
Value
Units
Note
Symbol
Value
Units
Note
A
17
0.1
mm
E
1.0
mm
B
15
0.1
mm
F
14.0
mm
C
1.3
0.1
mm
G
10.0
mm
D
0.35
0.05
mm
H
0.5
0.05
mm
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