K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
1
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.0
0.1
0.2
Remark
Preliminary
Final
History
1. Initial issue
- Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection).
So, /SE pin is don't-cared regardless of external logic input level and is
fixed as low internally.
1. Changed plane address in Copy-Back Program
-
A14
, the plane address, of source and destination page address must be
the same. =>
A14 and A25
, the plane address, of source and destination
page address must be the same.
1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Draft Date
Dec. 6th 2000
Dec. 28th 2000
Jan. 17th 2001
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
2
64M x 8 Bit NAND Flash Memory
The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200
s and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 60ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9K1208U0A
s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requir-
ing non-volatility.
GENERAL DESCRIPTION
FEATURES
Voltage Supply : 2.7V~3.6V
Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
528-Byte Page Read Operation
- Random Access : 10
s(Max.)
- Serial Page Access : 60ns(Min.)
Fast Write Cycle Time
- Program time : 200
s(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Package :
- K9K1208U0A-YCB0/YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
PIN CONFIGURATION
NOTE : Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name
Pin Function
I/O
0
~ I/O
7
Data Input/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready/Busy output
V
CC
Power
V
SS
Ground
N.C
No Connection
PIN DESCRIPTION
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
3
512B Byte
16 Byte
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
8
is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3rd Cycle
A
17
A
18
A
19
A
20
A
21
A
22
A
23
A
24
4th Cycle
A
25
*L
*L
*L
*L
*L
*L
*L
V
CC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
V
SS
A
9
- A
25
A
0
- A
7
Command
CE
RE
WE
CLE
WP
I/0 0
I/0 7
V
CC
V
SS
A
8
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
128K Pages
(=4,096 Blocks)
512 Byte
8 bit
16 Byte
1 Block = 32 Pages
= (16K + 512) Byte
I/O 0 ~ I/O 7
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4,096 Blocks
= 528 Mbits
Column Address
Row Address
(Page Address)
Page Register
ALE
512M + 16M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 131072
Y-Gating
Page Register & S/A
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
4
PRODUCT INTRODUCTION
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208U0A.
The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9K1208U0A.
Table 1. COMMAND SETS
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half
register(00h) on the next cycle.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h
(1)
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
5
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
6
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Operating
Current
Sequential Read
I
CC
1
tRC=60ns, CE=V
IL
, I
OUT
=0mA
-
10
20
mA
Program
I
CC
2
-
-
15
25
Erase
I
CC
3
-
-
15
25
Stand-by Current(TTL)
I
SB
1
CE=V
IH
, WP=0V/V
CC
-
-
1
Stand-by Current(CMOS)
I
SB
2
CE=V
CC
-0.2, WP=0V/V
CC
-
10
50
A
Input Leakage Current
I
LI
V
IN
=0 to 3.6V
-
-
10
Output Leakage Current
I
LO
V
OUT
=0 to 3.6V
-
-
10
Input High Voltage
V
IH
-
2.0
-
V
CC
+0.3
V
Input Low Voltage, All inputs
V
IL
-
-0.3
-
0.8
Output High Voltage Level
V
OH
I
OH
=-400
A
2.4
-
-
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
-
0.4
Output Low Current(R/B)
I
OL
(R/B)
V
OL
=0.4V
8
10
-
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K1208U0A-YCB0
:
T
A
=0 to 70
C, K9K1208U0A-YIB0
:
T
A
=-40 to 85
C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
V
CC
2.7
3.3
3.6
V
Supply Voltage
V
SS
0
0
0
V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V
CC,
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN
-0.6 to + 4.6
V
V
CC
-0.6 to + 4.6
Temperature Under Bias
K9K1208U0A-YCB0
T
BIAS
-10 to +125
C
K9K1208U0A-YIB0
-40 to +125
Storage Temperature
T
STG
-65 to +150
C
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
7
VALID BLOCK
NOTE :
1. The
K9K1208U0A
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not try
to access these invalid blocks for program and erase.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
4,026
-
4,096
Blocks
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
2
cycles
Spare Array
-
-
3
cycles
Block Erase Time
t
BERS
-
2
3
ms
CAPACITANCE
(
T
A
=25
C, V
CC
=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
30
pF
Input Capacitance
C
IN
V
IN
=0V
-
30
pF
AC TEST CONDITION
(K9K1208U0A-YCB0 :TA=0 to 70
C, K9K1208U0A-YIB0:TA=-40 to 85
C, VCC=2.7V~3.6V unless otherwise)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
MODE SELECTION
NOTE : 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(4clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(4clock)
L
L
L
H
H
Data Input
L
L
L
H
X
sequential Read & Data Output
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
8
AC Characteristics for Operation
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
t
R
-
10
s
ALE to RE Delay( ID read )
t
AR1
100
-
ns
ALE to RE Delay(Read cycle)
t
AR2
50
-
ns
CE to RE Delay( ID read)
t
CR
100
-
ns
Ready to RE Low
t
RR
20
-
ns
RE Pulse Width
t
RP
30
-
ns
WE High to Busy
t
WB
-
100
ns
Read Cycle Time
t
RC
60
-
ns
RE Access Time
t
REA
-
35
ns
RE High to Output Hi-Z
t
RHZ
15
30
ns
CE High to Output Hi-Z
t
CHZ
-
20
ns
RE High Hold Time
t
REH
25
-
ns
Output Hi-Z to RE Low
t
IR
0
-
ns
Last RE High to Busy(at sequential read)
t
RB
-
100
ns
CE High to Ready(in case of interception by CE at read)
t
CRY
-
50 +tr(R/B)
(1)
ns
CE High Hold Time(at the last serial read)
(2)
t
CEH
100
-
ns
RE Low to Status Output
t
RSTO
-
35
ns
CE Low to Status Output
t
CSTO
-
45
ns
WE High to RE Low
t
WHR
60
-
ns
RE access time(Read ID)
t
READID
-
35
ns
Device Resetting Time(Read/Program/Erase)
t
RST
-
5/10/500
(3)
s
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE setup Time
t
CLS
0
-
ns
CLE Hold Time
t
CLH
10
-
ns
CE setup Time
t
CS
0
-
ns
CE Hold Time
t
CH
10
-
ns
WE Pulse Width
t
WP
25
(1)
-
ns
ALE setup Time
t
ALS
0
-
ns
ALE Hold Time
t
ALH
10
-
ns
Data setup Time
t
DS
20
-
ns
Data Hold Time
t
DH
15
-
ns
Write Cycle Time
t
WC
60
-
ns
WE High Hold Time
t
WH
25
-
ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
9
NAND Flash Technical Notes
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to
be a valid block.
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area.
Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten-
tional erasure of the original invalid block information is prohibited.
*
Check "FFh" at the column address 517
Figure 1. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update)
No
Invalid Block(s) Table
of the 1st and 2nd page in the block
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
10
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Write Address
Wait for tR Time
Verify Data
No
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Yes
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that
the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block
failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Write
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read
Single Bit Failure
Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
11
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
Block Replacement
NAND Flash Technical Notes (Continued)
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Buffer
memory
error occurs
Block A
Block B
Page a
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
12
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h'
command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets
the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effec-
tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command,
the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be input-
ted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting
from 'B' area, '01h' command must be inputted right before '80h' command is written.
00h
(1) Command input sequence for programming 'A' area
Address / Data input
80h
10h
00h
80h
10h
Address / Data input
The address pointer is set to 'A' area(0~255), and sustained
01h
(2) Command input sequence for programming 'B' area
Address / Data input
80h
10h
01h
80h
10h
Address / Data input
'B', 'C' area can be programmed.
It depends on how many data are inputted.
'01h' command must be rewritten before
every program operation
The address pointer is set to 'B' area(256~512), and will be reset to
'A' area after every program operation is executed.
50h
(3) Command input sequence for programming 'C' area
Address / Data input
80h
10h
50h
80h
10h
Address / Data input
Only 'C' area can be programmed.
'50h' command can be omitted.
The address pointer is set to 'C' area(512~527), and sustained
'00h' command can be omitted.
It depends on how many data are inputted.
'A','B','C' area can be programmed.
Pointer Operation of K9K1208U0A
Table 1. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
256 Byte
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
13
System Interface Using CE don't-care.
CE
WE
t
WP
t
CH
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
t
CS
(Min. 10ns)
Start Add.(4Cycle)
80h
Data Input
CE
CLE
ALE
WE
I/O
0
~
7
Data Input
CE don't-care
10h
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Start Add.(4Cycle)
00h
CE
CLE
ALE
WE
I/O
0
~
7
Data Output(sequential)
CE don't-care
R/B
t
R
RE
t
CEA
out
t
REA
(Max. 45ns)
CE
RE
I/O
0
~
7
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 3. Program Operation with CE don't-care.
Figure 4. Read Operation with CE don't-care.
Must be held
low during tR.
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
14
* Command Latch Cycle
CE
WE
CLE
ALE
I/O
0
~
7
Command
* Address Latch Cycle
t
CLS
t
CS
t
CLH
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
CE
WE
CLE
ALE
I/O
0
~
7
A
0
~A
7
t
CLS
t
CS
t
WC
t
WP
t
ALS
t
DS
t
DH
t
ALH
t
ALS
t
WH
A
9
~A
16
t
WC
t
WP
t
DS
t
DH
t
ALH
t
ALS
t
WH
A
17
~A
24
t
WC
t
WP
t
DS
t
DH
t
ALH
t
ALS
t
WH
t
ALH
A
25
t
DS
t
DH
t
WP
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
15
* Input Data Latch Cycle
CE
CLE
WE
I/O
0
~
7
DIN 0
DIN 1
DIN 511
ALE
t
ALS
t
CLH
t
WC
t
CH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
WP
t
WH
t
WP
t
WP
* Sequential Out Cycle after Read
(CLE=L, WE=H, ALE=L)
RE
CE
R/B
I/O
0
~
7
Dout
Dout
Dout
t
RC
t
REA
t
RR
t
RHZ*
t
REA
t
REH
t
REA
t
CHZ*
t
RHZ
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
16
* Status Read Cycle
CE
WE
CLE
RE
I/O
0
~
7
70h
Status Output
t
CLS
t
CLH
t
CS
t
WP
t
CH
t
DS
t
DH
t
RSTO
t
IR
t
RHZ*
t
CHZ*
t
WHR
t
CSTO
t
CLS
READ1 OPERATION
(READ ONE PAGE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h A
0
~ A
7
A
9
~ A
16
A
17
~ A
24
Dout N
Dout N+1 Dout N+2
Column
Address
Page(Row)
Address
t
WB
t
AR2
t
R
t
RC
t
RHZ*
t
RR
t
CHZ*
t
CEH
Dout 527
t
RB
t
CRY
t
WC
A
25
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
17
READ1 OPERATION
(INTERCEPTED BY CE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h
A
0
~ A
7
A
9
~ A
16
A
17
~ A
24
Dout N
Dout N+1
Dout N+2
Page(Row)
Address
Address
Column
t
WB
t
AR2
t
CHZ
t
R
t
RR
t
RC
READ2 OPERATION
(READ ONE PAGE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
50h
A
0
~ A
7
A
9
~ A
16
A
17
~ A
24
Dout
Dout 527
M Address
511+M
t
AR2
t
R
t
WB
t
RR
A
0
~A
3
: Valid Address
A
4
~A
7
: Don
t
care
A
25
A
25
Selected
Row
Start
address M
512
16
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
18
PAGE PROGRAM OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
80h
70h
I/O
0
Din
N
Din
10h
527
A
0
~ A
7
A
17
~ A
24
A
9
~ A
16
Sequential Data
Input Command
Column
Address
Page(Row)
Address
1 up to 528 Byte Data
Serial Input
Program
Command
Read Status
Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
t
PROG
t
WB
t
WC
t
WC
t
WC
SEQUENTIAL ROW READ OPERATION (WITHIN A BLOCK)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
00h
A
0
~ A
7
Busy
M
Output
A
9
~ A
16
A
17
~ A
24
Dout
N
Dout
N+1
Dout
527
Dout
0
Dout
1
Dout
527
Busy
M+1
Output
N
Ready
A
25
A
25
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
19
BLOCK ERASE OPERATION
(ERASE ONE BLOCK)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
60h
A
17
~ A
24
A
9
~ A
16
Auto Block Erase Setup Command
Erase Command
Read Status
Command
I/O
0
=1 Error in Erase
DOh
70h
I/O 0
Busy
t
WB
t
BERS
I/O
0
=0 Successful Erase
Page(Row)
Address
MANUFACTURE & DEVICE ID READ OPERATION
CE
CLE
I/O 0 ~ 7
WE
ALE
RE
90h
Read ID Command
Maker Code
Device Code
00h
ECh
76h
t
READID
t
WC
A
25
Address. 1cycle
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
20
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10
s(t
R
). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 60ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10
s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command. Addresses A
0
to A
3
set the starting address of the spare
area while addresses A
4
to A
7
are ignored. Unless the operation is aborted, the page address is automatically incremented for
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each
read operation.
Figure 3. Read1 Operation
Start Add.(4Cycle)
00h
A
0
~ A
7
& A
9
~ A
25
Data Output(Sequential)
(00h Command)
Data Field
Spare Field
CE
CLE
ALE
R/B
WE
I/O
0
~
7
RE
t
R
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
(01h Command)*
Data Field
Spare Field
1st half array
2st half array
1st half array
2st half array
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
21
Figure 4. Read2 Operation
50h
A
0
~ A
3
& A
9
~ A
25
Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
WE
Data Field
Spare Field
Start Add.(4Cycle)
(A
4
~ A
7
:
Don
t Care)
I/O
0
~
7
RE
Figure 5. Sequential Row Read1 Operation
00h
01h
A
0
~ A
7
& A
9
~ A
25
I/O
0
~
7
R/B
Start Add.(4Cycle)
Data Output
Data Output
Data Output
1st
2nd
Nth
(528 Byte)
(528 Byte)
t
R
t
R
t
R
t
R
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
(00h Command)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
(01h Command)
Data Field
Spare Field
Nth
1st half array 2nd half array
1st
2nd
Nth
Block
1st half array 2nd half array
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
22
Figure 6. Sequential Row Read2 Operation
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 2 for main array and 3 for spare array. The addressing may be done in
any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
50h
A
0
~ A
3
& A
9
~ A
25
I/O
0
~
7
R/B
Start Add.(4Cycle)
Data Output
Data Output
Data Output
2nd
Nth
(16Byte)
(16Byte)
1st
Figure 7. Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
25
I/O
0
~
7
R/B
Address & Data Input
I/O
0
Pass
528 Byte Data
10h
70h
Fail
t
R
t
R
t
R
t
PROG
Data Field
Spare Field
1st
Block
(A
4
~ A
7
:
Don
t Care)
Nth
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
23
Figure 9. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A
14
to A
25
is valid while A
9
to A
13
is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
60h
Block Add. : A
9
~ A
25
I/O
0
~
7
R/B
Address Input(3Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-
tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation
with "00h" command with the address of the source page moves the whole 528byte data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed.
The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back
Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory
array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. Thus, A14
and A25, the plane address, of source and destination page address must be the same.
Figure 8. Copy-Back Program Operation
00h
A
0
~ A
7
& A
9
~ A
25
I/O
0
~
7
R/B
Add.(4Cycles)
I/O
0
Pass
8Ah
70h
Fail
t
PROG
A
0
~ A
7
& A
9
~ A
25
Add.(4Cycles)
t
R
Source Address
Destination Address
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
24
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
I/O #
Status
Definition
I/O 0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
Reserved for Future
Use
"0"
I/O 2
"0"
I/O 3
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
"0" : Busy "1" : Ready
I/O 7
Write Protect
"0" : Protected "1" : Not Protected
Table2. Read Staus Register Definition
Figure 9. Read ID Operation
CE
CLE
I/O
0
~
7
ALE
RE
WE
90h
00h
ECh
76h
Address. 1cycle
Maker code
Device code
t
CR
t
AR1
t
READID
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
25
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFh
I/O
0
~
7
R/B
Table3. Device Status
t
RST
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
V
CC
R/B
open drain output
Device
GND
Rp =
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
I
L
=
3.2V
8mA
+
I
L
where I
L
is the sum of the input currents of all devices tied to the
R/B pin.
Rp
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
26
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
IL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
Figure 11. AC Waveforms for Power Transition
V
CC
WP
High
~ 2.5V
~ 2.5V
Package Dimensions
27
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
0.787
0.008
20.00
0.20
#1
#24
0
.
2
0
+
0
.
0
7
-
0
.
0
3
0
.
0
0
8
+
0
.
0
0
3
-
0
.
0
0
1
0
.
5
0
0
.
0
1
9
7
#48
#25
0
.
4
8
8
1
2
.
4
0
M
A
X
1
2
.
0
0
0
.
4
7
2
0
.
1
0
0
.
0
0
4
M
A
X
0
.
2
5
0
.
0
1
0
(
)
0.039
0.002
1.00
0.05
0.002
0.05
MIN
0.047
1.20
MAX
0.45~0.75
0.018~0.030
0.724
0.004
18.40
0.10
0~8
0
.
0
1
0
0
.
2
5
T
Y
P
0
.
1
2
5
+
0
.
0
7
5
0
.
0
3
5
0
.
0
0
5
+
0
.
0
0
3
-
0
.
0
0
1
0.50
0.020
(
)
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