PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
The Samsung M366S2953MTS is a 64M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S2953MTS consists of sixteen CMOS 64M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The M366S2953MTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
Performance range
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Serial presence detect with EEPROM
PCB : Height (1,375mil), double sided component
Part No.
Max Freq. (Speed)
M366S2953MTS-C75
133MHz@CL=3
M366S3953MTS-C1H
100MHz @ CL=2
M366S2953MTS-C1L
100MHz @ CL=3
FEATURE
GENERAL DESCRIPTION
M366S2953MTS SDRAM DIMM
128Mx64 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
PIN NAMES
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CLK0 ~ CLK3
Clock input
CKE0 ~ CKE1
Clock enable input
CS0 ~ CS3
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
V
DD
Power supply (3.3V)
V
SS
Ground
*V
REF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
*WP
Write protection
DU
Don
t use
NC
No connection
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
*CB0
*CB1
V
SS
NC
NC
V
DD
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
DU
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CLK0
V
SS
DU
CS2
DQM2
DQM3
DU
V
DD
NC
NC
*CB2
*CB3
V
SS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
V
DD
DQ20
NC
*V
REF
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
*WP
**SDA
**SCL
V
DD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
*CB4
*CB5
V
SS
NC
NC
V
DD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
V
SS
CKE0
CS3
DQM6
DQM7
*A13
V
DD
NC
NC
*CB6
*CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*V
REF
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
**SA0
**SA1
**SA2
V
DD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Preliminary
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
FUNCTIONAL BLOCK DIAGRAM
A0 ~ An, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U7
10
DQn
Every DQpin of SDRAM
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS
CS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM CS
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM CS
DQM5
DQM4
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM CS
CS2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM CS
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM CS
DQM7
DQM6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U8
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U9
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U10
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U11
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U12
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U13
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U14
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U15
DQM CS
CS1
CS3
CKE1
SDRAM U8 ~ U15
10K
V
DD
V
DD
Vss
Two 0.1uF Capacitors
per each SDRAM
To all SDRAMs
U0/U1/U2/U3
U4/U5/U6/U7
10
CLK0/1/2/3
U8/U9/U10/U11
U12/U13/U14/U15
1.5pF
Serial PD
SDA
SCL
A1
A2
A0
SA1 SA2
SA0
WP
47K
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
16
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23
C, f = 1MHz, V
REF
= 1.4V
200
mV)
Pin
Symbol
Min
Max
Unit
Address (A0 ~ A12, BA0 ~ BA1)
RAS, CAS, WE
CKE (CKE0 ~ CKE1)
Clock (CLK0 ~ CLK3)
CS (CS0, CS2)
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
C
ADD
C
IN
C
CKE
C
CLK
C
CS
C
DQM
C
OUT
80
80
50
40
25
15
10
100
100
60
45
35
20
15
pF
pF
pF
pF
pF
pF
pF
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C)
Parameter
Symbol
Test Condition
Version
Unit
Note
-75
-1H
-1L
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
O
= 0 mA
2000
1840
mA
1
Precharge standby cur-
rent in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
95
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
80
Precharge standby cur-
rent in non power-down
mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
480
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
160
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
160
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
130
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
800
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
560
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4banks Activated.
t
CCD
= 2CLKs
2000
1760
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
3040
2880
mA
2
Self refresh current
I
CC6
CKE
0.2V
112
mA
mA
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
Notes :
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
0.3V, T
A
= 0 to 70
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-75
-1H
-1L
Row active to row active delay
t
RRD
(min)
15
20
20
ns
1
RAS to CAS delay
t
RCD
(min)
20
20
20
ns
1
Row precharge time
t
RP
(min)
20
20
20
ns
1
Row active time
t
RAS
(min)
45
50
50
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
65
70
70
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2, 5
Last data in to Active delay
t
DAL
(min)
2 CLK + tRP
-
5
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
-
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-75
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
10
1000
10
1000
ns
1
CAS latency=2
-
10
12
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
6
6
ns
1,2
CAS latency=2
-
6
7
Output data
hold time
CAS latency=3
t
OH
3
3
3
ns
2
CAS latency=2
-
3
3
CLK high pulse width
t
CH
2.5
3
3
ns
3
CLK low pulse width
t
CL
2.5
3
3
ns
3
Input setup time
t
SS
1.5
2
2
ns
3
Input hold time
t
SH
0.8
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
6
6
ns
CAS latency=2
-
6
7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
12,
A
11
A
9
~ A
0
Note
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
Refresh
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A
0
~ A
9,
A
11
)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
L
Column
address
(A
0
~ A
9,
A
11
)
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
H
L
X
X
6
Precharge
Bank selection
H
X
L
L
H
L
X
V
L
X
All banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge power down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
1. OP Code : Operand code
A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
PC133/PC100 Unbuffered DIMM
M366S2953MTS
REV. 0.0 Dec. 2001
PACKAGE DIMENSIONS
0.150 Max
0.050
0.0039
(1.270
0.10)
0.250
(6.350)
Detail A
0.123
0.005
(3.125
0.125)
0.250
(6.350)
Detail B
0.123
0.005
(3.125
0.125)
0.079
0.004
(2.000
0.100)
0.079
0.004
(2.000
0.100)
0
.
2
0
0
M
i
n
(
5
.
0
8
M
i
n
)
(3.81 Max)
Tolerances :
.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOP
SDRAM Part No. :K4S510832M
5.250
5.014
Units : Inches (Millimeters)
R 0.079
(R 2.000)
0.250
(6.350)
1.450
(36.830)
2.150
(54.61)
0
.
1
1
8
(
3
.
0
0
0
)
0.350
0
.
1
0
0
M
i
n
(
2
.
5
4
0
M
i
n
)
0
.
7
0
0
(
1
7
.
7
8
0
)
.118DIA
0.004
(3.000DIA
0.100)
(8.890)
A
B
C
0.250
(6.350)
.450
(11.430)
4.550
(115.57)
0.157
0.004
(4.000
0.100)
0.089
(2.26)
(127.350)
(133.350)
1
.
3
7
5
(
3
4
.
9
2
5
)
0.118
(3.000)
0.050
0.008
0.006
(0.200
0.150)
(1.270)
0
.
1
0
0
M
i
n
(
2
.
5
4
0
M
i
n
)
Detail C
0.039
0.002
(1.000
0.050)
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