REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

PIN NAMES

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

Pin Name

Function

A0 ~ A12

Address input (Multiplexed)

BA0 ~ BA1

Select bank

DQ0 ~ DQ63

Data input/output

CB0 ~ CB7

Check bit (Data-in/data-out)

CLK0

Clock input

CKE0

Clock enable input

CS0 ~ CS3

Chip select input

RAS

Row address strobe

CAS

Colume address strobe

Write enable

DQM0 ~ 7

DQM

Power supply (3.3V)

Ground

REF

Power supply for reference

REGE

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

Don

t use

No connection

*WP

Write protection

PIN CONFIGURATIONS (Front side/back side)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Front

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15

CB0
CB1

NC
NC

DQM0

Pin

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Front

DQM1

CS0

A0
A2
A4
A6
A8

A10/AP

BA1

CLK0

CS2

DQM2
DQM3

NC
NC

CB2
CB3

DQ16
DQ17

Pin

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Front

DQ18
DQ19

DQ20

REF

*CKE1

DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

*CLK2

*WP

**SDA

**SCL

Pin

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

Back

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

DQ46
DQ47

CB4
CB5

NC
NC

CAS

DQM4

Pin

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

Back

DQM5

CS1

RAS

A1
A3
A5
A7
A9

BA0

A11
V

*CLK1

A12
V

CKE0

CS3

DQM6
DQM7

*A13

NC
NC

CB6
CB7

DQ48
DQ49

Pin

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

Back

DQ50
DQ51

DQ52

REF

REGE

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

*CLK3

**SA0
**SA1
**SA2

The Samsung M390S2858CT1 is a 128M bit x 72 Synchro-

nous Dynamic RAM high density memory module. The Sam-

sung M390S2858CT1 consists of eighteen CMOS Stacked

128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-

ages, three 18-bits Drive ICs for input control signal, one PLL

in 24-pin TSSOP package for clock and one 2K EEPROM in 8-

pin TSSOP package for Serial Presence Detect on a 168-pin

glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-

pling capacitors are mounted on the printed circuit board in

parallel for each SDRAM. The M390S2858CT1 is a Dual In-

line Memory Module and is intented for mounting into 168-pin

edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

GENERAL DESCRIPTION

M390S2858CT1 SDRAM DIMM

128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD

FEATURE

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

�

Performance range

� Burst mode operation
� Auto & self refresh capability (8192 Cycles/64ms)
� LVTTL compatible inputs and outputs
� Single 3.3V

�

0.3V power supply

� MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 & Full page)
Data scramble (Sequential & Interleave)
� All inputs are sampled at the positive going edge of the
system clock
� Serial presence detect with EEPROM
� PCB : Height (1,700mil), double sided component

Part No.

Max Freq. (Speed)

M390S2858CT1-C7C

133MHz(7.5ns @ CL=2)

M390S2858CT1-C7A

133MHz (7.5ns @ CL=3)

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

PIN CONFIGURATION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.

A0 ~ A12

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 7

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

REGE

Register enable

The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V

through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

CB0 ~ 7

Check bit

Check bits for ECC.

Power supply/ground

Power and ground for the input buffers and the core logic.

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

CB4~7

CB0~3

DQ12~15

DQ8~11

FUNCTIONAL BLOCK DIAGRAM

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D0L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D0U

BCS1,B

CKE0

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D1L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D1U

DQ0~3

DQ4~7

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D9L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D9U

DQ32~35

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D10L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D10U

DQ36~39

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D2L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D2U

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D3L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D3U

PCLK2

BDQM1

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D4L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D4U

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D11L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D11U

DQ40~43

BDQM5

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D12L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D12U

DQ44~47

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D13L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D13U

DQ28~31

DQ24~27

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D5L

PCLK5

BDQM2

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D5U

CLK
CS1
CTL
Add
DQM
DQ0~3

D6L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D6U

DQ16~19

DQ20~23

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D14L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D14U

DQ48~51

BDQM6

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D15L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D15U

DQ52~55

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D7L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D7U

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D8L

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D8U

PCLK7

BDQM3

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D16L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D16U

DQ56~59

BDQM7

CLK
CS0,CKE
CTL
Add
DQM
DQ0~3

D17L

CLK
CS1,CKE
CTL
Add
DQM
DQ0~3

D17U

DQ60~63

BDQM4

,BA0

10,

BA0

74ALVCF162835

CS2,CS3

CKE0

DQM2,3,6,7

10k

74ALVCF162835

PCLK9

REGE

BCS2,BCS3
B

CKE0,B

CKE0

CKE0,B

CKE0

BDQM2,3,6,7

74ALVCF162835

RAS,CAS,WE

CS0,CS1

DQM0,1,4,5

CDCF2510

IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9

CLK
FBIN

CLK0

12pF

FBOUT

PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9

PCLK8

PCLK6

PCLK1

PCLK3

PCLK4

BCS0,B

CKE0

BCS2,B

CKE0

A0~B

A12

RAS,B

CAS,B

WE,B

BA0,B

BA1

A0~B

A12

PCLK0

BDQM0

BCS3,B

CKE0

10,

BA0

,BA1

11,

12.

BA1

12.

BA1

CS2,CS3

CKE0

DQM2,3,6,7

RAS, B

CAS, B

RAS, B

CAS, B

BCS0,BCS1
BDQM0,1,4,5

RAS,B

CAS,B

WE,B

BA0,B

BA1

CLK1,2,3

12pF

Note
1. The actual values of

will depend upon the PLL chosen.

Serial PD

SDA

SCL

SA1 SA2

SA0

47K

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)

REG

Control Signal(RAS,CAS,WE)

OUT

td, tr = Delay of register (74ALVCF162835)

Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D

is to be issued 1clock after write command in external timing because D

is issued directly to module.

: Don

care

*1. Register Input

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

RAS

CAS

RAS

CAS

tSAC

tRDL

Read

Row Active

Command

Row Active

Write

Command

Precharge
Command

1CLK

*2. Register Output

*3. SDRAM

tRAC(refer to *1)

CAS latency(refer to *1)
=2CLK+1CLK

Qa0

Qa1

Qa2

Qa3

Db0

Db1

Db2

Db3

Precharge
Command

CAS latency(refer to *2)
=2CLK

tRAC(refer to *2)

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

�

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

�

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

3.0

3.3

3.6

Input high voltage

2.0

3.0

DDQ

+0.3

Input low voltage

-0.3

0.8

Output high voltage

2.4

= -2mA

Output low voltage

0.4

= 2mA

Input leakage current

-10

CAPACITANCE

= 3.3V, T

= 23

�

C, f = 1MHz, V

REF

=1.4V

�

200

mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A

~ A

)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0)

Input capacitance (CLK0)

Input capacitance (CS0, CS2)

Input capacitance (DQM0 ~ DQM7)

Input capacitance (BA0 ~ BA1)

Data input/output capacitance (DQ0 ~ DQ63)

Data input/output capacitance (CB0 ~ CB7)

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

1. V

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0 to 70

�

Parameter

Symbol

Test Condition

Version

Unit

Note

-7C

-7A

Operating current
(One bank active)

CC1

Burst length =1
t

(min)

= 0 mA

2840

2660

Precharge standby current in
power-down mode

CC2

CKE

(max), t

= 10ns

422

CC2

CKE & CLK

(max), t

Precharge standby current in
non power-down mode

CC2

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during 20ns

1070

CC2

CKE

(min), CLK

(max), t

Input signals are stable

362

Active standby current in
power-down mode

CC3

CKE

(max), t

= 10ns

566

CC3

CKE & CLK

(max), t

218

Active standby current in
non power-down mode

CC3

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during 20ns

1430

CC3

CKE

(min), CLK

(max), t

Input signals are stable

902

Operating current
(Burst mode)

CC4

= 0mA

Page Burst
4 Banks activated
t

CCD

=2CLK

3020

Refresh current

CC5

(min)

5000

4640

Self refresh current

CC6

CKE

0.2V

458

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Measured with 1 PLL & 3 Drive ICs.

4. Unless otherwise noted, input swing level is CMOS(V

DDQ

SSQ

)

Notes :

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

3.3V

1200

870

Output

50pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

Vtt = 1.4V

Output

50pF

Z0 = 50

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

AC OPERATING TEST CONDITIONS

= 3.3V

�

0.3V, T

= 0 to 70

�

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

Input timing measurement reference level

1.4

Input rise and fall time

tr/tf = 1/1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

Notes :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-7C

-7A

Row active to row active delay

RRD

(min)

RAS to CAS delay

RCD

(min)

Row precharge time

(min)

Row active time

RAS

(min)

RAS

(max)

100

Row cycle time

(min)

Last data in to row precharge

RDL

(min)

CLK

2,5

Last data in to Active delay

DAL

(min)

2 CLK + tRP

Last data in to new col. address delay

CDL

(min)

CLK

Last data in to burst stop

BDL

(min)

CLK

Col. address to col. address delay

CCD

(min)

CLK

Number of valid output data

CAS latency=3

CAS latency=2

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-7C

-7A

Unit

Note

Min

Max

Min

Max

CLK cycle time

CAS latency=3

7.5

1000

7.5

1000

CAS latency=2

7.5

CLK to valid
output delay

CAS latency=3

SAC

5.4

1,2

CAS latency=2

5.4

Output data
hold time

CAS latency=3

CAS latency=2

CLK high pulse width

2.5

CLK low pulse width

2.5

Input setup time

1.5

Input hold time

0.8

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

5.4

CAS latency=2

5.4

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

Notes : 1. OP Code : Operand code

~ A

& BA

~ BA

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

0,1

/AP

12,

11,

~ A

Note

Mode register set

OP code

1,2

Refresh

Auto refresh

Self
refresh

Entry

Exit

Bank active & row addr.

Row address

Read &
column address

Auto precharge disable

Column
address

)

Auto precharge enable

4,5

Write &
Column Address

Auto precharge disable

Column
address

)

Auto precharge enable

4,5

Burst stop

Precharge

Bank selection

All banks

Clock suspend or
active power down

Entry

Exit

Precharge power down mode

Entry

Exit

DQM

No operation command

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

0.250

(6.350)

Detail A

0.123

�

0.005

(3.125

�

0.125)

0.250

(6.350)

Detail B

0.123

�

0.005

(3.125

�

0.125)

0.079

�

0.004

(2.000

�

0.100)

0.079

�

0.004

(2.000

�

0.100)

Tolerances :

�

0.005(.13) unless otherwise specified

SDRAM Part No. : K4S510632C
- The used device is stacked 128Mx4 SDRAM
- Staktek's stacking technology is Samsung's stacking technology of choice

This module is based on JEDEC PC133 Specification

PACKAGE DIMENSIONS

5.250

5.014

Units : Inches (Millimeters)

0.254 Max

0.050

�

0.0039

(1.270

�

0.10)

R 0.079

(R 2.000)

0.250

(6.350)

1.450

(36.830)

2.150

(54.61)

.
1

(
3

.
0

)

0.350

.
1

i
n

(
2

.
5

i
n

)

.
7

(
1

.
7

)

.118DIA

�

0.004

(3.000DIA

�

0.100)

(8.890)

0.250

(6.350)

.450
(11.430)

4.550

(115.57)

0.157

�

0.004

(4.000

�

0.100)

0.054

(1.372)

(127.350)

(133.350)

.
7

(
4

.
1

)

0.118

(3.000)

.
1

i
n

(
3

.
9

i
n

)

(6.452 Max)

REG

PLL

REG

0.050

0.008

�

0.006

(0.200

�

0.150)

(1.270)

.
1

i
n

(
2

.
5

i
n

)

Detail C

0.039

�

0.002

(1.000

�

0.050)

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

Byte #

Function described

Function Supported

Hex value

Note

-7C

-7A

-7C

-7A

# of bytes written into serial memory at module manufacturer

128bytes

80h

Total # of bytes of SPD memory device

256bytes (2K-bit)

08h

Fundamental memory type

SDRAM

04h

# of row address on this assembly

0Dh

# of column address on this assembly

0Bh

# of module Rows on this assembly

2 Rows

02h

Data width of this assembly

72 bits

48h

...... Data width of this assembly

00h

Voltage interface standard of this assembly

LVTTL

01h

SDRAM cycle time from clock @CAS latency of 3

7.5ns

75h

SDRAM access time from clock @CAS latency of 3

5.4ns

54h

DIMM configuration type

ECC

02h

Refresh rate & type

7.8us, support self refresh

82h

Primary SDRAM width

04h

Error checking SDRAM width

04h

Minimum clock delay for back-to-back random column address

CCD

= 1CLK

01h

SDRAM device attributes : Burst lengths supported

1, 2, 4, 8 & full page

8Fh

SDRAM device attributes : # of banks on SDRAM device

4 banks

04h

SDRAM device attributes : CAS latency

2 & 3

06h

SDRAM device attributes : CS latency

0 CLK

01h

SDRAM device attributes : Write latency

0 CLK

01h

SDRAM module attributes

Registered/Buffered DQM,

address & control inputs and

On-card PLL

1Fh

SDRAM device attributes : General

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

0Eh

SDRAM cycle time @CAS latency of 2

7.5ns

10ns

75h

A0h

SDRAM access time @CAS latency of 2

5.4ns

6ns

54h

60h

SDRAM cycle time @CAS latency of 1

00h

SDRAM access time @CAS latency of 1

00h

Minimum row precharge time (=t

)

15ns

20ns

0Fh

14h

Minimum row active to row active delay (t

RRD

)

15ns

0Fh

Minimum RAS to CAS delay (=t

RCD

)

15ns

20ns

0Fh

14h

Minimum activate precharge time (=t

RAS

)

45ns

2Dh

Module Row density

2 Rows of 512MB

80h

Command and Address signal input setup time

1.5ns

15h

Command and Address signal input hold time

0.8ns

08h

Data signal input setup time

1.5ns

15h

M390S2858CT1-C7A/C7C

�Organization : 128MX72
�Composition : 128MX4 * 18ea
�Used component part # : K4S510632C-TC75/C7C
�# of banks in module : 2 Rows
�# of banks in component : 4 banks
�Feature : 1,700 mil height & double sided
�Refresh : 8K/64ms
�Contents :

REV. 0.1 Sept. 2001

M390S2858CT1

PC133 Registered DIMM

SERIAL PRESENCE DETECT INFORMATION

Byte #

Function described

Function Supported

Hex value

Note

-7C

-7A

-7C

-7A

Data signal input hold time

0.8ns

08h

36~61

Superset information (maybe used in future)

00h

SPD data revision code

JEDEC 2

02h

Checksum for bytes 0 ~ 62

ECh

2Dh

Manufacturer JEDEC ID code

Samsung

CEh

65~71

...... Manufacturer JEDEC ID code

Samsung

00h

Manufacturing location

Onyang Korea

01h

Manufacturer part # (Memory module)

4Dh

Manufacturer part # (DIMM Configuration)

33h

Manufacturer part # (Data bits)

Blank

20h

...... Manufacturer part # (Data bits)

39h

...... Manufacturer part # (Data bits)

30h

Manufacturer part # (Mode & operating voltage)

53h

Manufacturer part # (Module depth)

32h

...... Manufacturer part # (Module depth)

38h

Manufacturer part # (Refresh, #of banks in Comp. & Inter-

35h

Manufacturer part # (Composition component)

38h

Manufacturer part # (Component revision)

43h

Manufacturer part # (Package type)

54h

Manufacturer part # (PCB revision & type)

31h

Manufacturer part # (Hyphen)

" - "

2Dh

Manufacturer part # (Power)

43h

Manufacturer part # (Minimum cycle time)

37h

Manufacturer part # (Minimum cycle time)

43h

41h

Manufacturer part # (TBD)

Blank

20h

Manufacturer revision code (For PCB)

31h

...... Manufacturer revision code (For component)

C-die (4th Gen.)

43h

Manufacturing date (Year)

Manufacturing date (Week)

95~98

Assembly serial #

99~125

Manufacturer specific data (may be used in future)

Undefined

126

System frequency for 100MHz

100MHz

64h

127

Intel Specification details

Detailed 100MHz Information

8Fh

128+

Unused storage locations

Undefined

1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung

s own Assembly Serial # system. All modules may have different unique serial #.

5. These bytes are Undefined and can be used for Samsung's own purpose.

Note :

Электронный компонент: DS_M390S2858CT1