ELECTRONICS
MULTIMEDIA VIDEO
S5D0127X01 Data Sheet
PAGE 1 OF 96
Modified on May/04/2000
MULTISTANDARD VIDEO DECODER/SCALER
The S5D0127X01 converts analog NTSC, PAL or SECAM
video in composite, S-video, or component format to
digitized component video. Output data can be selected for
CCIR 601 or square pixel sample rates in either YCbCr or
RGB formats. The digital video can be scaled down in both
the horizontal and vertical directions. The S5D0127X01
also decodes Intercast, Teletext, Closed Caption, and WSS
data with a built-in bit data slicer. Digitized CVBS data can
be output directly during VBI for external processing.
FEATURES
Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and
SECAM formats with auto detection
6 analog inputs: 3 S-video, 6 composite, or 1 3-wire
YCbCr component video
2-line luma and chroma comb filters including adaptive
luma comb for NTSC
Programmable luma bandwidth, contrast, brightness,
and edge enhancement
Programmable chroma bandwidth, hue, and saturation
High quality horizontal and vertical down scaler
Intercast, Teletext and Closed Caption decoding with
built-in bit slicer
Direct output of digitized CVBS during VBI for Intercast
application
Analog square pixel or CCIR 601 sample rates
Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or
24-bit or 16-bit RGB formats with dithering
YCbCr 4:2:2 output can be 8 or 16 bits wide with
embedded timing reference code support for 8-bit mode
Simultaneous scaled and non-scaled digital output ports
outputs for 8-bit mode.
Direct access to scaler via bi-directional digital port.
Programmable Gamma correction table
Programmable timing signals
Industry standard IIC interface
APPLICATIONS
Multimedia
100 PQFP
ORDERING INFORMATION
Device
Package
Temperature Range
S5D0127X01-
Q0R0
100 PQFP
-20~+70C
Digital Video
Video Capture/Editing
RELATED PRODUCTS
S5D0123X01 MULTISTANDARD VIDEO
ENCODER
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 2 OF 96
Modified on May/04/2000
BLOCK DIAGRAM
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ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 3 OF 96
Modified on May/04/2000
PIN ASSIGNMENT - 100 PQFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62
60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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A
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S
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(
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)
H
A
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C0
C1
C2
C3
C4
C5
C6
VSS
VSS
VDD3
VDD3
C7
Y0
Y1
Y2
Y3
S5D0127X01
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VDDA
COMP2
TEST
VSS
AC2
VDDA
AC1
VSS
AC0
VDDA
AY2
VSS
AY1
VDDA
AY0
VSS
V
R
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S
2
(
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1
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6
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3
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3
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5
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4
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5
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6
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S
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V
3
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4
97
98
99
100
NCP
NCP
V
A
V
(
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0
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(
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NCP
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NCP
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NCP
NCP
Y
7
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1
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61
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 4 OF 96
Modified on May/04/2000
PIN DESCRIPTION
Pin Name
Pin #
Type
Description
INPUT
AY0
84
I
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
AY1
86
I
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
AY2
88
I
1 of 6 analog CVBS input or 1 of 3 S-video Y inputs or Y input for 3
wire component input
AC0
90
I
1 of 6 analog CVBS or 1 of 3 S-video C inputs.
AC1
92
I
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cb input for 3 wire
component input
AC2
94
I
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cr input for 3 wire
component input
XTALI
8
I
Pin 1 for an external crystal or TTL clock input.
XTALO
7
O
Pin 2 for an external crystal.
RST
10
I
Chip reset. Active low signal.
OUTPUT (All output pins can be selectively three-stated)
Y0 - Y7, C0 - C7 45-48,53-56,33-
39,44
O
Digital video outputs.
EXV0 - EXV7
16,27,28,61-63,
68,71
I/O
Expanded digital video I/O port. Can be configured as an additional
8-bit output port (no scaling), or additional outputs of the main digital
output stream for 24 bit output modes, as an 8-bit input for direct
digital access of the down scaler.
HS1
26
I/O
Programmable horizontal timing signal. One pulse every video line.
When the EXV port is configured as an input, this pin can be
programmed as an input.
HS2(IIC)
76
I/O
Programmable horizontal timing signal. One pulse every video line.
At power up, this pin needs a 10 k
pull-down resistor to configure
the chip to operate in IIC mode.
VS
23
I/O
Programmable vertical timing signal. When the EXV port is
configured as an input, this pin can be programmed as an input.
HAV
25
O
Programmable horizontal active video flag.
VAV(OENC0)
3
I/O
Programmable vertical active video flag.
During reset, the pin is an input and the logic state of this pin is
latched into the OENC[0] register bit. Use a 10 k
resistor for pull-up
or pull-down.
EHAV
5
O
Valid pixel data flag. Polarity is programmable. Active when output
video data is valid.
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 5 OF 96
Modified on May/04/2000
EVAV(OENC1)
4
I/O
Valid line flag. Polarity is programmable. Active when output video
line is valid. During reset, the pin is an input and the logic state of
this pin is latched into the OENC[1]register bit. Use a 10 k
resistor
for pull-up or pull-down.
ODD
22
O
Odd field flag. Polarity is programmable. Active for fields 1 and 3.
PID
17
O
PAL ID flag. High for phase alternating line.
OEN
15
I
Digital video data, timing and clock output 3-state control.
CK
18
I/O
Pixel clock. In normal decoding mode, this is an output. When the
EXV port is used as an input, this can be programmed as an input
pixel clock.
CK2
21
O
Pixel output clock (rate is one half of CK) aligned to HAV signal.
CCDAT
73
O
Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.
CCEN
74
O
When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.
MULTI-PURPOSE I/O PORTS AND TEST ENABLE
PORTA
58
I/O
Multi-purpose I/O port.
SCH(PORTB)
24
I/O
Multi-purpose I/O port.
TESTEN
57
I
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
TEST
96
I
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
REFERENCE AND COMPENSATION
VRT
77
I/O
ADC VRT compensation (requires an external 0.1
F capacitor
connected to VSS).
VRB
78
I/O
ADC VRB compensation (requires an external 0.1
F capacitor
connected to VSS).
COMP2
97
I/O
Internal 1.3 V reference (requires an external 0.1
F capacitor
connected to VSS).
HOST INTERFACE
SCLK
75
I
Serial clock for IIC host interface.
SDAT
72
I/O
Serial data for IIC host interface.
AEX0 - AEX1
69 - 70
I
Device ID selection for IIC host interface.
PIN DESCRIPTION (Continued)
Pin Name
Pin #
Type
Description
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