DRAM MODULE
M372F0410DB0/DF0
M372F0400DB0/DF0
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
HPC
-C50
50ns
18ns
90ns
25ns
-C60
60ns
20ns
110ns
30ns
M372F0400DB0/DF0 / M372F0410DB0/DF0 with EDO Mode
4M x 72 DRAM DIMM with ECC using 4Mx4, 4K/2K Refresh, 3.3V
The Samsung M372F040(1)0D is a 4Mx72bits Dynamic RAM
high density memory module. The Samsung M372F040(1)0D
consists of eighteen CMOS 4Mx4bits DRAMs in SOJ/TSOP-II
300mil package, and two 16bits driver IC in 48pin TSSOP
package mounted on a 168-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM. The M372F040(1)0D is a Dual In-line
Memory Module and is intended for mounting into 168-pin
edge connector sockets.
GENERAL DESCRIPTION
PD Note : PD & ID Terminals must each be pulled up through a resister to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
Part Identification
- M372F0400DB0 (4096 cycles/64ms Ref., SOJ)
- M372F0400DF0 (4096 cycles/64ms Ref., TSOP)
- M372F0410DB0 (4096 cycles/32ms Ref., SOJ)
- M372F0410DF0 (4096 cycles/32ms Ref., TSOP)
Fast Page Mode with Extended Data Out Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
TTL compatible inputs and outputs
Single 3.3V
0.3V power supply
JEDEC standard pinout & Buffered PDpin
Buffered input except RAS and DQ
PCB : Height(1000mil), double sided component
PIN NAMES
Pins marked
*
are not used in this module.
Pin Names
Function
A0, B0, A1 - A11
Address Input (4K Ref.)
A0, B0, A1 - A10
Address Input (2K Ref.)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0, CAS4
Colume Address Strobe
V
CC
Power(+3.3V)
V
SS
Ground
NC
No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
PD & ID Table
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Pin
50NS
60NS
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
0
ID0
ID1
0
0
0
0
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
RSVD
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
*A12
V
CC
RFU
RFU
V
SS
OE2
RAS2
CAS4
RSVD
W2
V
CC
RSVD
RSVD
DQ18
DQ19
V
SS
DQ20
DQ21
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
*CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
RSVD
*RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
*RAS3
*CAS5
RSVD
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
FEATURES
NOTE : A11 is used for only M372F0400DB0/DF0 (4K ref.)
DRAM MODULE
M372F0410DB0/DF0
M372F0400DB0/DF0
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
.1 or .22uF Capacitor
under each DRAM
To all DRAMs
A0
B0
A1-An
W0, 2
OE0, 2
U0-U8
U9-U17
A1-An : U0-U17
RAS0
W0
OE0
A0
DQ0
DQ1
DQ2
DQ3
A1-A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS0
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ0
DQ1
DQ2
DQ3
DQ8
DQ9
DQ10
DQ11
U2
DQ0
DQ1
DQ2
DQ3
DQ12
DQ13
DQ14
DQ15
U3
DQ0
DQ1
DQ2
DQ3
DQ16
DQ17
DQ18
DQ19
U4
DQ0
DQ1
DQ2
DQ3
DQ20
DQ21
DQ22
DQ23
U5
DQ0
DQ1
DQ2
DQ3
DQ24
DQ25
DQ26
DQ27
U6
DQ0
DQ1
DQ2
DQ3
DQ28
DQ29
DQ30
DQ31
U7
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
U8
RAS2
W2
OE2
B0
DQ0
DQ1
DQ2
DQ3
A1-A11(A10)
DQ36
DQ37
DQ38
DQ39
CAS4
U9
DQ0
DQ1
DQ2
DQ3
DQ40
DQ41
DQ42
DQ43
U10
DQ0
DQ1
DQ2
DQ3
DQ44
DQ45
DQ46
DQ47
U11
DQ0
DQ1
DQ2
DQ3
DQ48
DQ49
DQ50
DQ51
U12
DQ0
DQ1
DQ2
DQ3
DQ52
DQ53
DQ54
DQ55
U13
DQ0
DQ1
DQ2
DQ3
DQ56
DQ57
DQ58
DQ59
U14
DQ0
DQ1
DQ2
DQ3
DQ60
DQ61
DQ62
DQ63
U15
DQ0
DQ1
DQ2
DQ3
DQ64
DQ65
DQ66
DQ67
U16
DQ0
DQ1
DQ2
DQ3
DQ68
DQ69
DQ70
DQ71
U17
DRAM MODULE
M372F0410DB0/DF0
M372F0400DB0/DF0
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one hyper page mode cycle,
t
HPC.
* NOTE :
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
*
I
CC2
I
CC3
*
I
CC4
*
I
CC5
I
CC6
*
I
I(L)
I
O(L)
V
OH
V
OL
Symbol
Speed
M372F0400DB0/DF0
M372F0410DB0/DF0
Unit
Min
Max
Min
Max
I
CC1
-C50
-C60
-
-
1620
1440
-
-
1980
1800
mA
mA
I
CC2
Don
t care
-
100
-
100
mA
I
CC3
-C50
-C60
-
-
1620
1440
-
-
1980
1800
mA
mA
I
CC4
-C50
-C60
-
-
1440
1260
-
-
1620
1440
mA
mA
I
CC5
Don
t care
-
30
-
30
mA
I
CC6
-C50
-C60
-
-
1620
1440
-
-
1980
1800
mA
mA
I
I(L)
I
O(L)
Don
t care
-45
-5
45
5
-45
-5
45
5
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: EDO Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -2mA)
: Output Low Voltage Level (I
OL
= 2mA)
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns, Pulse width is measured at V
CC
.
*2 : -1.3V/15ns, Pulse width is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3
0
-
-
3.6
0
V
CC
+0.3
*1
0.8
V
V
V
V
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
18
50
V
V
C
W
mA
DRAM MODULE
M372F0410DB0/DF0
M372F0400DB0/DF0
CAPACITANCE
(T
A
= 25
C, Vcc=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11(A10), B0]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0, CAS4]
Input/Output capacitance[DQ0 - 71]
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
-
-
-
-
-
20
20
80
20
20
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-C50
-C60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Read-modify-write cycle time
t
RWC
131
155
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
18
20
ns
3,4,5,14
Access time from column address
t
AA
30
35
ns
3,10,14
CAS to output in Low-Z
t
CLZ
8
8
ns
3,14
OE to output in Low-Z
t
OLZ
8
8
ns
3,14
Output buffer turn-off delay from CAS
t
CEZ
8
18
8
20
ns
6,11,12,14
Transition time(rise and fall)
t
T
2
50
2
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
18
20
ns
14
CAS hold time
t
CSH
36
43
ns
14
CAS pulse width
t
CAS
8
10K
10
10K
ns
13
RAS to CAS delay time
t
RCD
18
32
18
40
ns
4,14
RAS to column address delay time
t
RAD
13
20
13
25
ns
10,14
CAS to RAS precharge time
t
CRP
10
10
ns
14
Row address set-up time
t
ASR
5
5
ns
14
Row address hold time
t
RAH
8
8
ns
14
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address to RAS lead time
t
RAL
30
35
ns
14
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
-2
-2
ns
8,14
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
18
20
ns
14
Write command to CAS lead time
t
CWL
8
10
ns
Data set-up time
t
DS
-2
-2
ns
9,14
Data hold time
t
DH
13
15
ns
9,14
Refresh period(4K Ref.)
t
REF
64
64
ms
Refresh period(2K Ref.)
t
REF
32
32
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W dealy time
t
CWD
36
40
ns
7
DRAM MODULE
M372F0410DB0/DF0
M372F0400DB0/DF0
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-C50
-C60
Unit
Note
Min
Max
Min
Max
RAS to W dealy time
t
RWD
71
83
ns
7,14
Column address to W delay time
t
AWD
48
55
ns
7
CAS precharge time to W delay time
t
CPWD
53
60
ns
CAS set-up time(CAS-before-RAS refresh)
t
CSR
5
5
ns
14
CAS hold time(CAS-before-RAS refresh)
t
CHR
8
8
ns
14
RAS to CAS precharge time
t
RPC
3
3
ns
14
CAS precharge time (C-B-R counter test cycle)
t
CPT
20
20
ns
Access time from CAS precharge
t
CPA
33
40
ns
3,14
Hyper page cycle time
t
HPC
25
30
ns
12
Hyper page read-modify-write cycle time
t
HPRWC
68
77
ns
12
CAS precharge time(Hyper page cycle)
t
CP
8
10
ns
RAS pulse width (Hyper page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
35
40
ns
14
OE access time
t
OEA
18
20
ns
14
OE to data delay
t
OED
18
20
ns
14
Output buffer turn off delay time from OE
t
OEZ
5
18
5
20
ns
6,11,14
OE command hold time
t
OEH
13
15
ns
W to RAS precharge time(C-B-R refresh)
t
WRP
15
15
ns
14
W to RAS hold time(C-B-R refresh)
t
WRH
8
8
ns
14
Output data hold time
t
DOH
10
10
ns
14
Output buffer turn off delay time from RAS
t
REZ
3
13
3
15
ns
6.11.12
Output buffer turn off delay time from W
t
WEZ
3
18
3
20
ns
6.11.14
W to data delay
t
WED
20
20
ns
14
OE to CAS hold time
t
OCH
5
5
ns
CAS hold time to OE
t
CHO
5
5
ns
OE precharge time
t
OEP
5
5
ns
W pulse width(Hyper page cycle)
t
WPE
5
5
ns
PDE to Valid PD bit
t
PD
10
10
ns
PDE to PD bit Inactive
t
PDOFF
2
7
2
7
ns
Present Detect Read Cycle
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
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