200pin DDR SDRAM SODIMM

M470L6423CK0

Rev. 0.2 Jan. 2002

Revision History

Revision 0.0 (August 2001)

1. First release.

Revision 0.1 (Dec. 2001)

- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.

- Revised AC parameter table

- Deleted typical current in IDD spec. table
- Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
- Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
- Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
- Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
- Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
- Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
--Rename tCDLR(Write data out to Read command) t0 tWTR
- Added tDAL(tWR+tRP)

Revision 0.2 (Jan, 2002)

1. Added tRAP(Active to Read w/ autoprecharge command)

From

DDR266A

DDR266B

DDR200

DDR266A

DDR266B

DDR200

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tHZ

tACmin

-400ps

tACmax

-400ps

tACmin

-400ps

tACmax

-400ps

tACmin

-400ps

tACmax

-400ps

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

tLZ

tACmin

-400ps

tACmax

-400ps

tACmin

-400ps

tACmax

-400ps

tACmin

-400ps

tACmax

-400ps

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

tWPST

(tCK)

0.25

0.4

0.6

0.4

0.6

0.4

0.6

tPDEX

10ns

7.5ns

10ns

200pin DDR SDRAM SODIMM

M470L6423CK0

Rev. 0.2 Jan. 2002

GENERAL DESCRIPTION

PIN DESCRIPTION

* These pins are not used in this module.

Pin Name

Function

A0 ~ A12

Address input (Multiplexed)

BA0 ~ BA1

Bank Select Address

DQ0 ~ DQ63

Data input/output

DQS0 ~ DQS7

Data Strobe input/output

CK0~ CK2,
CK0 ~ CK2

Clock input

CKE0 ~ CKE1

Clock enable input

CS0 ~ CS1

Chip select input

RAS

Row address strobe

CAS

Column address strobe

Write enable

DM0 ~ DM7

Data - in mask

VDD

Power supply (2.5V)

VDDQ

Power Supply for DQS(2.5V)

VSS

Ground

VREF

Power supply for reference

VDDSPD

Serial EEPROM Power
Supply ( 2.3V to 3.6V)

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

VDDID

VDD identification flag

No connection

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

M470L6423CK0 200pin DDR SDRAM SODIMM
64Mx64 200pin DDR SDRAM SODIMM based on DDP 64Mx8

The Samsung M470L6423CK0 is 64M bit x 64 Double Data
Rate SDRAM high density memory modules.
The Samsung M470L6423CK0 consists of eight CMOS DDP
64M x 8 bit with 4banks Double Data Rate SDRAMs in 54pin
TSOP-II(400mil) packages mounted on a 200pin glass-epoxy
substrate. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM.
The M470L6423CK0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.

� Performance range

� Power supply : Vdd: 2.5V

�

0.2V, Vddq: 2.5V

�

0.2V

�

Double-data-rate architecture; two data transfers per clock cycle

� Bidirectional data strobe(DQS)
� Differential clock inputs(CK and CK )
� DLL aligns DQ and DQS transition with CK transition
� Programmable Read latency 2, 2.5 (clock)
� Programmable Burst length (2, 4, 8)
� Programmable Burst type (sequential & interleave)
� Edge aligned data output, center aligned data input
� Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
� Serial presence detect with EEPROM
� PCB : Height 1250 mil, double sided component

Part No.

Max Freq.

Interface

M470L6423CK0-C(L)B3 166MHz(6ns@CL=2.5)

SSTL_2

M470L6423CK0-C(L)A2 133MHz(7.5ns@CL=2)
M470L6423CK0-C(L)B0 133MHz(7.5ns@CL=2.5)

M470L6423CK0-C(L)A0 100MHz(10ns@CL=2)

FEATURE

PIN CONFIGURATIONS (Front side/back side)

Pin

Front

Pin

Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

1
3
5

7
9

11
13
15

17
19

21
23
25

27
29

31
33
35

37
39

41
43

45
47

49
51
53

55
57

59
61
63

VREF

VSS
DQ0

DQ1
VDD

DQS0

DQ2
VSS

DQ3
DQ8

VDD
DQ9

DQS1

VSS

DQ10

DQ11

VDD

CK0

/CK0

VSS

DQ16
DQ17

VDD

DQS2

DQ18

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

67
69
71

73
75

77
79
81

83
85

87
89
91

93
95

97
99

101

103
105

107
109
111

113
115

117
119
121

123
125

127
129
131

133

DQ27

VDD

CB0

CB1
VSS

DQS8

CB2

VDD

CB3

VSS
CK2

/CK2

VDD

CKE1

A12

VSS

A5
A3
A1

VDD

A10/AP

BA0
/WE

/S0

DU(A13)

VSS

DQ32
DQ33

VDD

DQS4

135
137
139

141
143

145
147
149

151
153

155
157
159

161
163

165
167
169

171
173

175
177
179

181
183

185
187
189

191
193

195
197
199

DQ34

VSS

DQ35

DQ40

VDD

DQ41
DQS5

VSS

DQ42
DQ43

VDD
VDD

VSS

DQ48

DQ49

VDD

DQS6

DQ50

VSS

DQ51
DQ56

VDD

DQ57
DQS7

VSS

DQ58
DQ59

VDD

SDA

SCL

VDDSPD

VDDID

2
4
6

12
14
16

18
20

22
24
26

28
30

32
34
36

38
40

42
44

46
48

50
52
54

56
58

60
62
64

VREF

VSS
DQ4

DQ5

VDD

DM0

DQ6
VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14

DQ15

VDD
VDD

VSS
VSS

DQ20
DQ21

VDD
DM2

DQ22

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

68
70
72

74
76

78
80
82

84
86

88
90
92

94
96

100
102

104
106

108
110
112

114
116

118
120
122

124
126

128
130
132

134

DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/(RESET)

VSS
VSS
VDD

VDD

CKE0

DU(BA2)

A11

VSS

A4
A2
A0

VDD

BA1

/RAS
/CAS

/S1

VSS

DQ36
DQ37

VDD

DM4

136
138
140

142
144

146
148
150

152
154

156
158
160

162
164

166
168
170

172
174

176
178
180

182
184

186
188
190

192
194

196
198
200

DQ38

VSS

DQ39

DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

/CK1

CK1

VSS

DQ52

DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7

VSS

DQ62
DQ63

VDD

SA0

SA1
SA2

D U

Key

200pin DDR SDRAM SODIMM

M470L6423CK0

Rev. 0.2 Jan. 2002

CKE0

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS

A0 - A13

A0-A13: DDR SDRAMs D0 - D7

BA0 - BA1

BA0-BA1: DDR SDRAMs D0 - D7

RAS

RAS: SDRAMs D0 - D7

CAS

CAS: SDRAMs D0 - D7

WE: SDRAMs D0 - D7

Serial PD

SA0

SA1

SA2

SCL

SDA

S S

D0 - D7

DDQ

D0 - D7

VREF

DDID

Strap: see Note 4

DDSPD

SPD

Clock Wiring

Clock

Input

SDRAMs

CK0/ CK0

CK1/ CK1

CK2/ CK2

4 SDRAMs

DQS0
DM0

*Clock Net Wiring

Card
Edge

Dram1

Dram2

R=120

�

Dram3

Dram4

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQS

DQS4
DM4

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS

DQS1
DM1

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQS

DQS5
DM5

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS

DQS2
DM2

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQS

DQS6
DM6

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS

DQS3
DM3

I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7

DQS

DQS7
DM7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CKE1

CKE0 CKE1

CKE1 CKE0

CKE0 CKE1

CKE1 CKE0

Notes:
1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.

FUNCTIONAL BLOCK DIAGRAM

200pin DDR SDRAM SODIMM

M470L6423CK0

Rev. 0.2 Jan. 2002

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Notes 1. Includes

�

25mV margin for DC offset on V

REF

, and a combined total of

�

50mV margin for all AC noise and DC offset on V

REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V

REF

and internal DRAM noise coupled

TO V

REF

, both of which may result in V

REF

noise. V

REF

should be de-coupled with an inductance of

3nH.

2.V

is not applied directly to the device. V

T T

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of V

REF

3. V

I D

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70

�

Parameter

Symbol

Min

Max

Unit

Note

Supply voltage(for device with a nominal V

of 2.5V)

2.3

2.7

I/O Supply voltage

DDQ

2.3

2.7

I/O Reference voltage

REF

VDDQ/2-50mV

VDDQ/2+50mV

I/O Termination voltage(system)

REF

-0.04

REF

+0.04

Input logic high voltage

I H

(DC)

REF

+0.15

DDQ

+0.3

Input logic low voltage

(DC)

-0.3

REF

-0.15

Input Voltage Level, CK and CK inputs

I N

(DC)

-0.3

DDQ

+0.3

Input Differential Voltage, CK and CK inputs

I D

(DC)

0.3

DDQ

+0.6

Input crossing point voltage, CK and CK inputs

(DC)

1.15

1.35

Input leakage current

-2

Output leakage current

O Z

-5

Output High Current(Normal strengh driver)
;V

OUT

= V

T T

+ 0.84V

-16.8

Output High Current(Normal strengh driver)
;V

OUT

= V

T T

- 0.84V

16.8

Output High Current(Half strengh driver)
;V

OUT

T T

+ 0.45V

-9

Output High Current(Half strengh driver)
;V

OUT

= V

T T

- 0.45V

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

& V

DDQ

supply relative to V

, V

DDQ

-1.0 ~ 3.6

Storage temperature

STG

-55 ~ +150

�

Power dissipation

Short circuit current

Absolute Maximum Rate

Электронный компонент: M470L0914ET0