200pin DDR SDRAM SODIMM
M470L6423DN0
Rev. 0.0 May 2002
GENERAL DESCRIPTION
PIN DESCRIPTION
* These pins are not used in this module.
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS7
Data Strobe input/output
CK0~CK1
CK0~ CK1
Clock input
CKE0 ~ CKE1
Clock enable input
CS0 ~ CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DM0 ~ DM7
Data - in mask
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
NC
No connection
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
M470L6423DN0 200pin DDR SDRAM SODIMM
64Mx64 200pin DDR SDRAM SODIMM based on sTSOP 32Mx8
The Samsung M470L6423DN0 is 64Mbit x 64 Double Data Rate
SDRAM high density memory modules.
The Samsung M470L6423DN0 consists of sixteen 32M x 8 bit
with 4banks Double Data Rate SDRAMs in 54pin sTSOP II
(300mil) packages mounted on a 200pin glass-epoxy substrate.
Three 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM.
The M470L6423DN0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. Data I/O transactions are possible on both edges of
DQS. Range of operating frequencies, programmable latencies
and burst lengths allow the same device to be useful for a variety
of high bandwidth, high performance memory system applica-
tions.
Performance range
(
C : Normal Power_IDD6 , L : Low Power_IDD6 )
Power supply : Vdd: 2.5V
0.2V, Vddq: 2.5V
0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1250 mil, double sided component
Part No.
Max Freq.
Interface
M470L6423DN0-C(L)B3 166MHz(6.0ns@CL=2.5)
SSTL_2
M470L6423DN0-C(L)A2 133MHz(7.5ns@CL=2)
M470L6423DN0-C(L)B0 133MHz(7.5ns@CL=2.5)
FEATURE
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
DQ27
VDD
CB0
*
CB1
*
VSS
DQS8
CB2
*
VDD
CB3
*
DU
VSS
CK2
*
/CK2
*
VDD
CKE1
DU
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
/WE
/CS0
DU(A13)
VSS
DQ32
DQ33
VDD
DQS4
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID*
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
*
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
DQ31
VDD
CB4
*
CB5
*
VSS
DM8*
CB6
*
VDD
CB7
*
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
*
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
*
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
*
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Key
Key
200pin DDR SDRAM SODIMM
M470L6423DN0
Rev. 0.0 May 2002
FUNCTIONAL BLOCK DIAGRAM
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D0
DM0
DM
D8
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
I/O 7
I/O 6
I/O 1
I/O 0
D1
DM
D9
I/O 5
I/O 4
I/O 3
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 7
I/O 6
I/O 1
I/O 0
D2
DM
D10
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 7
I/O 6
I/O 1
I/O 0
D3
DM
D11
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 7
I/O 6
I/O 1
I/O 0
D4
DM4
DM
D12
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 7
I/O 6
I/O 1
I/O 0
D5
DM
D13
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 7
I/O 6
I/O 1
I/O 0
D6
DM
D14
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 7
I/O 6
I/O 1
I/O 0
D7
DM
D15
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM7
A0 - A12
A0-A12 : DDR SDRAMs D0 - D15
RAS
RAS : DDR SDRAMs D0 - D15
CAS
CAS : DDR SDRAMs D0 - D15
CKE0
CKE : DDR SDRAMs D0 - D7
WE
WE : DDR SDRAMs D0 - D15
CS0
CS1
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CKE1
CKE : DDR SDRAMs D8 - D15
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D15
DQS0
DQS
DQS4
DQS1
DQS5
DQS
DQS
DQS2
DQS
DQS
DQS3
DQS
DQS
DM6
DQS6
DQS7
DQ15
I/O 2
I/O 5
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
V
SS
D0 - D15
D0 - D15
V
DD
/V
DDQ
D0 - D15
D0 - D15
VREF
V
DDSPD
SPD
*Clock Net Wiring
Card
Edge
D0,D8 / D4,D12
D1,D9 / D5,D13
R=120
5%
CK0 / 1
CK0 / 1
D2,D10/ D6,D14
D3,D11/ D7,D15
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown
3. DQ, DQS, DM/DQS resistors: 22 Ohm.
CK2
CK2
10pF
200pin DDR SDRAM SODIMM
M470L6423DN0
Rev. 0.0 May 2002
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Notes 1. Includes
25mV margin for DC offset on V
REF
, and a combined total of
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
3nH.
2.V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70
C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V)
V
DD
2.3
2.7
I/O Supply voltage
V
DDQ
2.3
2.7
V
I/O Reference voltage
V
REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
4
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK inputs
V
IN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and CK inputs
V
ID
(DC)
0.3
V
DDQ
+0.6
V
3
Input crossing point voltage, CK and CK inputs
V
IX
(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver)
;V
OUT
=
V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver)
;V
OUT
= V
TT
- 0.45V
I
OL
9
mA
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
& V
DDQ
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
24
W
Short circuit current
I
OS
50
mA
Absolute Maximum Rate
PDF 
ZIP
