Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

DDR2 Unbuffered SODIMM

200pin Unbuffered SODIMM based on 512Mb C-die

64bit Non-ECC

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

DDR2 Unbuffered SODIMM Ordering Information

Note: "Z" of Part number(11th digit) stand for Lead-free products.
Note: "3" of Part number(12th digit) stand for Dummy Pad PCB products.

Part Number

Density

Organization

Component Composition

Number of Rank

Height

M470T3354CZ3-C(L)E7/E6/D5/CC

256MB

32Mx64

32Mx16(K4T51163QC)*4

30mm

M470T3354CZ0-C(L)E7/E6/D5/CC

256MB

32Mx64

32Mx16(K4T51163QC)*4

30mm

M470T6554CZ3-C(L)E7/E6/D5/CC

512MB

64Mx64

32Mx16(K4T51163QC)*8

30mm

M470T6554CZ0-C(L)E7/E6/D5/CC

512MB

64Mx64

32Mx16(K4T51163QC)*8

30mm

M470T2953CZ3-C(L)E7/E6/D5/CC

1GB

128Mx64

64Mx8(K4T51083QC)*16

30mm

M470T2953CZ0-C(L)E7/E6/D5/CC

1GB

128Mx64

64Mx8(K4T51083QC)*16

30mm

Features

· Performance range

· JEDEC standard 1.8V ± 0.1V Power Supply
· V

DDQ

= 1.8V ± 0.1V

· 200 MHz f

for 400Mb/sec/pin, 267MHz f

for 533Mb/sec/pin, 333MHz f

for 667Mb/sec/pin, 400MHz f

for 800Mb/sec/pin

· 4 Banks
· Posted CAS

· Programmable CAS Latency: 3, 4, 5
· Programmable Additive Latency: 0, 1 , 2 , 3 and 4

· Write Latency(WL) = Read Latency(RL) -1
· Burst Length: 4 , 8(Interleave/nibble sequential)

· Programmable Sequential / Interleave Burst Mode
· Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

· Off-Chip Driver(OCD) Impedance Adjustment
· On Die Termination with selectable values(50/75/150 ohms or disable)

· PASR(Partial Array Self Refresh)
· Average Refresh Period 7.8us at lower than a T

CASE

°C, 3.9us at 85°C < T

CASE

< 95

°C

support

High Temperature Self-Refresh rate enable feature

· Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16

· All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.

E7 (DDR2-800)

E6 (DDR2-667)

D5 (DDR2-533)

CC (DDR2-400)

Unit

Speed@CL3

400

Mbps

Speed@CL4

533

400

Mbps

Speed@CL5

800

667

533

Mbps

CL-tRCD-tRP

5-5-5

4-4-4

3-3-3

Address Configuration

Organization

Row Address

Column Address

Bank Address

Auto Precharge

64Mx8(512Mb) based Module

A0-A13

A0-A9

BA0-BA1

A10

32Mx16(512Mb) based Module

A0-A12

A0-A9

BA0-BA1

A10

Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

Pin Configurations (Front side/Back side)

Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.

Pin

Front

Pin

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

REF

DQS2

DM2

101

102

151

DQ42

152

DQ46

DQ4

103

104

153

DQ43

154

DQ47

DQ0

DQ5

DQ18

DQ22

105

A10/AP

106

BA1

155

156

DQ1

DQ19

DQ23

107

BA0

108

RAS

157

DQ48

158

DQ52

DM0

109

110

159

DQ49

160

DQ53

DQS0

DQ24

DQ28

111

112

161

162

DQS0

DQ6

DQ25

DQ29

113

CAS

114

ODT0

163

NC, TEST

164

CK1

DQ7

115

NC/S1

116

A13

165

166

CK1

DQ2

DM3

DQS3

117

118

167

DQS6

168

DQ3

DQ12

DQS3

119

NC/ODT1

120

169

DQS6

170

DM6

DQ13

121

122

171

172

DQ8

DQ26

DQ30

123

DQ32

124

DQ36

173

DQ50

174

DQ54

DQ9

DM1

DQ27

DQ31

125

DQ33

126

DQ37

175

DQ51

176

DQ55

127

128

177

178

DQS1

CK0

CKE0

NC/CKE1

129

DQS4

130

DM4

179

DQ56

180

DQ60

DQS1

CK0

131

DQS4

132

181

DQ57

182

DQ61

133

134

DQ38

183

184

DQ10

DQ14

BA2

135

DQ34

136

DQ39

185

DM7

186

DQS7

DQ11

DQ15

137

DQ35

138

187

188

DQS7

A12

A11

139

140

DQ44

189

DQ58

190

141

DQ40

142

DQ45

191

DQ59

192

DQ62

DQ16

DQ20

143

DQ41

144

193

194

DQ63

DQ17

DQ21

145

146

DQS5

195

SDA

196

147

DM5

148

DQS5

197

SCL

198

SA0

DQS2

100

149

150

199

SPD

200

SA1

Pin Description

Pin Name

Function

Pin Name

Function

CK0,CK1

Clock Inputs, positive line

SDA

SPD Data Input/Output

CK0,CK1

Clock Inputs, negative line

SA1,SA0

SPD address

CKE0,CKE1

Clock Enables

DQ0~DQ63

Data Input/Output

RAS

Row Address Strobe

DM0~DM7

Data Masks

CAS

Column Address Strobe

DQS0~DQS7

Data strobes

Write Enable

DQS0~DQS7

Data strobes complement

S0,S1

Chip Selects

TEST

Logic Analyzer specific test pin
(No connect on So-DIMM)

A0~A9, A11~A13

Address Inputs

Core and I/O Power

A10/AP

Address Input/Autoprecharge

Ground

BA0,BA1

SDRAM Bank Address

REF

Input/Output Reference

ODT0,ODT1

On-die termination control

SPD

SPD Power

SCL

Serial Presence Detect(SPD) Clock Input

Spare pins, No connect

Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

Input/Output Functional Description

Symbol

Type

Function

CK0-CK1

Input

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and fall-
ing edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is
synchronized to the input clock.

CKE0-CKE1

Input

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refesh mode.

S0-S1

Input

Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected
by S0, Rank 1 is selected by S1. Ranks are also called "Physical banks".

RAS, CAS, WE

Input

When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation
to be executed by the SDRAM.

BA0~BA1

Input

Selects which DDR2 SDRAM internal bank is activated.

ODT0~ODT1

Input

Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register
Set (EMRS).

A0~A9,

A10/AP,

A11~A13

Input

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK
and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines
the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the
state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

DQ0~DQ63

In/Out

Data Input/Output pins.

DM0~DM7

Input

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to
be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.

DQS0~DQS7
DQS0~DQS7

In/Out

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by
the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is
sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the
system board to VSS and DDR2 SDRAM mode registers programmed appropriately.

SPD,V

Supply

Power supplies for core, I/O, Serial Presence Detect, and ground for the module.

SDA

In/Out

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to V

to act

as a pull up.

SCL

Input

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to V

to act as

a pull up.

SA0~SA1

Input

Address pins used to select the Serial Presence Detect base address.

TEST

In/Out

The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).

Rev. 1.2 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 SDRAM

Functional Block Diagram:

512MB, 64Mx64 Module

(Populated as 2 rank of x16 DDR2 SDRAMs)

M470T6554CZ3/M470T6554CZ0

DQS1
DQS1
DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS0
DQS0
DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS5
DQS5
DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS4
DQS4
DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS3
DQS3
DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS2
DQS2
DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS7
DQS7
DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

C
K
E

O
D
T

C
K
E

O
D
T

C
K
E

O
D
T

C
K
E

O
D
T

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

C
K
E

O
D
T

C
K
E

O
D
T

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

C
K
E

O
D
T

C
K
E

O
D
T

CKE0

CKE1

ODT0

ODT1

SPD

SA0

SCL

SDA

DDR2 SDRAMs D0 - D7, SPD

REF

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7, V

and V

SPD

Serial PD

SA1

SCL
A0
A1
A2

A0 - A13

DDR2 SDRAMs D0 - D7

RAS

DDR2 SDRAMs D0 - D7

CAS

DDR2 SDRAMs D0 - D7

BA0 - BA1

DDR2 SDRAMs D0 - D7

+ 5%

Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms

5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms

5%.

* Wire per Clock Loading

Table/Wiring Diagrams

* Clock Wiring

Clock Input

DDR2 SDRAMs

*CK0/CK0
*CK1/CK1

4 DDR2 SDRAMs
4 DDR2 SDRAMs

+ 5%

DQS6
DQS6
DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M470T3354CZ0-CCC

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M470T3354CZ0-CCC