Product Overview
Address Spaces
Addressing Modes
Control Registers
Interrupt Structure
Instruction Set
S3C8444
PRODUCT OVERVIEW
11
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements.
Timer/counters with selectable operating modes are included to support real-time operations. Many SAM8
microcontrollers have an external interface that provides access to external memory and other peripheral
devices.
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C8444 MICROCONTROLLER
The S3C8444 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is
based on the powerful SAM8 CPU core. Stop and Idle power-down modes were implemented to reduce power
consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip
register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of
program and data memory. The S3C8444 is a versatile microcontroller that is ideal for use in a wide range of
general-purpose applications such as CD-ROM/DVD-ROM drives.
Using the SAM8 modular design approach, the following peripherals were integrated with the SAM8 CPU core:
PRODUCT OVERVIEW
S3C8444
12
-- Six configurable 8-bit general I/O ports
-- One 8-bit n-channel, open-drain output port
-- One 8-bit input port for A/D converter input or
digital input
-- Full-duplex serial data port with one
synchronous and three asynchronous (UART)
operating modes
-- Two 8-bit timers with interval timer or PWM
mode
-- Two 16-bit timer/counters with four
programmable operating modes
-- Two programmable 8-bit PWM modules with
corresponding output pins
-- One 8-bit capture module with CAP input pin
-- A/D converter with 8 selectable input pins
The S3C8444 is a versatile microcontroller that is
ideal for use in a wide range of general-purpose
ROM-less applications such as CD-ROM/DVD-ROM
drivers.
Figure 11. S3C8444 Microcontroller
S3C8444
PRODUCT OVERVIEW
13
FEATURES
CPU
SAM8 CPU core
Memory
1040-byte of internal register file
4-kbyte internal program memory area
External Interface
64-Kbyte external data memory area
64-Kbyte external program memory (ROMless)
60-Kbyte external program memory (normal)
Instruction Set
78 instructions
IDLE and STOP instructions
Instruction Execution Time
240 ns at 25 MHz f
OSC
(minimum)
Interrupts
20 interrupt sources and 19 interrupt vectors
Seven interrupt levels
Fast interrupt processing (level0 and 3-7 only)
Timer/Counters
Two 8-bit timers with interval timer or PWM
mode (timers A and B)
Two 16-bit timer/counters with four
programmable operating modes (timers C and
D)
General I/O
Six 8-bit general I/O ports (ports 0,1,2,3,4, and
5)
One 8-bit n-channel, open-drain output port
(port 6)
One 8-bit input port (for ADC input or port 7
digital input)
Serial Port
Full-duplex serial data port (UART)
Four programmable operating modes
PWM and Capture
Two output channels (PWM0, PWM1)
8-bit resolution with 2-bit prescaler
97.66-kHz frequency (25-MHz CPU clock)
Capture module with CAP input pin
Analog-to-Digital Converter
Eight analog input pins
8-bit conversion resolution
7.68-s conversion speed (25-MHz CPU clock)
Operating Temperature Range
20
C to + 85
C
Operating Voltage Range
4.5 V to 5.5 V
Package Type
80-pin QFP, 80pin TQFP
PRODUCT OVERVIEW
S3C8444
14
BLOCK DIAGRAM
PORT 0
PORT 3
PORT I/O & INTERRUPT
CONTROL
SAM8 CPU
P0.0P0.7
(A8A15)
RESET
PORT2
PORT 4
PORT 1
PORT 2
P2.0P2.5
(Control Signal)
P1.0P1.7
(AD0AD7)
EA
PORT 5
P5.0P5.3
TIMERS
A and B
SERIAL
PORT
RxD
TxD
PORT 6
P6.0P6.7
TIMERS
C and D
P2.6
P2.7
P5.4P5.7
SAM8 BUS
P4.0P4.7
A/D
CONVERTER
ADC0 /P7.0
ADC7 /P7.7
AV
SS
AV
REF
PWM
MODULE
PWM0
PWM1
SAM8 BUS
CAPTURE (P3.6)
TA
TB
TCCK
TDCK
TCG
TDG
V
DD1
V
DD2
,V
SS1
,V
SS2
EXTERNAL ADDRESS/DATA BUS
1040-BYTE
REGISTER FILE
P3.0P3.7
Figure 12. S3C8444 Block Diagram
S3C8444
PRODUCT OVERVIEW
15
PIN ASSIGNMENTS
P0.1 / A9
P0.0 / A8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
(ext.
)
P2.7 / TB
P2.6 / TA
P2.5 /
PM
P2.4 /
MR
P2.3 /
DM
P2.2 /
MW
P2.1 /
DS
P2.0 /
AS
RxD
TxD
PWM1
PWM0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RESET
NC
AS
V
SS1
(int.)
X
OUT
X
IN
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.7 / ADC7
P7.6 / ADC6
P7.5 / ADC5
P7.4 / ADC4
P7.3 / ADC3
AV
SS
P7.2 / ADC2
P7.1 / ADC1
AV
REF
P7.0 / ADC0
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
EA
P1.7 / AD7
P1.6 / AD6
P1.5 / AD5
P1.4 / AD4
P1.3 / AD3
P1.2 / AD2
P1.1 / AD1
P1.0 / AD0
V
DD1
(int.)
P0.7 / A15
P0.6 / A14
P0.5 / A13
P0.4 / A12
P0.3 / A11
P0.2 / A10
P4.7 / INT11
P4.6 / INT10
P4.5 / INT9
P4.4 / INT8
P4.3 / INT7
P4.2 / INT6
P4.1 / INT5
P4.0 / INT4
V
SS2
(ext.)
P3.7 /
WAIT
P3.6 / CAP
P3.5
P3.4
P3.3 / TDG / INT3
P3.2 / TCG / INT2
P3.1 / TDCK / INT1
S3C8444
80-QFP
(TOP VIEW)
P3.0 / TCCK / INT0
Figure 13. S3C8444 Pin Assignments
PRODUCT OVERVIEW
S3C8444
16
PIN ASSIGNMENTS (Continued)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S3C8444
80-TQFP
(TOP VIEW)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P7.0 / ADC0
P4.7 / INT11
P4.6 / INT10
P4.5 / INT9
P4.4 / INT8
P4.3 / INT7
P4.2 / INT6
P4.1 / INT5
P4.0 / INT4
V
SS2
(ext.)
P3.7 /
WAIT
P3.6 / CAP
P3.5
P3.4
P3.3 / TDG / INT3
P3.2 / TCG / INT2
P3.1 / TDCK / INT1
P3.0 / TCCK / INT0
PWM0
PWM1
AS
NC
RESET
EA
P1.7 / AD7
P1.6 / AD6
P1.5 / AD5
P1.4 / AD4
P1.3 / AD3
P1.2 / AD2
P1.1 / AD1
P1.0 / AD0
V
DD1
(int.)
P0.7 / A15
P0.6 / A14
P0.5 / A13
P0.4 / A12
P0.3 / A11
P0.2 / A10
P0.1 / A9
P0.0 / A8
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
(ext.
)
P2.7 / TB
P2.6 / TA
P2.5 /
PM
P2.4 /
MR
P2.3 /
DM
P2.2 /
MW
P2.1 /
DS
P2.0 /
AS
RxD
TxD
Vss1 (int.)
X
OUT
X
IN
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.7 / ADC7
P7.6 / ADC6
P7.5 / ADC5
P7.4 / ADC4
P7.3 / ADC3
AV
SS
P7.2 / ADC2
P7.1 / ADC1
AV
REF
Figure 14. S3C8444 Pin Assignments
S3C8444
PRODUCT OVERVIEW
17
PIN DESCRIPTIONS
Table 11. S3C8444 Pin Descriptions
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
P0.0 - P0.7
I/O
Nibble programmable port; input or output mode
selected by software; Schmitt trigger input or push-
pull, open-drain output with software assignable
pull-ups; alternately configurable as external
interface address lines A8 - A15.
3
2, 1,
80-75
A8 - A15
P1.0 - P1.7
I/O
Same general characteristics as port 0; alternately
configurable as external interface address/data
lines AD0 - AD7.
3
73-66
AD0 - AD7
P2.0 - P2.7
I/O
General I/O port with Schmitt trigger input or push-
pull output. bit programmable;
P2.0 / Address Strobe (
AS
)
P2.1 / Data Strobe (
DS
)
P2.2 / Memory Write (
MW
)
P2.3 / Data Memory select (
DM
)
P2.4 / Memory Read (
MR
)
P2.5 / Program Memory select (
PM
)
P2.6 / timer A output (TA)
P2.7 / timer B output (TB)
5
19 - 12
AS, DS,
MW, DM,
MR, PM
,
TA, TB
P3.0 - P3.7
I/O
General I/O port with bit programmable pins.
Schmitt trigger input or push-pull output with
software assignable pull-ups. Input or output mode
is selectable by software. P3.0 - P3.3 are alternately
used as inputs for external interrupts INT0-INT3,
respectively (with noise filters and interrupt control):
P3.0 / timer C clock input (TCCK) / INT0
P3.1 / timer D clock input (TDCK) / INT1
P3.2 / timer C gate input (TCG) / INT2
P3.3 / timer D gate input (TDG) / INT3
P3.6 / Capture data input (CAP)
P3.7 /
WAIT
for slow memory interface
4
24-31
(See pin
description)
P4.0 - P4.7
I/O
General I/O port with bit programmable pins.
Schmitt trigger input or push-pull, open-drain output
with software assignable pull-ups. Input or output
mode is selectable by software. P4.0-P4.7 can
alternately be used as inputs for external interrupts
INT4-INT11, respectively (with noise filters and
interrupt control)
4
33-40
INT4 -
INT11
PRODUCT OVERVIEW
S3C8444
18
Table 11. S3C8444 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
P5.0P5.7
I/O
General I/O port with nibble programmable
pins. Schmitt trigger input or push-pull,
open-drain output mode. Mode and pull-ups
are assigned by software.
3
103
--
P6.0P6.7
O
N-channel, open-drain output port; the pin
circuits can withstand loads up to 9 volts.
8
5851
--
ADC0ADC7
I
Analog input pins for A/D converter module.
Alternatively used as general-purpose
digital input port 7.
2
41, 4344,
4650
P7.0P7.7
AV
REF
, AV
SS
--
A/D converter reference voltage and
ground
--
42, 45
--
RxD
I/O
Serial data RxD pin for receive input and
transmit output (mode 0)
6
20
--
TxD
O
Serial data TxD pin for transmit output and
shift clock input (mode 0)
7
21
--
PWM0,
PWM1
O
Pulse width modulation output pins
7
23, 22
--
TA, TB
O
Output pins for timer A and timer B
5
13, 12
P2.6, P2.7
INT0INT11
I
External interrupt input pins
4
2427,
3340
P3.0P3.3,
P4.0P4.7
TCCK, TDCK
I
External clock input for timer C and timer D
4
24, 25
P3.0, P3.1
TCG, TDG
I
Gate input pins for timer C and timer D
4
26, 27
P3.2, P3.3
CAP
I
Capture data input for PWM module
4
30
P3.6
WAIT
I
Input pin for the slow memory timing signal
from the external interface
4
31
P3.7
RESET
I
System reset pin (pull-up resistor: 220 k
)
1
64
--
EA
I
External access (EA) pin with two modes:
5 V input: normal ROM-less operation with
external interface (0 V is not allowed)
9 V10 V input: for factory test mode
--
65
--
V
DD1
, V
SS1
--
Power input pins for CPU operation
(internal)
--
74, 61
--
V
DD2
, V
SS2
--
Power input pins for port output (external)
--
11, 32
--
X
IN
, X
OUT
--
Main oscillator pins
--
59, 60
--
AS
O
Address strobe
7
62
--
NC
--
No connection pins (connect to V
SS
)
--
62, 63
--
NOTE
VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also.
S3C8444
PRODUCT OVERVIEW
19
PIN CIRCUITS
Table 12. Pin Circuit Assignments for the S3C8444
Circuit Number
Circuit Type
S3C8444 Assignments
1
Input
RESET
pin
2
Input
A/D converter input pins, ADC0ADC7
3
I/O
Port 0, 1, and 5
4
I/O
Ports 3 and 4, TCCK, TDCK, TCG, TDG, CAP,
WAIT
, INT0INT11
5
I/O
Port 2 (
AS, DS, MW, DM, MR, PM
, TA,TB)
6
I/O
Serial port RxD pin
7
Output
Serial port TxD pin, PWM0, PWM1 and
AS
8
Output
Port 6 (n-channel, open-drain output with high current capability)
PRODUCT OVERVIEW
S3C8444
110
INPUT
PULL-UP
RESISTOR
(Typical 230 k
)
V
DD
Figure 15. Pin Circuit Type 1 (
RESET
RESET
)
IN
V
REF
ADC
LOGIC
INPUT
BUFFER
+
Figure 16. Pin Circuit Type 2 (ADC0ADC7)
S3C8444
PRODUCT OVERVIEW
111
PULL-UP
RESISTOR
(Typical 46 k
)
DATA
V
DD
IN / OUT
PULL-UP
ENABLE
INPUT
V
SS
OPEN-
DRAIN
OUTPUT
DISABLE
V
DD
Figure 17. Pin Circuit Type 3 (Ports 0,1, and 5)
PRODUCT OVERVIEW
S3C8444
112
IN / OUT
V
SS
V
DD
OUTPUT
DISABLE
DATA
EXTERNAL
INTERRUPT
INPUT
INPUT
NOISE
FILTER
PULL-UP
RESISTOR
(Typical 46 k
)
V
DD
PULL-UP
ENABLE
Figure 18. Pin Circuit Type 4
(Ports 3 and 4, TCCK, TDCK, TCG, TDG, CAP,
WAIT,
WAIT,
INT0INT11)
S3C8444
PRODUCT OVERVIEW
113
IN / OUT
INPUT
V
SS
OUTPUT
DISABLE
V
DD
DATA
SELECTION BITS
FOR PORTS OR
OTHER FUNCTIONS
OTHER
FUNCTION
OPEN-
DRAIN
Figure 19. Pin Circuit Type 5 (Port 2,
AS, DS, MW, DM, MR
AS, DS, MW, DM, MR
,
PM
PM
, TA and TB)
PRODUCT OVERVIEW
S3C8444
114
IN / OUT
V
SS
V
DD
OUTPUT
DISABLE
DATA
V
DD
EDGE DETECTION
NOISE FILTER
INPUT
R
(46 k
)
a
Figure 110. Pin Circuit Type 6 (Serial RxD Pin)
S3C8444
PRODUCT OVERVIEW
115
OUTPUT
V
SS
DATA
V
DD
Figure 111. Pin Circuit Type 7
(AS, serial TxD Pin, PWM0, PWM1)
NOTE: Circuit type 8 can withstand up to 9-volt loads.
OUTPUT
V
SS
DATA
Figure 112. Pin Circuit Type 8 (Port 6)
S3C8444
ELECTRICAL DATA
161
16
ELECTRICAL DATA
In this section, S3C8444 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
-- Absolute maximum ratings
-- DC electrical characteristics
-- AC electrical characteristics
-- Input timing for external interrupts (ports 3 and 4)
--
Input timing for
RESET
-- I/O capacitance
-- Data retention supply voltage in Stop mode
-- Stop mode release timing initiated by
RESET
-- A./D Converter Electrical Characteristics
-- Serial port timing characteristics in mode 0 (10 MHz)
-- Serial clock waveform
-- Serial port timing in mode 0 (shift register mode)
-- External memory timing characteristics (10 MHz)
-- External memory read and write timing
-- Recommended A/D converter circuit for highest absolute accuracy
-- Main oscillator frequency (f
OSC1
)
-- Main oscillator clock stabilization time (t
ST1
)
-- Clock timing measurement at X
IN
-- Suboscillator clock stabilization time (t
ST2
)
-- Characteristic curves
ELECTRICAL DATA
S3C8444
162
Table 161. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to +7.0
V
Input voltage
V
I1
Port 6 only (open-drain)
0.3 to +10
V
V
I2
All ports except port 6
0.3 to V
DD
+ 0.3
Output voltage
V
O
0.3 to V
DD
+ 0.3
V
Output current
high
I
O H
One I/O pin active
18
mA
All I/O pins active
60
Output current low
I
O L
One I/O pin active
30
mA
Total pin current for ports 0, 2, 3, 4, 6
100
Total pin current for ports 1 and 5
200
Operating
temperature
T
A
20 to + 85
C
Storage
temperature
T
STG
65 to + 150
C
Table 162. D.C. Electrical Characteristics
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input high
V
IH1
All input pins except V
IH2
0.8 V
DD
V
DD
V
voltage
V
IH2
X
IN
V
DD
0.5
Input low voltage
V
IL1
All input pins except V
IL2
0.2 V
DD
V
V
IL2
X
IN
0.4
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Port 1 only
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5V
I
OH
= 200 A
All output pins except port 1
V
DD
1.0
S3C8444
ELECTRICAL DATA
163
Table 162. D.C. Electrical Characteristics (Continued)
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 2 mA
All output pins except port 5
0.4
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 1.5 mA
Port 5
Input high leakage
current
I
LIH1
V
IN
= V
DD
All input pins except X
IN
3
A
I
LIH2
V
IN
= V
DD
X
IN
20
Input low leakage
current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
,
and
RESET
3
A
I
LIL2
V
IN
= 0 V
X
IN
20
Output high
leakage current
I
LOH1
V
OUT
= V
DD
All output pins except for
port 6
5
A
I
LOH2
Port 6 (open-drain)
V
OUT
= 9 V
20
Output low
leakage current
I
LOL
V
OUT
= 0 V
5
A
Pull-up resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V 10%
Ports 0, 1, 4, 5, and RxD
30
46
80
k
R
L2
V
IN
= 0 V; V
DD
= 5 V 10%
RESET
only
120
230
320
Supply current
(1)
I
DD1
V
DD
= 5 V
10%
25 MHz crystal oscillator
35
50
mA
V
DD
= 5 V
10%
10 MHz crystal oscillator
30
I
DD2
Idle mode: V
DD
= 5 V
10%
25 MHz crystal oscillator
11
25
Idle mode: V
DD
= 5 V
10%
10 MHz crystal oscillator
5
I
DD3
Stop mode;
V
DD
= 5 V 10%
3
20
A
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
ELECTRICAL DATA
S3C8444
164
Table 163. A.C. Electrical Characteristics
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 6.0V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input
high, low width
t
INTH,
t
INTL
P3.0P3.3, P4.0P4.7
3
t
CPU
RESET
input low
width
t
RSL
Input
22
t
CPU
NOTES:
1.
The unit t
CPU
means one CPU clock period.
2.
The oscillator frequency is the same as CPU clock frequency.
t
INTL
t
INTH
0.8
V
DD
0.2
V
DD
Figure 161. Input Timing for External Interrupts (Ports 3 and 4)
t
RSL
0.2 V
DD
RESET
Figure 162. Input Timing for
RESET
RESET
S3C8444
ELECTRICAL DATA
165
Table 164. Input/Output Capacitance
(T
A
= 20
C to + 85
C, V
DD
=
0 V )
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
C
IN
f = 1 MHz; unmeasured pins
are returned to V
SS
10
pF
Output
capacitance
C
OUT
I/O capacitance
C
IO
Table 165. Data Retention Supply Voltage in Stop Mode
(T
A
= 20
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
DDDR
2
6
V
Data retention
supply current
I
DDDR
V
DDDR
= 2 V
5
A
VDD
RESET
EXECUTION OF
STOP INSTRUCTION
VDDDR
DATA RETENTION MODE
STOP MODE
RESET
OCCURS
NORMAL
OPERATING
MODE
OSCILLATION
STABILIZATION
TIME
tWAIT
NOTE:
tWAIT is the same as 4096 x 32 x 1 / f OSC .
0.2 VDD
Figure 163. Stop Mode Release Timing Initiated by
RESET
RESET
ELECTRICAL DATA
S3C8444
166
Table 166. A/D Converter Electrical Characteristics
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 6.0 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Resolution
8
8
8
bit
Absolute
accuracy
(1)
V
DD
= 5.12 V
CPU clock = 18 MHz
AV
REF
= 5.12 V
AV
SS
= 0 V
| 3 |
LSB
Conversion
time
(2)
t
CON
t
CPU
192
(3)
s
Analog reference
voltage
AV
REF
2.56
V
DD
V
Analog ground
AV
SS
V
SS
V
Analog input
voltage
V
IAN
AV
SS
AV
REF
V
Analog input
impedance
R
AN
2
M
NOTES:
1.
Excluding quantization error, absolute accuracy equals
1/2 LSB.
2.
'Conversion time' is the time required from the moment a conversion operation starts until it ends.
3.
tCPU is the CPU clock period.
Table 167. Serial Port Timing Characteristics in Mode 0 (10 MHz)
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 6.0V, V
SS
= 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Serial port clock cycle time
t
SCK
500
t
CPU
6
700
ns
Output data setup to clock rising edge
t
S1
300
t
CPU
5
Clock rising edge to input data valid
t
S2
300
Output data hold after clock rising edge
t
H1
50
t
CPU
Input data hold after clock rising edge
t
H2
0
Serial port clock high, low width
t
HIGH
,
t
LOW
200
t
CPU
3
400
NOTES:
1.
All times are in ns and assume a 10 MHz input frequency.
2.
The unit tCPU means one CPU clock period.
3.
The oscillator frequency is identical to the CPU clock frequency.
S3C8444
ELECTRICAL DATA
167
t
HIGH
0.8 V
DD
0.2 V
DD
t
LOW
t
SCK
Figure 164. Serial Clock Waveform
ELECTRICAL DATA
S3C8444
168
N
O
T
E
:
T
h
e
s
y
m
b
o
l
s
s
h
o
w
n
i
n
t
h
i
s
d
i
a
g
r
a
m
a
r
e
d
e
f
i
n
e
d
a
s
f
o
l
l
o
w
s
:
t
S
C
K
S
e
r
i
a
l
p
o
r
t
c
l
o
c
k
c
y
c
l
e
t
i
m
e
t
S
1
O
u
t
p
u
t d
a
t
a
s
e
t
u
p
t
o
c
l
o
c
k
r
i
s
i
n
g
e
d
g
e
t
S
2
C
l
o
c
k
ris
i
n
g
e
d
g
e
t
o
i
n
p
u
t
d
a
t
a
v
a
l
i
d
t
H
1
O
u
t
p
u
t d
a
t
a
h
o
l
d
a
f
t
e
r
c
l
o
c
k
r
i
s
i
n
g
e
d
g
e
t
H
2
I
n
p
u
t
d
a
t
a
h
o
l
d
a
f
t
e
r
c
l
o
c
k
r
i
s
i
n
g
e
d
g
e
D
A
T
A
O
U
T
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
t
S
C
K
S
H
I
F
T
C
L
O
C
K
t
S
1
t
H
1
D
A
T
A
I
N
t
S
2
t
H
2
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
V
A
L
I
D
Figure 165. Serial Port Timing in Mode 0 (Shift Register Mode)
S3C8444
ELECTRICAL DATA
169
Table 168. External Memory Timing Characteristics (10 MHz)
(T
A
= 20
C to + 85
C, V
DD
= 4.5 V to 6.0 V)
Number
Symbol
Parameter
Normal Timing
Extended Timing
Min
Max
Min
Max
1
t
dA
(AS)
Address valid to
AS
delay
10
50
2
t
dAS
(A)
AS
to address float delay
35
85
3
t
dAS
(DR)
AS
to read data required valid
140
335
4
t
wAS
AS
low width
35
85
5
t
dA
(DS)
Address float to
DS
0
0
6a
t
wDS
(read)
DS
(read) low width
125
275
6b
t
wDS
(write)
DS
(write) low width
65
165
7
t
dDS
(DR)
DS
to read data required valid
80
255
8
t
hDS
(DR)
Read data to
DS
hold time
0
0
9
t
dDS
(A)
DS
to address active delay
20
70
10
t
dDS
(AS)
DS
to
AS
delay
30
80
11
t
dDO
(DS)
Write data valid to
DS
(write)
delay
10
50
12
t
dAS
(W)
AS
to wait delay
90
335
13
t
hDS
(W)
DS
to wait hold time
0
0
14
t
dRW
(AS)
R/
W
valid to
AS
delay
20
70
15
t
dDS
(DW)
DS
to write data not valid delay
20
70
NOTES:
1.
All times are in ns and assume a 10 MHz input frequency.
2.
Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.
3.
Auto-wait states add 100 ns to the time of number 12.
ELECTRICAL DATA
S3C8444
1610
WAIT
(P3.7)
DS
R/
W
PORT A
A8A15,
DM
DM
PORT AD
D0D7
A0A7
AS
IN
OUT
D0D7 OUT
WAIT WINDOW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Figure 166. External Memory Read and Write Timing
(See Table 157 for a description of each timing point.)
S3C8444
ELECTRICAL DATA
1611
V
DD
V
DD
NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 100 Ohms.
If this resistor is omitted, the absolute accuracy will be maximum of 4 LSBs.
ADC0ADC7
S3C8444
R
ANALOG
INPUT PIN
10 F
+
103
C
101
C
REFERENCE
VOLTAGE
INPUT
AV
SS
V
SS
AV
REF
Figure 167. Recommended A/D Converter Circuit for Highest Absolute Accuracy
ELECTRICAL DATA
S3C8444
1612
Table 169. Main Oscillator Frequency (f
OSC1
)
(T
A
= 20
C + 85
C, V
DD
= 4.5 V to 6.0 V)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal
C2
C1
X
IN
X
OUT
C2
C1
X
IN
X
OUT
CPU clock oscillation
frequency
1
18
MHz
Ceramic
C2
C1
X
IN
X
OUT
CPU clock oscillation
frequency
1
18
MHz
External clock
X
IN
X
OUT
a
a
X
IN
input frequency
1
18
MHz
Table 1610. Recommended Oscillator Constants
(T
A
= 20
C + 85
C, V
DD
= 4.5 V to 6.0 V)
Manufacturer
Product Name
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
C2
MIN
MAX
TDK
CCR20.0MS6
5
5
4.5
5.5
SMD Type
CCR24.0M6
5
5
4.5
5.5
SMD Type
CCR25.0M6
5
4.5
5.5
SMD Type
NOTE: On-chip C: 30pF
20% built in.
S3C8444
ELECTRICAL DATA
1613
Table 1611. Main Oscillator Clock Stabilization Time (t
ST1
)
(T
A
= 20
C + 85
C, V
DD
= 4.5 V to 6.0 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
V
DD
= 4.5 V to 6.0 V
20
ms
Ceramic
Stabilization occurs when V
DD
is equal to the minimum
oscillator voltage range.
10
ms
External clock
X
IN
input high and low level width (t
XH
, t
XL
)
25
500
ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a
RESET
signal. The RESET should therefore
be held at low level until the tST1 time has elapsed (see Figure 153).
X
IN
t
XL
t
XH
1 /
f
OSC1
V
DD
0.5
V
0.4
V
Figure 168. Clock Timing Measurement at X
IN
ELECTRICAL DATA
S3C8444
1614
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
I
DD1
(mA)
4.5
VDD (V)
(TA = 25
C)
5.0
5.5
fOSC = 25 MHz
fOSC = 20 MHz
22
24
26
28
30
32
34
36
38
fOSC = 10 MHz
Figure 169. IDD1 vs VDD
S3C8444
ELECTRICAL DATA
1615
I
DD2
(mA)
4.5
VDD (V)
(TA = 25
C)
5.0
5.5
fOSC = 25 MHz
fOSC = 20 MHz
4
5
6
7
8
9
10
11
12
fOSC = 10 MHz
13
Figure 1610. IDD2 vs VDD
I
DD3
(nA)
4.5
VDD (V)
(T A = 25
C)
5.0
5.5
100
120
140
160
180
200
220
240
260
280
Figure 1611. IDD3 vs VDD
ELECTRICAL DATA
S3C8444
1616
0
I
OL
(mA)
0.2
VOL1 (V)
0.4
(TA = 25
C)
0.6
0.8
1.0
VDD = 4.5 V
VDD = 5.5 V
1.2
2
4
6
8
10
12
14
16
18
Figure 1612. IOL vs VOL1
S3C8444
ELECTRICAL DATA
1617
0
I
OL
(mA)
0.2
VOL2 (V)
0.4
(TA = 25
C)
0.6
0.8
1.0
VDD = 4.5 V
VDD = 5.5 V
1.2
2
4
6
8
10
12
14
16
18
Figure 1613. IOL vs VOL2
ELECTRICAL DATA
S3C8444
1618
0
I
OH
(mA)
2.4
VOH2 (V)
3.0
(TA = 25
C)
3.6
4.2
4.8
VDD = 4.5 V
VDD = 5.5 V
5.4
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
Figure 1614. IOH vs VOH2
S3C8444
MECHANICAL DATA
171
17
MECHANICAL DATA
NOTE: Dimensions are in millimeters.
17.90
0.3
14.00
0.2
(1.00)
80-QFP-1420C
23.90
0.3
#80
(0.80)
#1
0.35
0.1
0.15 MAX
0.80
0.20
0.10 MAX
0.15
+0.10
- 0.05
0~8
2.65
0.10
3.00 MAX
0.05 MIN
0.80
0.20
20.00
0.2
0.80
Figure 171. S3C8444 QFP Standard Package Dimensions (in Millimeters)
MECHANICAL DATA
S3C8444
172
NOTE: Dimensions are in millimeters.
1
4
.
00
B
S
C
1
2
.
0
0
B
S
C
80-TQFP-1212-AN
14.00BSC
12.00BSC
#80
(1.25)
#1
0.50
0.17~0.27
0
.
6
5
0
.
1
5
0.10 MAX
0.09~0.20
0~7
1.00
0.05
1.20 MAX
0.05~0.15
0.25GAUGE PLANE
0.08 MAX M
Figure 172. S3C8444 TQFP Standard Package Dimensions (in Millimeters)
S3C8444
DEVELOPMENT TOOLS
181
18
DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. Two types of debugging
tools including hardware and software are provided: the in-circuit emulator, SMDS2, developed for S3C1, S3C7,
S3C8 families of microcontrollers, and even more sophisticated and powerful in-circuit emulator, SMDS2+, for
S3C7, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. In the future
SMDS2+ will replace SMDS2 and eventually SMDS2 will not be supported. Samsung also offers support
software that includes debugger, assembler, and a program for setting options.
DEVELOPMENT TOOLS VERSIONS
As of the date of this publication, two versions of the SMDS are being supported:
-- SMDS2 Version 5.3 (S/W) and SMDS2 Version 1.3 (H/W); last release: October, 1995.
-- SHINE Version 1.0 (S/W) and SMDS2+ Version 1.0 (H/W); last release: January, 1997.
SMDS V5.3
SMDS V5.3 is an assembly level debugger with user-friendly host interfacing that uses in-circuit
emulator,SMDS2.
SHINE
Samsung Host Interface for iN-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
sized, moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and
an auxiliary definition (DEF) file with device specific information.
SASM88
The SASM88 is an relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
DEVELOPMENT TOOLS
S3C8444
182
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device
automatically.
TARGET BOARDS
Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
IBM-PC AT
or
Compatible
Target
Application
System
Internal BUS
Main Board
Personality
Board
5-Volt
Power
Supply
Front
Panel
Board
TB8444
Target
Board
EVA
Chip
RS-232C
Target Cable
POD
Figure 181. SMDS Product Configuration (SMDS2)
S3C8444
DEVELOPMENT TOOLS
183
Bus
SMDS2+
RS-232C
POD
Target
Cable
PROM/MTP Writer Unit
RAM Break/Display Unit
Trace/Timer Unit
SAM8 Base Unit
Power Supply Unit
IBM-PC AT or Compatible
TB8444
Target
Board
EVA
Chip
Target
Application
System
Figure 182. SMDS Product Configuration (SMDS2+)
DEVELOPMENT TOOLS
S3C8444
184
TB8444 TARGET BOARD
The TB8444 target board is used for the S3C8444 microcontroller. It is supported by the SMDS2 or SMDS2+
development system.
TB8444
SM1296A
RESET1
To User_V
CC
Off
On
40-Pin Connector
2
1
39
40
25
1
J101
144 QFP
S3E8440
EVA Chip
GND
V
CC
CN1
AV
SS
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
AV
REF
SW1
+
Stop
+
Idle
U3
U1
40-Pin Connector
2
1
39
40
J102
External
Triggers
CH1
CH2
Figure 183. TB8444Target Board Configuration
S3C8444
DEVELOPMENT TOOLS
185
Table 181. Power Selection Settings for TB8444
'To User_Vcc' Settings
Operating Mode
Comments
OFF
ON
To User_Vcc
a
Target
System
SMDS2/SMDS2+
TB8444
V
CC
V
SS
V
CC
The SMDS2/SMDS2+ main
board supplies V
CC
to the
target board (evaluation chip)
and the target system.
OFF
ON
To User_Vcc
a
TB8444
Target
System
SMDS2/SMDS2+
External
V
CC
V
SS
V
CC
The SMDS2/SMDS2+ main
board supplies V
CC
only to
the target board (evaluation
chip). The target system must
have its own power supply.
NOTE: The following symbol in the 'To User_Vcc' Setting column indicates the electrical short configuration:
a
Table 182. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part
Comments
EXTERNAL
TRIGGERS
CH1
CH2
Connector from
external trigger
sources of the
application system
You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2/SMDS2+ breakpoint
and trace functions.
DEVELOPMENT TOOLS
S3C8444
186
Table 183. Analog Pin Connection Switch Settings (TB8444)
Analog Pin Switch
Operating Mode
DIP SW1: ON
TARGET
BOARD
TARGET
SYSTEM
ANALOG SIGNALS
DIP SW1: OFF
TARGET
SYSTEM
HOLES DRILLED
FOR DIRECT CONNECTION
ADC0
|
ADC7
TARGET
BOARD
NOTE: Analog signals coming into the target board can easily introduce noise into the analog converter circuit. This can
cause invalid conversion results. To reduce noise, you can use the analog pin switches to provide the shortest
possible path for analog signals. To do this, turn all DIP switches to the OFF position. Then, connect the analog
signal lines directly via the holes of the corresponding analog pins.
IDLE LED
The Green LED is ON when the evaluation chip(S3E8440) is in idle mode.
STOP LED
The Red LED is ON when the evaluation chip(S3E8440) is in stop mode.
S3C8444
DEVELOPMENT TOOLS
187
40-PIN CONNECTOR
J101
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
A9
P5.7
P5.5
P5.3
P5.1
VDD2
P2.6/TA
DR
DW
AS
TXD
PWM0
P3.1/TDCK/INT1
P3.3/TDG/INT3
P3.5
P3.7/
WAIT
P4.0/INT4
P4.2/INT6
P4.4/INT8
P4.6/INT10
A8
P5.6
P5.4
P5.2
P5.0
P2.7/TB
PM
DM
DS
PXD
PWM1
P3.0/TCCK/INT0
P3.2/TCG/INT2
P3.4
P3.6/CAP
VSS2
P4.1/INT5
P4.3/INT7
P4.5/INT9
P4.7/INT11
40-PIN CONNECTOR
J102
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
P7.0/ADC0
P7.1/ADC1
AVSS
P7.4/ADC4
P7.6/ADC6
P6.7
P6.5
P6.3
P6.1
NC(XIN)
VSS1
NC
EA
AD6
AD4
AD2
AD0
A15
A13
A11
AVREF
P7.2/ADC2
P7.3/ADC3
P7.5/ADC5
P7.7/ADC7
P6.6
P6.4
P6.2
P6.0
NC(XOUT)
NC
RESET
AD7
AD5
AD3
AD1
VDD1
A14
A12
A10
Figure 184. 40-Pin Connectors for TB8444 (S3C8444, 80-QFP Package)
DEVELOPMENT TOOLS
S3C8444
188
40-PIN CONNECTORS
TARGET BOARD
TARGET SYSTEM
Target Cable for 80 QFP Adapter
Part Name: CS80QF
Order Code: SM6501
1
2
39 40
41 42
79 80
80-QFP Adapter
Order Code: SM6402
J101
J102
NOTE: Two 40-pin flat cables can be used instead of the target cable and the 80-QFP adapter
to connect the target board and the target system.
Figure 185. TB8444 Cable for 80-QFP Adapter
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