1
Preliminary Data Sheet, Rev. 1.0
91-SR-011-05-8L
Mobile DiskOnChip G3
512Mbit/1Gbit Flash Disk with MLC NAND and
M-Systems' x2 Technology
Preliminary Data Sheet, June 2003
Highlights
Mobile DiskOnChip G3 is one of the industry's
most efficient storage solutions, using
Toshiba's 0.13
m Multi-Level Cell (MLC)
NAND flash technology and x2 technology
from M-Systems. MLC NAND flash
technology provides the smallest die size by
storing 2 bits of information in a single memory
cell. x2 technology enables MLC NAND to
achieve highly reliable, high-performance data
and code storage with a specially designed error
detection and correction mechanism, optimized
file management, and proprietary algorithms for
enhanced performance.
Further cost benefits derive from the
cost-effective architecture of Mobile
DiskOnChip G3, which includes a boot block
that can replace expensive NOR flash, and
incorporates both the flash array and an
embedded thin controller in a single die.
Mobile DiskOnChip G3 provides:
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core
Hardware protection and security-enabling
features
High capacity: single die - 512Mb (64MB),
dual die - 1Gb (128MB)
Device cascade capacity: up to 2Gb
(256MB)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
512Mb (64MB) capacity (single die):
48-pin TSOP-I package
85-ball FBGA 7x10 mm package
1Gb (128MB) capacity (dual die):
69-ball FBGA 9x12 mm package
Enhanced performance by implementation
of:
Multi-plane operation
DMA support
MultiBurst operation
Turbo operation
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) tailored for MLC NAND flash
technology
Maximized flash endurance with TrueFFS
6.1 (and higher)
Support for major mobile operating systems
(OSs), including Symbian OS, Pocket PC
2002/3, Smartphone 2002/3, Palm OS,
Nucleus, Linux, Windows CE, and more.
Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.
Mobile DiskOnChip G3
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Data Sheet, Rev. 1.0
91-SR-011-05-8L
Performance
MultiBurst read: 80 MB/sec
Erase: 30 MB/sec
Sustained read: 5 MB/sec
Sustained write: 1.1 MB/sec
Access time:
Normal: 55 nsec
Turbo: 33 nsec
MultiBurst: 25 nsec
Protection & Security-Enabling Features
16-byte Unique Identification (UID)
number
6KByte user-controlled One Time
Programmable (OTP) area
Two configurable hardware-protected
partitions for data and code:
Read-only mode
Write-only mode
One-Time Write mode (ROM-like)
partition
Protection key and LOCK# signal
Sticky Lock (SLOCK) to lock boot
partition
Protected Bad Block Table
Reliability and Data Integrity
Hardware- and software-driven, on-the-fly
EDC and ECC algorithms
4-bit Error Detection Code/Error Correction
Code (EDC/ECC), based on a patented
combination of BCH and Hamming code
algorithms, tailored for MLC NAND flash
technology
Guaranteed data integrity after power
failure
Transparent bad-block management
Dynamic and static wear-leveling
Boot Capability
Programmable Boot Block with XIP
capability to replace boot NOR
2KB for 512Mb devices
4KB for 1Gb devices
Download Engine (DE) for automatic
download of boot code from Programmable
Boot Block
Boot options:
CPU initialization
Platform initialization
OS boot
Asynchronous Boot mode to boot from
ARM-based CPUs, e.g. XScale, TI OMAP,
without the need for external glue logic
Exceptional boot performance with
MultiBurst operation and DMA support
enhanced by external clock
Hardware Compatibility
Configurable interface: simple NOR-like or
multiplexed address/data interface
CPU compatibility, including:
ARM-based CPUs
Texas Instruments OMAP
Intel StrongARM/XScale
Motorola DragonBall MX1
Qualcomm MSMxxxx
AMD Alchemy
Motorola PowerPCTM MPC8xx
Philips PR31700
Hitachi SuperHTM SH-x
NEC VR Series
Supports 8-, 16- and 32-bit architectures
Mobile DiskOnChip G3
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Data Sheet, Rev. 1.0
91-SR-011-05-8L
TrueFFS
Software
Full hard-disk read/write emulation for
transparent file system management
Patented TrueFFS
Flash file system management
Automatic block management
Data management to maximize the limit
of typical flash life expectancy
Dynamic virtual mapping
Dynamic and static wear-leveling
Programming, duplicating, testing and
debugging tools available in source code
Operating Environment
Wide OS support, including:
Symbian OS (EPOC)
Pocket PC 2002/3
Smartphone 2002/3
Palm OS
Nucleus
Windows CE
Linux
TrueFFS Software Development Kit (SDK)
for quick and easy support for proprietary
OSs, or OS-less environment
TrueFFS Boot Software Development Kit
(BDK)
Power Requirements
Operating voltage
Core: 2.5V to 3.6V
I/O: 1.65 to 2.0V; or 2.5V to 3.6V
(auto-detect)
Current
Active: 10 mA
Deep Power-Down: 10
A (512Mb)
20
A (1Gb)
Capacity and Packaging
512Mb (64MB) capacity (single die):
Device cascading option for up to four
devices (2Gb)
48-pin TSOP-I package:
20x12x1.2 mm (width x length x height)
85-ball FBGA package:
7x10x1.2 mm (width x length x height)
Pinout compatible with DiskOnChip
Plus TSOP-I products
Ballout compatible with DiskOnChip
Plus FBGA products: 9x12 mm
1Gb (128MB) capacity (dual die):
Device cascading option for up to two
devices (2Gb)
69-ball FBGA package:
9x12x1.4 mm (width x length x height)
Ballout compatible with Mobile
DiskOnChip G3 512Mb and
DiskOnChip Plus FBGA products:
9x12 mm
Mobile DiskOnChip G3
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Data Sheet, Rev. 1.0
91-SR-011-05-8L
T
ABLE OF
C
ONTENTS
1.
Introduction ............................................................................................................................... 5
2.
Product Overview...................................................................................................................... 6
2.1
Product Description ............................................................................................................ 6
2.2
512Mb Standard Interface .................................................................................................. 7
2.2.1
Pin/Ball Diagrams................................................................................................................. 7
2.2.2
System Interface .................................................................................................................. 9
2.2.3
Signal Description .............................................................................................................. 10
2.3
1Gb Standard Interface .................................................................................................... 14
2.3.1
Ball Diagram ....................................................................................................................... 14
2.3.2
System Interface ................................................................................................................ 15
2.3.3
Signal Description .............................................................................................................. 16
2.4
512Mb Multiplexed Interface ............................................................................................ 18
2.4.1
Pin/Ball Diagram................................................................................................................. 18
2.4.2
System Interface ................................................................................................................ 20
2.4.3
Signal Description .............................................................................................................. 21
2.5
1Gb Multiplexed Interface................................................................................................. 25
2.5.1
Ball Diagram ....................................................................................................................... 25
2.5.2
System Interface ................................................................................................................ 26
2.5.3
Signal Description .............................................................................................................. 27
3.
Theory of Operation ................................................................................................................ 29
3.1
Overview........................................................................................................................... 29
3.2
System Interface............................................................................................................... 30
3.2.1
Standard (NOR-Like) Interface........................................................................................... 30
3.2.2
Multiplexed Interface .......................................................................................................... 30
3.3
Configuration Interface ..................................................................................................... 31
3.4
Protection and Security-Enabling Features ...................................................................... 31
3.4.1
Read/Write Protection ........................................................................................................ 31
3.4.2
Unique Identification (UID) Number ................................................................................... 31
3.4.3
One-Time Programmable (OTP) Area ............................................................................... 32
3.4.4
One-Time Write (ROM-Like) Partition ................................................................................ 32
3.4.5
Sticky Lock (SLOCK).......................................................................................................... 32
3.5
Programmable Boot Block with eXecute In Place (XIP) Functionality.............................. 32
3.6
Download Engine (DE) ..................................................................................................... 33
3.7
Error Detection Code/Error Correction Code (EDC/ECC) ................................................ 33
Mobile DiskOnChip G3
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Data Sheet, Rev. 1.0
91-SR-011-05-8L
3.8
Data Pipeline .................................................................................................................... 33
3.9
Control and Status............................................................................................................ 33
3.10
Flash Architecture............................................................................................................. 34
4.
x2 Technology ......................................................................................................................... 36
4.1
MultiBurst Operation......................................................................................................... 36
4.2
DMA Operation................................................................................................................. 38
4.3
Combined MultiBurst Mode and DMA Operation ............................................................. 39
4.4
Turbo Operation ............................................................................................................... 39
5.
Hardware Protection ............................................................................................................... 40
5.1
Method of Operation......................................................................................................... 40
5.2
Low-Level Structure of the Protected Area....................................................................... 41
6.
Modes of Operation................................................................................................................. 43
6.1
Normal Mode .................................................................................................................... 44
6.2
Reset Mode ...................................................................................................................... 44
6.3
Deep Power-Down Mode ................................................................................................. 44
7.
TrueFFS Technology............................................................................................................... 46
7.1
General Description.......................................................................................................... 46
7.1.1
Built-In Operating System Support..................................................................................... 47
7.1.2
TrueFFS Software Development Kit (SDK)........................................................................ 47
7.1.3
File Management................................................................................................................ 47
7.1.4
Bad Block Management ..................................................................................................... 47
7.1.5
Wear-Leveling .................................................................................................................... 47
7.1.6
Power Failure Management ............................................................................................... 48
7.1.7
Error Detection/Correction.................................................................................................. 48
7.1.8
Special Features Through I/O Control (IOCTL) Mechanism.............................................. 49
7.1.9
Compatibility ....................................................................................................................... 49
7.2
8KB Memory Window ....................................................................................................... 49
8.
Register Descriptions ............................................................................................................. 50
8.1
Definition of Terms ........................................................................................................... 50
8.2
Reset Values .................................................................................................................... 50
8.3
No Operation (NOP) Register........................................................................................... 51
8.4
Chip Identification (ID) Register [0:1]................................................................................ 51
8.5
Test Register .................................................................................................................... 51
8.6
Bus Lock Register ............................................................................................................ 52
8.7
Endian Control Register ................................................................................................... 53
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