Preliminary Data Sheet, Rev. 0.3

93-SR-009-8L

Mobile DiskOnChip P3

256Mb Flash Disk with

M-Systems' x2 Technology

Preliminary Data Sheet, June 2003

Highlights

Mobile DiskOnChipTM P3, a member of
M-Systems' DiskOnChipTM family of
optimized memory solutions for new-generation
mobile handsets, provides high performance
and reliability using NAND flash technology. It
combines Toshiba's cutting-edge 0.13 micron
NAND flash manufacturing process enhanced
for performance and reliability with
M-Systems' x2 technology.
Mobile DiskOnChip P3 optimizes real estate
and cost structure by incorporating the flash
array and an embedded thin controller in a
single die. A boot block can be used to boot the
OS or initialize the CPU/platform, replacing
expensive NOR flash and further reducing
memory system costs.
Mobile DiskOnChip P3 provides:

Flash disk for both code and data storage

Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core

Hardware protection and security-enabling
features

High capacity: 256Mbit (32MByte)

Device cascading option: up to 1Gbit
(128MByte)

Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface

Small form factors:

48-pin TSOP-I package

85-ball FBGA 7x10x1.2 mm package

Enhanced performance with:

Multi-plane operation

DMA support

MultiBurst operation

Turbo operation

Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC)

Maximized flash endurance with TrueFFS

6.1 (and higher) flash management software

Support for major mobile OSs, including:
Symbian OS, Pocket PC 2002/3,
Smartphone 2002/3, Palm OS, Nucleus,
Linux, Windows CE

Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Performance

MultiBurst read: 80 MB/sec

Sustained read: 5 MB/sec

Sustained write: 2.5 MB/sec

Access time:

Normal: 55 nsec

Turbo: 33 nsec

MultiBurst: 25 nsec

Protection & Security-Enabling Features

16-byte Unique Identification (UID)
number

6KByte user-controlled One Time
Programmable (OTP) area

Two configurable hardware-protected
partitions for data and code:

Read-only mode

Write-only mode

One-Time Write mode (ROM-like)
partition

Protection key and LOCK# signal

Sticky Lock (SLOCK) to lock boot
partition

Protected Bad Block Table

Reliability and Data Integrity

Hardware- and software-driven, on-the-fly
EDC and ECC algorithms

4-bit Error Detection Code/Error Correction
Code (EDC/ECC), based on a patented
combination of BCH and Hamming code
algorithms

Guaranteed data integrity after power
failure

Transparent bad-block management

Dynamic and static wear-leveling

Boot Capability

2KB Programmable Boot Block with XIP
capability to replace boot NOR

Download Engine (DE) for automatic
download of boot code from Programmable
Boot Block

Boot options:

CPU initialization

Platform initialization

OS boot

Asynchronous Boot mode to boot from
ARM-based CPUs, e.g. XScale, TI OMAP,
without the need for external glue logic

Exceptional boot performance with
MultiBurst operation and DMA support
enhanced by external clock

Hardware Compatibility

Configurable interface: simple NOR-like or
multiplexed address/data interface

CPU compatibility, including:

ARM-based CPUs

Texas Instruments OMAP

Intel StrongARM/XScale

Motorola DragonBall MX1

Qualcomm MSMxxxx

AMD Alchemy

Motorola PowerPCTM MPC8xx

Philips PR31700

Hitachi SuperHTM SH-x

NEC VR Series

Supports 8-, 16- and 32-bit architectures

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

TrueFFS

Software

Full hard-disk read/write emulation for
transparent file system management

Patented TrueFFS

Flash file system management

Automatic block management

Data management to maximize the limit
of typical flash life expectancy

Dynamic virtual mapping

Dynamic and static wear-leveling

Programming, duplicating, testing and
debugging tools available in source code

Operating Environment

Wide OS support, including:

Symbian OS (EPOC)

Pocket PC 2002/3

Smartphone 2002/3

Palm OS

Nucleus

Windows CE

Linux

TrueFFS Software Development Kit (SDK)
for quick and easy support for proprietary
OSs, or OS-less environment

TrueFFS Boot Software Development Kit
(BDK)

Power Requirements

Operating voltage

Core: 2.5V to 3.6V

I/O: 1.65 to 2.0V; or 2.5V to 3.6V
(auto-detect)

Current

Active: 10 mA

Deep Power-Down: 10

µA

Capacity and Packaging

256Mb (32MB) capacity

Device cascading option for up to four
devices (1Gb)

48-pin TSOP-I package:
20x12x1.2 mm (width x length x height)

85-ball FBGA package:
7x10x1.2 mm (width x length x height)

Pinout compatible with DiskOnChip Plus
TSOP-I products

Ballout compatible with DiskOnChip Plus
69-ball FBGA products: 9x12x1.4 mm

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

ABLE OF

ONTENTS

Introduction ............................................................................................................................... 5

Product Overview...................................................................................................................... 6

2.1

Product Description ............................................................................................................ 6

2.2

Standard Interface .............................................................................................................. 7

2.2.1

Pin/Ball Diagrams................................................................................................................. 7

2.2.2

System Interface .................................................................................................................. 9

2.2.3

Signal Description .............................................................................................................. 10

2.3

Multiplexed Interface ........................................................................................................ 14

2.3.1

Pin/Ball Diagram................................................................................................................. 14

2.3.2

System Interface ................................................................................................................ 16

2.3.3

Signal Description .............................................................................................................. 17

Theory of Operation ................................................................................................................ 21

3.1

Overview........................................................................................................................... 21

3.2

System Interface............................................................................................................... 22

3.2.1

Standard (NOR-Like) Interface........................................................................................... 22

3.2.2

Multiplexed Interface .......................................................................................................... 22

3.3

Configuration Interface ..................................................................................................... 23

3.4

Protection and Security-Enabling Features ...................................................................... 23

3.4.1

Read/Write Protection ........................................................................................................ 23

3.4.2

Unique Identification (UID) Number ................................................................................... 23

3.4.3

One-Time Programmable (OTP) Area ............................................................................... 24

3.4.4

One-Time Write (ROM-Like) Partition ................................................................................ 24

3.4.5

Sticky Lock (SLOCK).......................................................................................................... 24

3.5

Programmable Boot Block with eXecute In Place (XIP) Functionality.............................. 24

3.6

Download Engine (DE) ..................................................................................................... 25

3.7

Error Detection Code/Error Correction Code (EDC/ECC) ................................................ 25

3.8

Data Pipeline .................................................................................................................... 25

3.9

Control and Status............................................................................................................ 25

3.10

Flash Architecture............................................................................................................. 26

x2 Technology ......................................................................................................................... 28

4.1

MultiBurst Operation......................................................................................................... 28

4.2

DMA Operation................................................................................................................. 30

4.3

Combined MultiBurst Mode and DMA Operation ............................................................. 31

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

4.4

Turbo Operation ............................................................................................................... 31

Hardware Protection ............................................................................................................... 32

5.1

Method of Operation......................................................................................................... 32

5.2

Low-Level Structure of the Protected Area....................................................................... 33

Modes of Operation................................................................................................................. 35

6.1

Normal Mode .................................................................................................................... 36

6.2

Reset Mode ...................................................................................................................... 36

6.3

Deep Power-Down Mode ................................................................................................. 36

TrueFFS Technology............................................................................................................... 38

7.1

General Description.......................................................................................................... 38

7.1.1

Built-In Operating System Support..................................................................................... 39

7.1.2

TrueFFS Software Development Kit (SDK)........................................................................ 39

7.1.3

File Management................................................................................................................ 39

7.1.4

Bad Block Management ..................................................................................................... 39

7.1.5

Wear-Leveling .................................................................................................................... 39

7.1.6

Power Failure Management ............................................................................................... 40

7.1.7

Error Detection/Correction.................................................................................................. 40

7.1.8

Special Features Through I/O Control (IOCTL) Mechanism.............................................. 41

7.1.9

Compatibility ....................................................................................................................... 41

7.2

8KB Memory Window ....................................................................................................... 41

Register Descriptions ............................................................................................................. 42

8.1

Definition of Terms ........................................................................................................... 42

8.2

Reset Values .................................................................................................................... 42

8.3

No Operation (NOP) Register........................................................................................... 43

8.4

Chip Identification (ID) Register [0:1]................................................................................ 43

8.5

Test Register .................................................................................................................... 43

8.6

Bus Lock Register ............................................................................................................ 44

8.7

Endian Control Register ................................................................................................... 45

8.8

DiskOnChip Control Register/Control Confirmation Register ........................................... 46

8.9

Device ID Select Register................................................................................................. 47

8.10

Configuration Register...................................................................................................... 47

8.11

Interrupt Control Register ................................................................................................. 48

8.12

Interrupt Status Register................................................................................................... 49

8.13

Output Control Register.................................................................................................... 50

8.14

DPD Control Register ....................................................................................................... 51

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.15

DMA Control Register [1:0]............................................................................................... 52

8.16

MultiBurst Mode Control Register..................................................................................... 54

Booting from Mobile DiskOnChip P3..................................................................................... 55

9.1

Introduction....................................................................................................................... 55

9.2

Boot Procedure in PC-Compatible Platforms ................................................................... 55

9.3

Boot Replacement ............................................................................................................ 56

9.3.1

PC Architectures ................................................................................................................ 56

9.3.2

Non-PC Architectures......................................................................................................... 57

9.3.3

Asynchronous Boot Mode .................................................................................................. 57

10.

Design Considerations ........................................................................................................... 58

10.1

General Guidelines........................................................................................................... 58

10.2

Standard NOR-Like Interface ........................................................................................... 59

10.3

Multiplexed Interface ........................................................................................................ 60

10.4

Connecting Control Signals .............................................................................................. 60

10.4.1

Standard Interface.............................................................................................................. 60

10.4.2

Multiplexed Interface .......................................................................................................... 61

10.5

Implementing the Interrupt Mechanism ............................................................................ 62

10.5.1

Hardware Configuration ..................................................................................................... 62

10.5.2

Software Configuration....................................................................................................... 62

10.6

Device Cascading............................................................................................................. 63

10.7

Boot Replacement ............................................................................................................ 64

10.8

Platform-Specific Issues ................................................................................................... 65

10.8.1

Wait State ........................................................................................................................... 65

10.8.2

Big and Little Endian Systems............................................................................................ 65

10.8.3

Busy Signal......................................................................................................................... 65

10.8.4

Working with 8/16/32-Bit Systems...................................................................................... 65

10.9

Design Environment ......................................................................................................... 67

11.

Product Specifications ........................................................................................................... 68

11.1

Environmental Specifications ........................................................................................... 68

11.1.1

Operating Temperature ...................................................................................................... 68

11.1.2

Thermal Characteristics ..................................................................................................... 68

11.1.3

Humidity.............................................................................................................................. 68

11.1.4

Endurance .......................................................................................................................... 68

11.2

Electrical Specifications.................................................................................................... 68

11.2.1

Absolute Maximum Ratings................................................................................................ 68

11.2.2

Capacitance........................................................................................................................ 69

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.2.3

DC Electrical Characteristics Over Operating Range ........................................................ 69

11.2.4

AC Operating Conditions.................................................................................................... 70

11.3

Timing Specifications........................................................................................................ 71

11.3.1

Read Cycle Timing Standard Interface .............................................................................. 71

11.3.2

Write Cycle Timing Standard Interface .............................................................................. 73

11.3.3

Read Cycle Timing Multiplexed Interface........................................................................... 74

11.3.4

Write Cycle Timing Multiplexed Interface........................................................................... 75

11.3.5

Read Cycle Timing MultiBurst ............................................................................................ 76

11.3.6

Power Supply Sequence .................................................................................................... 77

11.3.7

Power-up Timing ................................................................................................................ 77

11.3.8

Interrupt Timing .................................................................................................................. 79

11.3.9

DMA Request Timing ......................................................................................................... 79

11.4

Mechanical Dimensions.................................................................................................... 80

12.

Ordering Information............................................................................................................... 82

How to Contact Us ........................................................................................................................ 83

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

1. I

NTRODUCTION

This data sheet includes the following sections:
Section 1:

Overview of data sheet contents

Section 2:

Product overview, including a brief product description, ball diagrams and signal
descriptions

Section 3:

Theory of operation for the major building blocks

Section 4:

Major features and benefits of x2 technology

Section 5:

Detailed description of hardware protection and security-enabling features

Section 6:

Modes of operation

Section 7:

TrueFFS technology, including power failure management and 8KByte memory
window

Section 8: Register

descriptions

Section 9:

Booting from Mobile DiskOnChip P3

Section 10: Hardware and software design considerations

Section 11: Environmental, electrical, timing and product specifications

Section 12: Information on ordering Mobile DiskOnChip P3

For additional information on M-Systems' flash disk products, please contact one of the offices
listed on the back page.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2. P

RODUCT

VERVIEW

2.1 Product

Description

Mobile DiskOnChip P3, packed in the smallest available FBGA package with 256Mb (32MB)
capacity, is a single-die device with an embedded thin flash controller and flash memory. It uses
Toshiba's cutting-edge, 0.13 micron NAND-based flash manufacturing process, enhanced by
M-Systems' proprietary x2 technology.
M-Systems' x2 technology provides performance enhancement with multi-plane operation, DMA
support, turbo operation and MultiBurst operation. The combination of NAND flash and
x2 technology results in a low-cost, minimal-sized flash disk that achieves unsurpassed reliability
levels and enhanced performance.
This breakthrough in performance, size and cost makes Mobile DiskOnChip P3 the ideal solution
for mobile product manufacturers who require high-capacity, small size, high-performance, and
above all, high-reliability storage to enable applications such as enhanced Multimedia Messaging
Service (MMS), gaming, video and Personal Information Management (PIM) on mobile handsets
and Personal Digital Assistants (PDAs).
Mobile DiskOnChip P3 content protection and security-enabling features offer several benefits.
Two write- and read-protected partitions, with both software- and hardware-based protection, can
be configured independently for maximum design flexibility. The 16-byte Unique ID (UID)
identifies each flash device, eliminating the need for a separate ID device on the motherboard. The
6KB One Time Programmable (OTP) area, written to once and then locked to prevent data and code
from being altered, is ideal for storing customer and product-specific information.
Mobile DiskOnChip P3 256Mb has a 2KB Programmable Boot Block. This block provides eXecute
In Place (XIP) functionality, enabling Mobile DiskOnChip P3 to replace the boot device and
function as the only non-volatile memory device on-board. Eliminating the need for an additional
boot device reduces hardware expenditures, board real estate, programming time, and logistics.
M-Systems' patented TrueFFS software technology fully emulates a hard disk to manage the files
stored on Mobile DiskOnChip P3. This transparent file system management enables read/write
operations that are identical to a standard, sector-based hard disk. In addition, TrueFFS employs
patented methods, such as virtual mapping, dynamic and static wear-leveling, and automatic block
management to ensure high data reliability and to maximize flash life expectancy.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2.2 Standard

Interface

2.2.1 Pin/Ball

Diagrams

See Figure 1 and Figure 2 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the standard
interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future
use and should not be connected.
Note: Mobile DiskOnChip P3 is designed as a drop-in replacement for second-generation (G2)

DiskOnChip Plus products, assuming that the latter were integrated according to migration
guide guidelines. Refer to application note AP-DOC-067, Preparing your PCB Footprint for
the DiskOnChip BGA Migration Path, for further information.

TSOP-I Package

29
28
27

35
34
33
32
31
30

40
39
38
37

44
43
42
41

47
46
45

VSS
IRQ#

D13

D14

D15

CLK

D10

D11

D12

VCCQ

VSS

ID1

BUSY#

VSS

Mobile DiskOnChip P3 256Mb (32MB)

48-Pin TSOP-I

1
2

RSTIN#

CE#

A12

OE#

WE#

A10

A11

VCC

VSS

RSRVD

A0/DPD

LOCK#

IF_CFG

DMARQ#

ID0

Figure 1: TSOP-I Pinout for Standard Interface (Mobile DiskOnChip P3 256Mb)

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2.2.3 Signal

Description

Mobile DiskOnChip P3 TSOP-I and FBGA packages support identical signals. The related pin and
ball designations are listed in the signal descriptions, presented in logic groups, in Table 1 and
Table 2.

TSOP-I Package

Table 1: Signal Descriptions for Standard Interface (Mobile DiskOnChip P3 256Mb TSOP-I Package)

Signal Pin

No.

Input

Type

Description

Signal

Type

System Interface

A[12:6]
A[5:0]

5-11

14-19

Address bus. A0 is multiplexed with the DPD pin.

Input

D[15:8]

46-39

ST, R8 Data bus, high byte. Not used and may be left

floating when IF_CFG is set to 0 (8-bit mode).

Input/

Output

D[7:0]

35-28

Data bus, low byte.

Input/

Output

CE#

Chip Enable, active low

Input

WE#

Write Enable, active low

Input

OE#

Output Enable, active low

Input

Configuration

ID[1:0]

26, 24

Identification. Configuration control to support up to
four chips cascaded in the same memory window.
Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used

for single-chip configuration

Chip 2 = ID1, ID0 = VSS, VCCQ (0,1)
Chip 3 = ID1, ID0 = VCCQ, VSS (1,0)
Chip 4 = ID1, ID0 = VCCQ, VCCQ (1,1)

Input

LOCK#

Lock, active low. When active, provides full
hardware data protection of selected partitions.

Input

IF_CFG

Interface Configuration, 1(VCCQ) for 16-bit
interface mode, 0 (VSS) for 8-bit interface mode.

Input

Control

BUSY#

Busy, active low, open drain. Indicates that
DiskOnChip is initializing and should not be
accessed. A 10 K

pull-up resistor is required if

this pin drives an input. A 10 K

pull-up resistor is

recommended even if this pin is not used.

Output

RSTIN#

Reset, active low.

Input

CLK 38

System

Clock.

Input

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Signal Pin

No.

Input

Type

Description

Signal

Type

DMARQ# 21 OD

DMA Request, active low. A 10 K

pull-up resistor

is required if this pin drives an input. A 10 K

pull-

up resistor is recommended even if this pin is not
used.

Output

IRQ# 47

Interrupt Request, active low. A 10 K

pull-up

resistor is required if this pin drives an input. A 10
K

pull-up resistor is recommended even if this pin

is not used.

Output

DPD

Deep Power-Down. Used to enter and exit Deep
Power-Down mode. This pin is assigned A0
instead of DPD when working in 8-bit mode.

Input

Power

VCC

Device core power supply. Requires a 10 nF and
0.1 µF capacitor.

Supply

VCCQ

I/O power supply. Sets the logic 1 voltage level
range of I/O pins. VCCQ may be either 2.5V to
3.6V or 1.65V to 2.0V. Requires a 10 nF and
0.1 µF capacitor.

Supply

VSS

13, 25, 36, 48

Ground. All VSS pins must be connected.

Supply

Other

RSRVD

Reserved. All reserved signals are not connected
internally and must be left floating to guarantee
forward compatibility with future products.

The following abbreviations are used: IN - Standard (non-Schmidt) input, ST - Schmidt Trigger input, OD - Open drain output, R8 - Nominal
22K

pull-up resistor, enabled only for 8-bit interface mode (IF_CFG input is 0)

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

7x10 FBGA Package

Table 2: Signal Descriptions for Standard Interface (Mobile DiskOnChip P3 256Mb 7x10 FBGA Package)

Signal Ball

No.

Input

Type

Description

Signal

Type

System Interface

A[12:11]
A[10:8]
A[7:4]
A[3:0]

D7, C7

F6, E6, C6

C2, D2, E2, F2
D1, E1, F1, G1

Address bus. A0 is multiplexed with the DPD ball.

Input

D[15:14]
D[13:12]
D[11:8]

H7, K7

H6, J6

K4, J3, H3, K2

ST, R8 Data bus, high byte. Not used and may be left

floating when IF_CFG is set to 0 (8-bit mode).

Input/

Output

D[7:6]
D[5:3]
D[2:0]

J7, G6

K6, H5, H4

K3, G3, J2

Data bus, low byte.

Input/

Output

CE#

Chip Enable, active low

Input

OE#

Write Enable, active low

Input

WE#

Output Enable, active low

Input

Configuration

ID[1:0]

G8, F7

Identification. Configuration control to support up to
four chips cascaded in the same memory window.
Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used

for single chip configuration

Chip 2 = ID1, ID0 = VSS, VCCQ (0,1)
Chip 3 = ID1, ID0 = VCCQ, VSS (1,0)
Chip 4 = ID1, ID0 = VCCQ, VCCQ (1,1)

Input

LOCK#

Lock, active low. When active, provides full
hardware data protection of selected partitions.

Input

IF_CFG

Interface Configuration, 1 (VCCQ) for 16-bit
interface mode, 0 (VSS) for 8-bit interface mode.

Input

Control

BUSY#

Busy, active low, open drain. Indicates that
DiskOnChip is initializing and should not be
accessed. A 10 K

pull-up resistor is required if

this ball drives an input. A 10 K

pull-up resistor is

recommended even if this ball is not used.

Output

RSTIN#

Reset, active low.

Input

CLK K5

System

Clock.

Input

DMARQ# G7 OD

DMA Request, active low. A 10 K

pull-up resistor

is required if this ball drives an input. A 10 K

pull-

up resistor is recommended even if this ball is not
used.

Output

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Signal Ball

No.

Input

Type

Description

Signal

Type

IRQ# F8

Interrupt Request, active low. A 10 K

pull-up

resistor is required if this ball drives an input. A 10
K

pull-up resistor is recommended even if this

ball is not used.

Output

DPD

Deep Power-Down. Used to enter and exit Deep
Power-Down mode. This ball is assigned A0
instead of DPD when working in 8-bit mode.

Input

Power

VCC

Device supply. Requires a 10 nF and 0.1 µF
capacitor.

Supply

VCCQ

I/O power supply. Sets the logic 1 voltage level
range of I/O balls. VCCQ may be either 2.5V to
3.6V or 1.65V to 2.0V. Requires a 10 nF and
0.1 µF capacitor.

Supply

VSS

G2, J8

Ground. All VSS balls must be connected.

Supply

Other

RSRVD

See Figure 2

Reserved. All reserved signals are not connected
internally and must be left floating to guarantee
forward compatibility with future products.

Mechanical. These balls are for mechanical
placement, and are not connected internally.

Alignment. This ball is for device alignment and is
not connected internally.

The following abbreviations are used: IN - Standard (non-Schmidt) input, ST - Schmidt Trigger input, OD - Open drain output, R8 - Nominal
22K

pull-up resistor, enabled only for 8-bit interface mode (IF_CFG input is 0)

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2.3 Multiplexed

Interface

2.3.1 Pin/Ball

Diagram

See Figure 4 and Figure 5 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the multiplexed
interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future
use and should not be connected.
Note: Mobile DiskOnChip P3 is designed as a drop-in replacement for second-generation (G2)

TSOP-I Package

29
28
27

35
34
33
32
31
30

40
39
38
37

44
43
42
41

47
46
45

VSS
IRQ#

AD13

AD14

AD15

CLK

AD8

AD9

AD10

AD11

AD12

VCCQ

AD5

AD6

AD7

GND

AD1

AD2

AD3

AD4

AVD#

BUSY#

AD0

VSS

Mobile DiskOnChip P3 256Mb

48-Pin TSOP-I

1
2

RSTIN#

CE#

VSS

OE#

WE#

VSS

Vcc

VSS

DPD

VSS

LOCK#

VCCQ

DMARQ#

ID0

Figure 4: Pinout for Multiplexed Interface (Mobile DiskOnChip P3 256Mb TSOP-I Package)

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2.3.3 Signal

Description

Mobile DiskOnChip P3 256Mb TSOP-I and 7x10 FBGA packages support identical signals in the
multiplexed interface. The related pin/ball designations are listed in the signal descriptions,
presented in logic groups, in Table 3 and Table 4.

TSOP-I Package

Table 3: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip P3 256Mb TSOP-I Package)

Signal Pin

No.

Input

Type

Description

Signal

Type

System Interface

AD[15:0] 28-35,

39-46

Multiplexed

bus. Address and data signals.

Input/

Output

CE#

ST Chip Enable, active low.

Input

WE#

ST Write Enable, active low.

Input

OE#

ST Output Enable, active low.

Input

Configuration

AVD#

ST Set multiplexed interface.

Input

ID0 24

Identification.

Configuration control to support up to two chips

cascaded in the same memory window.
Chip 1 = ID0 = VSS; must be used for single-chip

configuration

Chip 2 = ID0 = VCCQ

Input

LOCK#

ST Lock, active low. When active, provides full hardware data

protection of selected partitions.

Input

Control

BUSY#

OD Busy, active low, open drain. Indicates that DiskOnChip is

initializing and should not be accessed.
A 10 K

pull-up resistor is required if this pin drives an input.

A 10 K

pull-up resistor is recommended even if this pin is

not used.

Output

RSTIN#

ST Reset, active low.

Input

CLK

ST System Clock.

Input

DMARQ# 21 OD

DMA Request, active low. A 10 K

pull-up resistor is required

if this pin drives an input. A 10 K

pull-up resistor is

recommended even if this pin is not used.

IRQ# 47

Interrupt Request, active low. A 10 K

pull-up resistor is

required if this pin drives an input. A 10 K

pull-up resistor is

recommended even if this pin is not used.

Output

DPD

ST Deep Power-Down. Used to enter and exit Deep Power-Down

mode.

Input

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

7x10 FBGA Package

Table 4: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip P3 7x10 FBGA Package)

Signal

Ball No.

Input

Type

Description

Signal

Type

System Interface

AD[15:14]
AD[13:12]
AD[11:9]
AD[8:6]
AD[5:3]
AD[2:0]

H7, K7

H6, J6

K4, J3, H3

K2, J7, G6

K6, H5, H4

K3, G3, J2

ST Multiplexed bus. Address and data signals

Input/

Output

CE#

ST Chip Enable, active low

Input

OE#

ST Write Enable, active low

Input

WE#

ST Output Enable, active low

Input

Configuration

AVD#

ST Set multiplexed interface

Input

ID0 F7

Identification.

Configuration control to support up to two chips

cascaded in the same memory window.
Chip 1 = ID0 = VSS; must be used for single-chip

configuration

Chip 2 = ID0 = VCC

Input

LOCK#

ST Lock, active low. When active, provides full hardware data

protection of selected partitions.

Input

Control

BUSY#

OD Busy, active low, open drain. Indicates that DiskOnChip is

initializing and should not be accessed A 10 K

pull-up

resistor is required if this ball drives an input. A 10 K

pull-up

resistor is recommended even if this ball is not used.

Output

RSTIN#

ST Reset, active low.

Input

CLK

ST System Clock.

Input

DMARQ# G7

DMA Request, active low. A 10 K

pull-up resistor is required

if this ball drives an input. A 10 K

pull-up resistor is

recommended even if this ball is not used.

Output

IRQ# F8

Interrupt Request, active low. A 10 K

pull-up resistor is

required if this ball drives an input. A 10 K

pull-up resistor is

recommended even if this ball is not used.

Output

DPD

ST Deep Power-Down. Used to enter and exit Deep Power-

Down mode.

Input

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Signal

Ball No.

Input

Type

Description

Signal

Type

Power

VCC

Device core supply. Requires a 10 nF and 0.1 µF capacitor. Supply

VCCQ

J5, F3

I/O power supply. Sets the logic 1 voltage level range of I/O
balls. VCCQ may be either 2.5V to 3.6V or 1.65V to 2.0V.
Requires a 10 nF and 0.1 µF capacitor.

Supply

VSS G2,J8,

D7,C7,F6,E6,

C6,C2,D2,E2
,F2,D1,E1,F1

Ground. All VSS pins must be connected.

Supply

Other

RSRVD

See Figure 5

Reserved. All reserved signals are not connected internally
and must be left floating to guarantee forward compatibility
with future products.

Mechanical. These balls are for mechanical placement, and
are not connected internally.

Alignment. This ball is for device alignment and is not
connected internally.

The following abbreviations are used: IN - Standard (non-Schmidt) input, ST - Schmidt Trigger input, OD - Open drain output

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

3. T

HEORY OF

PERATION

3.1 Overview

Mobile DiskOnChip P3 consists of the following major functional blocks, as shown in Figure 7.

*ADDR[0] and DPD are multiplexed on the same ball/pin.

Figure 7: Mobile DiskOnChip P3 Simplified Block Diagram, Standard Interface

These components are described briefly below and in more detail in the following sections.
· System Interface for the host interface.
· Configuration Interface for configuring Mobile DiskOnChip P3 to operate in 8-bit, 16-bit or

32-bit mode, cascaded configuration, hardware read/write protection and entering/exiting Deep
Power-Down mode.

· Read/Write Protection and OTP for advanced data/code security and protection.
· Programmable Boot Block with XIP functionality enhanced with a Download Engine (DE)

for system initialization capability.

· Error Detection and Error Correction Code (EDC/ECC) for on-the-fly error handling.
· Data Pipeline through which the data flows from the system to the NAND flash arrays.
· Control & Status block that contains registers responsible for transferring the address, data

and control information between the TrueFFS driver and the flash media

· Flash Interface that interfaces to two NAND flash planes.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

· Bus Control for translating the host bus address, and data and control signals into valid NAND

flash signals.

· Address Decoder to enable the relevant unit inside the DiskOnChip controller, according to

the address range received from the system interface.

3.2 System

Interface

3.2.1 Standard (NOR-Like) Interface

The system interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-
like) interface to Mobile DiskOnChip P3, enabling it to interface with various CPU interfaces, such
as a local bus, ISA bus, NOR interface, SRAM interface, EEPROM interface or any other
compatible interface. In addition, the EEPROM-like interface enables direct access to the
Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system
initialization.
A 13-bit wide address bus enables access to the Mobile DiskOnChip 8KB memory window (as
shown in Section 7.2). A 16-bit internal data bus is supported by parallel access to two 128Mb flash
planes (for 256Mb single-die devices), each of which enables 8-bit access. This 16-bit data bus
permits 16-bit wide access to the host.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a
read cycle occurs while both the CE# and OE# inputs are asserted. Note that Mobile DiskOnChip
P3 does not require a clock signal. It features a unique analog static design, optimized for minimal
power consumption. The CE#, WE# and OE# signals trigger the controller (e.g., system interface
block, bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase,
delay the CPU resources. The signal is also asserted when a Data Protection violation has occurred.
This signal frees the CPU to run other tasks, continuing read/write operations with Mobile
DiskOnChip P3 only after the IRQ# signal has been asserted and an interrupt handling routine
(implemented in the OS) has been called to return control to the TrueFFS driver.
The DMARQ# output is used to control multi-page DMA operations, and the CLK input is used to
support MultiBurst operation when reading flash data. See Section 4.1 for further information.

3.2.2 Multiplexed

Interface

In this configuration, the address and data signals are multiplexed. The ID[1] input is driven by the
host AVD# signal, and the D[15:0] pins/balls, used for both address inputs and data, are connected
to the host AD[15:0] bus. While AVD# is asserted, the host drives AD[11:0] with bits [12:1] of the
address. Host signals AD[15:12] are not significant during this part of the cycle.
This interface is automatically used when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before the first read or write cycle to the controller. When using a
multiplexed interface, the value of ID[1] is internally forced to logic-0. The only possible device ID
values are 0 and 1; therefore, only up to two Mobile DiskOnChip P3 256Mb devices may be
cascaded in multiplexed configuration.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

3.3 Configuration

Interface

The Configuration Interface block enables the designer to configure Mobile DiskOnChip P3 to
operate in different modes. The ID[1:0] signals are used in a cascaded configuration (refer to
Section 10.6), the DPD signal is used to enter and exit Deep Power-Down mode (see Section 6.3),
the LOCK# signal is used for hardware write/read protection, and the IF_CFG signal is used to
configure 8/16-bit access.

3.4 Protection and Security-Enabling Features

The Protection and Security-Enabling block, consisting of read/write protection, UID and an OTP
area, enables advanced data and code security and content protection. Located on the main route of
traffic between the host and the flash, this block monitors and controls all data and code transactions
to and from Mobile DiskOnChip P3.

3.4.1 Read/Write

Protection

Data and code protection is implemented through a Protection State Machine (PSM). The user can
configure one or two independently programmable areas of the flash memory as read protected,
write protected, or read/write protected.
A protected partition may be protected by either/both of these hardware mechanisms:

· 64-bit protection key
· Hard-wired LOCK# signal
If the Lock option is enabled (by means of software) and the LOCK# signal is asserted, the
protected partition has an additional hardware lock that prevents read/write access to the partition,
even with the use of the correct protection key. The LOCK# signal must be asserted during
formatting (and later when the partition is defined as changeable) to enable the additional hardware
safety lock.
Only one partition can be defined as "changeable"; i.e., its password and attributes are fully
configurable at any time (from read to write, both or none and vise versa). Note that "un-
changeable" partition attributes cannot be changed unless the media is reformatted.
The size and protection attributes of the protected partition are defined during the media-formatting
stage.
In the event of an attempt to bypass the protection mechanism, illegally modify the protection key
or in any way sabotage the configuration parameters, the entire Mobile DiskOnChip P3 becomes
both read and write protected, and is completely inaccessible.
For further information on hardware protection, please refer to the TrueFFS Software Development
Kit (SDK) developer guide.

3.4.2 Unique Identification (UID) Number

Each Mobile DiskOnChip P3 is assigned a 16-byte UID number. Burned onto the flash during
production, the UID cannot be altered and is unique worldwide. The UID is essential in security-
related applications, and can be used to identify end-user products in order to fight fraudulent
duplication by imitators.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

3.4.3 One-Time Programmable (OTP) Area

The 6KB OTP area is user programmable for complete customization. The user can write to this
area once, after which it is automatically and permanently locked. After it is locked, the OTP area
becomes read only, just like a ROM device.
Typically, the OTP area is used to store customer and product information such as: product ID,
software version, production data, customer ID and tracking information.

3.4.4 One-Time Write (ROM-Like) Partition

A single partition in the Mobile DiskOnChip P3 can be set as One-Time Write. After it is locked,
this partition becomes read only, just like a ROM device. Its capacity is defined during the media-
formatting stage.

3.4.5 Sticky Lock (SLOCK)

The boot partition can be locked automatically by hardware after the boot phase is completed and
the device is in Normal mode. This is done by setting the Sticky Lock (SLOCK) bit in the Output
Control register to 1. This has the same effect as asserting the LOCK# signal. Once set, SLOCK can
only be cleared by asserting the RSTIN# input. Like the LOCK# input, assertion of this bit prevents
the protection key from disabling the protection for a given partition. There is no need to mount the
boot partition before calling a hardware protection routine.
Upon reset, the boot partition is unlocked for the duration of the boot phase, and is automatically
locked once this phase is over. This provides a high level of protection to the boot code, while still
enabling an easy method for field and remote upgrades.

3.5 Programmable Boot Block with eXecute In Place (XIP) Functionality

The Programmable Boot Block with XIP functionality enables Mobile DiskOnChip P3 to act as a
boot device in addition to performing flash disk data storage functions. This eliminates the need for
expensive, legacy NOR flash or any other boot device on the motherboard.
The Programmable Boot Block on Mobile DiskOnChip P3 256Mb is 2KB in size. The Download
Engine (DE), described in the next section, expands the functionality of this block by copying the
boot code from the flash into the boot block.
DiskOnChip P3 256Mb devices may be cascaded in order to form a larger flash disk. When Mobile
DiskOnChip P3 256Mb is connected with a standard NOR-like interface, up to four devices may be
cascaded to create a 1Gb flash disk. When Mobile DiskOnChip P3 256Mb is connected with a
multiplexed interface, up to two devices may be cascaded to create a 512 Mb flash disk.
Note: When more than one Mobile DiskOnChip P3 256Mb are cascaded, a maximum boot block of

4KB is available. The Programmable Boot Block of each device is mapped to a unique
address space.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

3.6 Download

Engine

(DE)

Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial
Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the
booting process. The download process is quick, and is designed so that when the CPU accesses
Mobile DiskOnChip P3 for code execution, the IPL code is already located in the Programmable
Boot Block.
In addition, the DE downloads the data protection rules from the flash to the Protection State
Machines (PSM), so that Mobile DiskOnChip P3 is secure and protected from the first moment it is
active.
During the download process, Mobile DiskOnChip P3 asserts the BUSY# signal to indicate to the
system that it is not yet ready to be accessed. Once BUSY# is negated, the system can access
Mobile DiskOnChip P3.
A failsafe mechanism prevents improper initialization due to a faulty VCC or invalid assertion of
the RSTIN# input. Another failsafe mechanism is designed to overcome possible NAND flash data
errors. It prevents internal registers from powering up in a state that bypasses the intended data
protection. In addition, any attempt to sabotage the data structures causes the entire DiskOnChip to
become both read and write protected, and completely inaccessible.

3.7 Error Detection Code/Error Correction Code (EDC/ECC)

M-Systems' x2 technology implements 4-bit Error Detection Code/Error Correction Code
(EDC/ECC), based on a patented combination of Bose, Chaudhuri and Hocquenghem (BCH) and
Hamming code algorithms. Error Detection Code (EDC) is implemented in hardware to optimize
performance, while Error Correction Code (ECC) is performed in software, when required, to save
silicon costs.
Each time a 256-byte page is written, additional parity bits are calculated and written to the flash.
Each time data is read from the flash, the parity bits are read and used to calculate error locations.
The Hamming code can detect 2 errors per page and correct 1 error per page. The BCH code can
detect and correct 4 errors per page. It can detect 5 errors per page with a probability of 99.9%. It
ensures that the minimal amount of code required is used for detection and correction to deliver the
required reliability without degrading performance.

3.8 Data

Pipeline

Mobile DiskOnChip P3 uses a two-stage pipeline mechanism, designed for maximum performance
while enabling on-the-fly data manipulation, such as read/write protection and Error
Detection/Error Correction. Refer to technical note TN-DOC-014, Pipeline Mechanism in
DiskOnChip, for further information.

3.9 Control

and

Status

The Control and Status block contains registers responsible for transferring address, data and
control information between the DiskOnChip TrueFFS driver and the flash media. Additional
registers are used to monitor the status of the flash media (ready/busy) and the DiskOnChip
controller. For further information on the DiskOnChip registers, refer to Section 8.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

3.10 Flash Architecture

Mobile DiskOnChip P3 256Mb consists of two 128Mb flash planes that consist of 1024 blocks
each, divided in groups of 32 pages, as follows:

· Page Each page contains 512 bytes of user data and a 8-byte extra area that is used to store

flash management and EDC/ECC signature data, as shown in Figure 8.

· Block Each block contains 32 pages (total of 128Kb), as shown in Figure 9. A block is the

minimal unit that can be erased, and is sometimes referred to as an erase block.
Note: Since the device works with multiple planes, the operational block size is 256Kb, as

described in the next section.

16 Bytes

512 Bytes

User Data 512 Bytes

Flash Management &

ECC/EDC Signature

Figure 8: Page Structure

16 Bytes

512 Bytes

Page 0

Page 1

128 Kb

Page 31

Page 30

Figure 9: Block Structure

Parallel Multi-Plane Access

The two 128Mb flash planes operate in parallel, thereby providing a true 32-bit internal data bus
and four times the read, write and erase performance. Two pages on different planes can be
concurrently read or written if they have the same offset within their respective units, even if the
units are unaligned.
Bad units are mapped individually on each plane by enabling unaligned unit access, as shown in
Figure 10. Good units can therefore be aligned or unaligned, minimizing the effects of bad units on
the media. Without this capability, a bad unit in one plane would cause a good unit in the second
plane to be tagged as a bad unit, making it unusable. This customized method of bad unit handling
for two planes enhances data reliability without adversely affecting performance.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2 T

ECHNOLOGY

Mobile DiskOnChip P3 enhances performance using various proprietary techniques:

· Parallel access to the separate 128Mb flash planes, thereby providing an internal 32-bit data

bus. See Section 3.10 for further information.

· MultiBurst operation to read large chunks of data, providing a MultiBurst read speed of up to

80 MB/sec.

· DMA operation to release the CPU for other tasks in coordination with the platform's DMA

controller. This is especially useful during the boot stage. Up to 32KB of data can be
transferred during a DMA operation.

· Turbo operation to enhance read access time from 55 ns to 33 ns (standard interface, access to

flash addresses).

4.1 MultiBurst

Operation

MultiBurst operation is especially effective for large file reads that are typical during boot-up.
During MultiBurst operation, data is read from the two flash planes in parallel through a 32-bit wide
internal flash interface. Data is read by the host one 16-bit word after another using the CLK input,
resulting in a MultiBurst read mode of up to 80 MB/sec. MultiBurst operation can only be
performed on hosts that support burst reads. See Figure 11 below.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Flash Plane

O
R
D

Flash Plane

O
R
D

-b

i
t
D

a
ta

u
x

16-bit to

Host

16-bit Data

FIFO

32-bit Transfer

Data transfer from

Flash Planes to FIFO

/Flash_OE

Internal data transfers

16-bit Transfer

/DiskOnChip_OE

Data transfer from

FIFO to Host

External data transfers

Figure 11: MultiBurst Operation

Note: Mobile DiskOnChip P3 does not support MultiBurst write operations.

MultiBurst operation is controlled by 5 bits in the MultiBurst Mode Control register: BURST_EN,
CLK_INV, LATENCY, HOLD and LENGTH. For full details on this register, please refer to
Section 8.
MultiBurst mode read cycles are supported via the CLK input, which is enabled by setting the
BURST_EN bit in the MultiBurst Mode Control register.
To determine whether the rising or falling edge of the CLK input is sampled (called CLK0), the
CLK_INV bit in the MultiBurst Mode Control register must be specified. When the CLK_INV bit
is set to 0, CE# and OE# are sampled on the rising edge of CLK; when the CLK_INV bit is set to 1,
sampling is done on the falling edge of CLK.
Notes: 1. When the CLK_INV bit is set to 1, sampling is done on the falling edge of CLK, and an

additional half-clock cycle of latency is incurred. Data continues to be output on D[15:0]
on the rising edge of CLK.

2. The CLK input is disabled upon the assertion of the RSTIN# input and may therefore be

left floating.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When
the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after
CLK0. This time can be extended by up to seven clock cycles by programming the LATENCY bit.
After latching the first word, additional 16-bit data words can be latched on each subsequent clock
cycle.
The HOLD bit in the MultiBurst Mode Control register can be set to hold each data word valid for
two clock cycles rather than one.

The LENGTH bit in the MultiBurst Mode Control register must be programmed with the length of
the burst to be performed. As read cycles from the flash are volatile, each burst cycle must read
exactly this number of words.
The CLK input can be toggled continuously or can be halted. When halting the CLK input, the
following guidelines must be observed:

· After asserting OE# and CE#, LATENCY + 2 CLK cycles are required prior to latching the

first word (2.5 CLK cycles if CLK_INV is set to 1).

· If the HOLD bit is set to 0, the host must provide one rising CLK edge for each word read,

except for the last word latched, for which CLK does not need to be toggled.

· If the HOLD bit is set to 1, the host must provide two rising CLK edges for each word read,

except for the last word, for which the second of the two CLK rising edges is not required.

· Subsequent toggling of the CLK is optional.

4.2 DMA

Operation

Mobile DiskOnChip P3 provides a DMARQ# output that enables up to 32KB to be read from the
flash by the host DMA controller. During DMA operation, the DMARQ# output is used to notify
the host DMA controller that the next flash page is ready to be read, and the IRQ# pin indicates
whether an error occurred while reading the data from the flash or the end of the DMA transfer was
reached.
The DMARQ# output sensitivity is chosen by setting the EDGE bit in the DMA Control register[0]:

· Edge - The DMARQ# output pulses to logic 0 for 250~500 nsec to indicate to the DMA

controller that a flash page is ready to be read. The EDGE bit is set to 1 for this mode.

· Level - The DMARQ# output is asserted to initiate the block transfer and returns to the

negated state at the end of each block transfer. The EDGE bit is set to 0 for this mode.

The following steps are required to initiate a DMA operation:
1. Initialize the platform's DMA controller to transfer 512 bytes upon each assertion of the

DMARQ# output. If the DMA controller supports an edge-sensitive DMARQ# signal, then
initialize the DMA controller to transfer 512 bytes upon each DMA request. If the DMA
controller supports a level-sensitive DMARQ# signal, then initialize the DMA controller to
transfer data while DMARQ# is asserted.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

2. Set the bits in the Interrupt Control register (see Section 8) to enable interrupts on an ECC error

and at the end of the DMA operation.

3. Write to the DMA Control register[0] to set the DMA_EN bit, the EDGE bit and the number of

sectors (SECTOR_COUNT bit) to be transferred to the host. At this point, Mobile DiskOnChip
P3 generates a DMA request to indicate to the host that it is ready to transfer data.

4. The host DMA controller reads one sector (512 bytes) of data from Mobile DiskOnChip P3.
5. If an ECC error is detected, an interrupt is generated (IRQ# signal asserted), the transfer of data

is halted and control is returned to the host. If no ECC error is detected, a DMA request is
initiated (DMARQ# signal asserted) and the next sector is read by the host.

6. The process continues until the last sector is read, after which Mobile DiskOnChip P3

generates an interrupt (IRQ# signal asserted) to indicate that it has transferred the last byte.

Notes: 1. Mobile DiskOnChip P3 generates a DMA request (DMARQ# signal asserted) after the

last byte is read. It may therefore be necessary to clear the final DMA request from the
DMA controller.

2. DMA operation may be aborted after transferring each 512-byte block (step 4) by

clearing the DMA_EN bit in the DMA Control register[0].

4.3 Combined

MultiBurst

Mode and DMA Operation

When using MultiBurst mode and DMA operation together, and an interrupt is generated (IRQ#
signal asserted), the Download Status register cannot be polled, as it will not comply with the
MultiBurst mode timing specification. The following sequence is therefore required to respond to
an interrupt request while in MultiBurst mode:

· Perform 7 write cycles to the NOP register.
· Turn off MultiBurst mode by writing to the MultiBurst Mode Control register.

4.4 Turbo

Operation

In order to provide faster read access time, Mobile DiskOnChip P3 can be configured for Turbo
operation by enabling the D[15:0] output buffers immediately after the assertion of OE# and CE#.
Enter Turbo operation by setting the TURBO bit in the Output Control register. For timing
specifications for Turbo operation, see Section 11.3.
Since the read access time for the Programmable Boot Block is slower than the read access time for
the registers, bus contention may occur when reading from the Programmable Boot Block during
system boot. It is therefore not recommended to use Turbo operation during boot, but only after the
system is up and running and Mobile DiskOnChip P3 is being used as a flash disk.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

5. H

ARDWARE

ROTECTION

5.1 Method of Operation

Mobile DiskOnChip P3 enables the user to define two partitions that are protected (in hardware)
against any combination of read or write operations. The two protected areas can be configured as
read protected or write protected, and are protected by a protection key (i.e. password) defined by
the user. Each of the protected areas can be configured separately and can function separately,
providing maximum flexibility for the user.
The size and protection attributes (protection key, read, write, changeable, lock) of the protected
partition are defined in the media formatting stage (DFORMAT utility or the format function in the
TrueFFS SDK).
In order to set or remove read/write protection, the protection key (i.e., password) must be used, as
follows:
· Insert the protection key to remove read/write protection.
· Remove the protection key to set read/write protection.
Mobile DiskOnChip P3 has an additional hardware safety measure. If the Lock option is enabled
(by means of software) and the LOCK# signal is asserted, the protected partition has an additional
hardware lock that prevents read/write access to the partition, even with the use of the correct
protection key. The LOCK# signal must be asserted during DFORMAT (and later when the
partition is defined as changeable) to enable the additional hard-wired safety lock.
It is possible to set the Lock option for one session only; that is, until the next power-up or reset.
This Sticky Lock feature can be useful when the boot code in the boot partition must be read/write
protected. Upon power-up, the boot code must be unprotected so the CPU can run it directly from
Mobile DiskOnChip P3. At the end of the boot process, protection can be set until the next power-
up or reset.
Setting the Sticky Lock (SLOCK) bit in the Output Control register to 1 has the same effect as
asserting the LOCK# signal. Once set, SLOCK can only be cleared by asserting the RSTIN# input.
Like the LOCK# input, the assertion of this bit prevents the protection key from disabling the
protection for a given partition. For more information, see Section 3.4.5. The target partition does
require mounting before calling a hardware protection routine.
The only way to read or write from a protected partition is to use insert the key (even DFORMAT
does not remove the protection). This is also true for modifying its attributes (protection key, read,
write and lock). Read/write protection is disabled in each of the following events:
· Power-down
· Change of any protection attribute (not necessarily in the same partition)
· Write operation to the IPL area
· Removal of the protection key.
For further information on hardware protection, please refer to the TrueFFS Software Development
Kit (SDK) developer guide.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

5.2 Low-Level

Structure

of the Protected Area

The first five blocks in Mobile DiskOnChip P3 contain foundry information, the Data Protect
structures, IPL code, and bad block mapping information. See Figure 12.

Bad Block Table and Factory-Programmed UID

Data Protect Structure 0

Pages 0-5

Pages 8-31

OTP

Data Protect Structure 1 and IPL Code

Block 0

Block 1+2

Block 3+4

Figure 12: Low Level Structure of Mobile DiskOnChip P3

Blocks 0-4 in Mobile DiskOnChip P3 contain the following information:

Block 0
o Bad Block Table (page 4). Contains the mapping information on unusable erase units on

the flash media.

o UID (16 bytes). This number is written during the manufacturing stage, and cannot be

altered at a later time.

o Customer OTP (occupies pages 8-31). The OTP area is written once and then locked.
Block 1 and 2
o Data Protect Structure 0. This structure contains configuration information on one of the

two user-defined protected partitions. Block 2 is a copy of Block 1 for redundancy
purposes.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

6. M

ODES OF

PERATION

Mobile DiskOnChip P3 operates in one of three basic modes:
· Normal mode
· Reset mode
· Deep Power-Down mode
The current mode of the chip can always be determined by reading the DiskOnChip Control
register. Mode changes can occur due to any of the following events:
· Assertion of the RSTIN# signal sets the device in Reset mode.
· During power-up, boot detector circuitry sets the device in Reset mode.
· A valid write sequence to Mobile DiskOnChip P3 sets the device in Normal mode. This is done

automatically by the TrueFFS driver on power-up (reset sequence end).

· Switching back from Normal mode to Reset mode can be done by a valid write sequence to

Mobile DiskOnChip P3, or by triggering the boot detector circuitry (via a soft reset).

· Deep Power-Down
· A valid write sequence, initiated by software, sets the device from Normal mode to Deep

Power-Down mode. Four read cycles from offset 0x1FFF set the device back to Normal mode.
Alternately, the device can be set back to Normal mode with an extended access time during a
read from the Programmable Boot Block.

· Asserting the RSTIN# signal and holding it in this state while in Normal mode puts the device

in Deep Power-Down mode. When RSTIN# is released, the device is set in Reset mode.

· Toggling the DPD signal as defined by the DPD Control register.

Power Off

Reset Mode

Deep

Power-Down

Mode

Normal Mode

Power-Up

Power-Down

Assert RSTIN#,

Boot Detect or

Software Control

Power-Down

Reset

Sequence

End

Software Control

4x Read Cycles from

offset 0x1FFF or

extended read cycle

Power-Down

Release RSTIN#

Assert RSTIN#

Assert RSTIN#

Figure 13: Operation Modes and Related Events

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

6.1 Normal

Mode

This is the mode in which standard operations involving the flash memory are performed. Normal
mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control
Confirmation register. The boot detector circuit triggers the software to set the device to Normal
mode.
A write cycle occurs when both the CE# and WE# inputs are asserted. Similarly, a read cycle occurs
when both the CE# and OE# inputs are asserted. Because the flash controller generates its internal
clock from these CPU cycles and some read operations return volatile data, it is essential that the
timing requirements specified in Section 11.3 be met. It is also essential that read and write cycles
not be interrupted by glitches or ringing on the CE#, WE#, and OE# address inputs. All inputs to
Mobile DiskOnChip P3 are Schmidt Trigger types to improve noise immunity.

6.2 Reset

Mode

In Reset mode, Mobile DiskOnChip P3 ignores all write cycles, except for those to the DiskOnChip
Control register and Control Confirmation register. All register read cycles return a value of 00H.
Before attempting to perform a register read operation, the device is set to Normal mode by
TrueFFS software.

6.3 Deep Power-Down Mode

While in Deep Power-Down mode, Mobile DiskOnChip P3's quiescent power dissipation is
reduced by disabling internal high current consumers (e.g. voltage regulators, input buffers,
oscillator etc.). The following signals are also disabled in this mode:

· Standard interface: Input buffers A[12:0], WE#, D[15:0] and OE# (when CE# is negated)
· Multiplexed interface: Input buffers AD[15:0], AVD#, WE# and OE# (when CE# is negated).
To enter Deep Power-Down mode, a proper sequence must be written to the Mobile DiskOnChip
P3 Control registers and the CE# input must be negated. All other inputs should be VSS or VCC.
When in Normal mode, asserting the RSTIN# signal and holding it in low state puts the device in
Deep Power-Down mode. When the RSTIN# signal is released, the device is set in Reset mode.
In Deep Power-Down mode, write cycles have no effect and read cycles return indeterminate data
(Mobile DiskOnChip P3 does not drive the data bus). Entering Deep Power-Down mode and then
returning to the previous mode does not affect the value of any register.
To exit Deep Power-Down mode, use one of the following methods:

· Read four times from address 1FFFH (Programmable Boot Block). The data returned is

undefined.

· Perform a single read cycle from the Programmable Boot Block with an extended access time

and address hold time as specified in the timing diagrams. The data returned will be correct.
Please note that this option can only be used with a standard interface, not with a multiplexed
interface.

· Toggle the DPD input as defined by the DPD Control register.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

7. T

RUE

FFS T

ECHNOLOGY

7.1 General

Description

M-Systems' patented TrueFFS technology was designed to maximize the benefits of flash memory
while overcoming inherent flash limitations that would otherwise reduce its performance, reliability
and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition,
since it operates under the OS file system layer (see Figure 14), it is completely transparent to the
application.

Figure 14: TrueFFS Location in System Hierarchy

TrueFFS technology support includes:

· Binary driver support for all major OSs
· TrueFFS Software Development Kit (TrueFFS SDK)
· Boot Software Development Kit (BDK)
· Support for all major CPUs, including 8, 16 and 32-bit bus architectures.
TrueFFS technology features:

· Block device API
· Flash file system management
· Bad-block management
· Dynamic virtual mapping
· Dynamic and static wear-leveling
· Power failure management
· Implementation of EDC/ECC
· Performance optimization
· Compatibility with all DiskOnChip products

Application

OS File System

TrueFFS

DiskOnChip

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

7.1.1 Built-In Operating System Support

The TrueFFS driver is integrated into all major OSs, including Symbian, Palm OS, Pocket PC
2002/3, Smartphone 2002/3, Windows CE/NT, Linux (various kernels), Nucleus, and others. For a
complete listing of all available drivers, please refer to M-Systems' website,

www.m-sys.com

. It is

advised to use the latest driver versions that can be downloaded from the website.

7.1.2 TrueFFS Software Development Kit (SDK)

The basic TrueFFS Software Development Kit (SDK) developer guide provides the source code for
the TrueFFS driver. It can be used in an OS-less environment or when special customization of the
driver is required for proprietary OSs.
When using Mobile DiskOnChip P3 as the boot replacement device, TrueFFS SDK also
incorporates in its source code the boot software that is required for this configuration (this package
is also available separately). Please refer to the DiskOnChip Boot Software Development Kit (BDK)
developer guide for further information on using this software package.
Note: Mobile DiskOnChip P3 is supported by TrueFFS 6.1 and above.

7.1.3 File

Management

TrueFFS accesses the flash memory within Mobile DiskOnChip P3 through an 8KB window in the
CPU memory space. TrueFFS provides block device API by using standard file system calls,
identical to those used by a mechanical hard disk, to enable reading from and writing to any sector
on Mobile DiskOnChip P3. This makes Mobile DiskOnChip P3 compatible with any file system
and file system utilities, such as diagnostic tools and applications. When using the Flash Allocation
Table (FAT) file system, the data stored on Mobile DiskOnChip P3 uses the FAT-16 file system.
Note: Mobile DiskOnChip P3 is shipped unformatted and contains virgin media.

7.1.4 Bad Block Management

Since NAND flash is an imperfect storage media, it can contain bad blocks that cannot be used for
storage because of their high error rates. TrueFFS automatically detects and maps out bad blocks
upon system initialization, ensuring that they are not used for storage. This management process is
completely transparent to the user, who is unaware of the existence and location of bad blocks,
while remaining confident of the integrity of data stored.

7.1.5 Wear-Leveling

Flash memory can be erased a limited number of times. This number is called the erase cycle limit,
or write endurance limit, and is defined by the flash array vendor. The erase cycle limit applies to
each individual erase block in the flash device. In Mobile DiskOnChip P3, the erase cycle limit of
the flash is 100,000 erase cycles. This means that after approximately 100,000 erase cycles, the
erase block begins to make storage errors at a rate significantly higher than the error rate that is
typical to the flash.
In a typical application, and especially if a file system is used, specific pages are constantly updated
(e.g., the page/s that contain the FAT, registry, etc.). Without any special handling, these pages
would wear out more rapidly than other pages, reducing the lifetime of the entire flash.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

To overcome this inherent deficiency, TrueFFS uses M-Systems' patented wear-leveling algorithm.
This wear-leveling algorithm ensures that consecutive writes of a specific sector are not written
physically to the same page in the flash. This spreads flash media usage evenly across all pages,
thereby maximizing flash lifetime. TrueFFS wear-leveling extends the flash lifetime 10 to 15 years
beyond the lifetime of a typical application.

Dynamic Wear-Leveling

TrueFFS uses statistical allocation to perform dynamic wear-leveling on newly written data. This
not only minimizes the number of erase cycles per block, it also minimizes the total number of erase
cycles. Because a block erase is the most time-consuming operation, dynamic wear-leveling has a
major impact on overall performance. This impact cannot be noticed during the first write to flash
(since there is no need to erase blocks beforehand), but it is more and more noticeable as the flash
media becomes full.

Static Wear-Leveling

Areas on the flash media may contain static files, characterized by blocks of data that remain
unchanged for very long periods of time, or even for the whole device lifetime. If wear-leveling
were only applied on newly written pages, static areas would never be cycled. This limited
application of wear-leveling would lower life expectancy significantly in cases where flash memory
contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as
well as in dynamic areas, thereby applying wear-leveling to the entire media.

7.1.6 Power Failure Management

TrueFFS uses algorithms based on "erase after write" instead of "erase before write" to ensure data
integrity during normal operation and in the event of a power failure. Used areas are reclaimed for
erasing and writing the flash management information into them only after an operation is
complete. This procedure serves as a check on data integrity.
The "erase after write" algorithm is also used to update and store mapping information on the flash
memory. This keeps the mapping information coherent even during power failures. The only
mapping information held in RAM is a table pointing to the location of the actual mapping
information. This table is reconstructed during power-up or after reset from the information stored
in the flash memory.
To prevent data from being lost or corrupted, TrueFFS uses the following mechanisms:

· When writing, copying, or erasing the flash device, the data format remains valid at all

intermediate stages. Previous data is never erased until the operation has been completed and
the new data has been verified.

· A data sector cannot exist in a partially written state. Either the operation is successfully

completed, in which case the new sector contents are valid, or the operation has not yet been
completed or has failed, in which case the old sector contents remain valid.

7.1.7 Error

Detection/Correction

TrueFFS implements a unique Error Correction Code (ECC) algorithm to ensure data reliability.
Refer to Section 3.7 for further information on the EDC/ECC mechanism.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

7.1.8 Special Features Through I/O Control (IOCTL) Mechanism

In addition to standard storage device functionality, the TrueFFS driver provides extended
functionality. This functionality goes beyond simple data storage capabilities to include features
such as: formatting the media, read/write protection, boot partition(s) access, flash defragmentation
and other options. This unique functionality is available in all TrueFFS-based drivers through the
standard I/O control command of the native file system.

7.1.9 Compatibility

Mobile DiskOnChip P3 requires TrueFFS driver 6.x or higher.
When using different drivers (e.g. TrueFFS SDK, BDK, BIOS extension firmware, etc.) to access
Mobile DiskOnChip P3, verify that all software is based on the same code base version. It is also
important to use only tools (e.g. DFORMAT, DINFO, GETIMAGE, etc.) from the same version as
the firmware and the TrueFFS drivers used in the application. Failure to do so may lead to
unexpected results, such as lost or corrupted data. The driver and firmware version can be verified
by the sign-on messages displayed, or by the version information stored in the driver or tool.

7.2 8KB Memory Window

TrueFFS utilizes an 8KB memory window in the CPU address space, consisting of four 2KB
sections as depicted in Figure 15. When in Reset mode, read cycles from sections 1 and 2 always
return the value 00H to create a fixed and known checksum. When in Normal mode, these two
sections are used for the internal registers. The 2KB Programmable Boot Block is in section 0 and
section 3, to support systems that search for a checksum at the boot stage both from the top and
bottom of memory. The addresses described here are relative to the absolute starting address of the
8KB memory window.

Programmable

Boot Block

Reset Mode

Flash area

window

(+ aliases)

000H

800H

1000H

1800H

Control

Registers

Section 0

Section 1

Section 2

Section 3

Normal Mode

00H

Programmable

Boot Block

Programmable

Boot Block

00H

Programmable

Boot Block

Figure 15: Mobile DiskOnChip P3 Memory Map

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8. R

EGISTER

ESCRIPTIONS

This section describes various Mobile DiskOnChip P3 registers and their functions, as listed in
Table 5. Most Mobile DiskOnChip P3 registers are 8-bit, unless otherwise denoted as 16-bit.

Table 5: Mobile DiskOnChip P3 Registers

Address (Hex)

Register Name

103E

No Operation (NOP)

1000/1074

Chip Identification [1:0]

1004 Test

1006

Bus Lock

1008 Endian

Control

100C DiskOnChip

Control

1072

DiskOnChip Control Confirmation

100A

Device ID Select

100E Configuration

1010 Interrupt

Control

1020 Interrupt

Status

1014 Output

Control

107C DPD

Control

1078/107A DMA

Control

[1:0]

101C

MultiBurst Mode Control

8.1 Definition of Terms

The following abbreviations and terms are used within this section:
RFU

Reserved for future use. This bit is undefined during a read cycle and "don't care"
during a write cycle.

RFU_0

Reserved for future use; when read, this bit always returns the value 0; when
written, software should ensure that this bit is always set to 0.

RFU_1

Reserved for future use; when read, this bit always returns the value 1; when
written, software should ensure that this bit is always set to 1.

Reset Value Refers to the value immediately present after exiting from Reset mode to Normal

mode.

8.2 Reset

Values

All registers return 00H while in Reset mode. The Reset value written in the register description is
the register value after exiting Reset mode and entering Normal mode. Some register contents are
undefined at that time (N/A).

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.3 No Operation (NOP) Register

Description:

A call to this 16-bit register results in no operation. To aid in code readability
and documentation, software should access this register when performing cycles
intended to create a time delay.

Address (hex): 103E
Type: Write
Reset Value:

None

8.4 Chip Identification (ID) Register [0:1]

Description:

These two 16-bit registers are used to identify the DiskOnChip device residing
on the host platform. They always return the same value.

Address (hex): 1000/1074
Type: Read

only

Reset Value:

Chip Identification Register[0]: 0200H
Chip Identification Register[1]: FDFFH

8.5 Test

Register

Description:

This register enables software to identify multiple Mobile DiskOnChip P3
devices or multiple aliases in the CPUs memory space. Data written is stored but
does not affect the behavior of Mobile DiskOnChip P3.

Address (hex): 1004
Type: Read/Write
Reset Value:

Bit No.

Description

7-0

D[7:0]: Data bits

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.6 Bus Lock Register

Description:

This register provides a mechanism for a CPU to request and hold sole access
rights to Mobile DiskOnChip P3 in multiprocessor applications.
The following algorithm must be implemented to ensure that only one CPU at a
time accesses Mobile DiskOnChip P3:
1. Before beginning an indivisible operation sequence (e.g. reading/writing a

sector to the DiskOnChip), the value of this register is read. If it is non-zero,
then it must continue to be polled until it becomes zero.

2. Once the value read is zero, a non-zero value unique to each CPU is written

to this register to indicate to other CPUs that the device is in use.

3. The value written must then be confirmed. If the register returns the same

value that was written, then the CPU is assured of sole access rights to
Mobile DiskOnChip P3. If it is not the same value, then another CPU has
claimed access rights to the device and the process must be repeated from
step 1.

4. Upon completion of the indivisible operation sequence, this register must be

set to 00H to release the lock and permit other CPUs to access the device.

Address (hex): 1006
Type: Read/Write
Reset Value:

Bit No.

Description

7-0

D[7:0]: CPU Control value

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.7 Endian Control Register

Description:

This 16-bit register is used to control the swapping of the low and high data
bytes when reading or writing with a 16-bit host. This provides an Endian-
independent method of enabling/disabling the byte swap feature.
Note: Hosts that support 8-bit access only do not need to write to this register.

Address (hex): 1008

Bit

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 SWAPL

Reset Value

0 0 0 0 0 0 0 0

Bit

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Read/Write

R R/W

Description

RFU_0 SWAPH

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

SWAPL (Swap Low Byte): This bit must be set to enable byte swapping. If the bit is
cleared, then byte swapping is disabled.

7-1

Reserved for future use.

SWAPH (Swap High Byte): This bit must be set to enable byte swapping. If the bit is
cleared, then byte swapping is disabled.

15-9

Reserved for future use.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.8 DiskOnChip Control Register/Control Confirmation Register

Description:

These two registers are identical and contain information about the Mobile
DiskOnChip P3 operational mode. After writing the required value to the
DiskOnChip Control register, the complement of that data byte must also be
written to the Control Confirmation register. The two writes cycles must not be
separated by any other read or write cycles to the Mobile DiskOnChip P3
memory space, except for reads from the Programmable Boot Block space.

Address (hex): 100C/1072

Bit

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R/W R

Description

Mode[1:0] MDWREN

BDET

RST_LAT

RFU_0

Reset Value

0 0 0 0 1 0 0 0

Note: The DiskOnChip Control Confirmation register is write only

Bit No.

Description

1-0

Mode. These bits select the mode of operation, as follows:
00: Reset
01: Normal
10: Deep Power-Down

MDWREN (Mode Write Enable). This bit must be set to 1 before changing the mode of
operation. It always returns 0 when read.

BDET (Boot Detect). This bit is set whenever the device has entered Reset mode as a
result of the Boot Detector triggering. It is cleared by writing a 1 to this bit.

RST_LAT (Reset Latch). This bit is set whenever the device has entered the Reset mode
as a result of the RSTIN# input signal being asserted or the internal voltage detector
triggering. It is cleared by writing a 1 to this bit.

7-5

Reserved for future use.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.9 Device ID Select Register

Description:

In a cascaded configuration, this register controls which device provides the
register space. The value of bits ID[0:1] is compared to the value of the ID
configuration input pins/balls. The device whose ID input matches the value of
bits ID[0:1] responds to read and write cycles.

Address (hex): 100A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 ID[1:0]

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

1-0

ID[1:0] (Identification). The device whose ID input pins/balls match the value of bits ID[0:1]
responds to read and write cycles to register space.

7-2

Reserved for future use.

8.10 Configuration Register

Description:

This register indicates the current configuration of Mobile DiskOnChip P3. Unless
otherwise noted, the bits are reset only by a hardware reset, and not upon boot
detection or any other entry to Reset mode.

Address (hex): 100E

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

IF_CFG RFU_0

MAX_ID

RFU

RFU_0

VCCQ_3V

Reset Value

X 0 0 0 0 0 0 X

Bit No.

Description

VCCQ_3V: Reflects the level of VCCQ input.
0: VCCQ < 2.0V
1: VCCQ > 2.5V

6, 3-1

Reserved for future use.

5-4

MAX_ID (Maximum Device ID). This field controls the Programmable Boot Block address
mapping when multiple devices are used in a cascaded configuration, using the ID[1:0]
inputs. It should be programmed to the highest ID value that is found by software in order to
map all available boot blocks into usable address spaces.

IF_CFG (Interface Configuration). Reflects the state of the IF_CFG input pin.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.11 Interrupt Control Register

Description:

This 16-bit register controls how interrupts are generated by Mobile DiskOnChip
P3, and indicates which of the following five sources has asserted an interrupt:
0: Flash array is ready
1: Data protection violation
2: Reading or writing more flash data than was specified in the DCNT field of

ECC Control Register[0]

3: BCH ECC error detected (this feature is provided to support multi-page DMA

transfers)

4: Real-time clock
5: Completion of a DMA operation

Address (hex): 1010

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 ENABLE

Reset Value

0 0 0 0 0 0 0 0

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Read/Write

R/W

Description

GMASK EDGE

MASK

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

5-0

ENABLE. For each bit in this field:
1: Enables the respective bit in the STATUS field of the Interrupt Status register to latch

activity and cause an interrupt if the corresponding MASK bit is set.

0: Holds the respective bit in the STATUS field in the cleared state. To clear a pending

interrupt and re-enable further interrupts on that channel, the respective ENABLE bit
must be cleared and then set.

7-6

Reserved for future use.

13-8

MASK. For each bit in this field:
1: Enables the respective bit in the STATUS field of the Interrupt Status register to generate

an interrupt by asserting the IRQ# output.

0: Prevents the respective STATUS bit from generating an interrupt.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Bit No.

Description

EDGE. Selects edge or level triggered interrupts:
0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the

interrupt is cleared.

1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low and return to

logic 1.

GMASK (Global Mask).
1: Enables the IRQ# output to be asserted. Setting this bit while one or more interrupts are

pending will generate an interrupt.

0: Forces the IRQ# output to the negated state.

8.12 Interrupt Status Register

Description:

This register indicates which interrupt source created an interrupt.

Address (hex): 1020

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 STATUS

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

5-0

STATUS. Indicates which of the following interrupt sources created an interrupt:
0: Flash array is ready
1: Data protection violation
2: Reading or writing more flash data than was specified in the DCNT field of ECC Control

3: BCH ECC error detected (this feature is provided to support multi-page DMA transfers)
4: Real time clock
5: Completion of a DMA operation

7-6

Reserved for future use.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.13 Output Control Register

Description:

This register controls the behavior of certain output signals. This register is reset
by a hardware reset, not by entering Reset mode.
Note: When multiple devices are cascaded, writing to this register will affect all

devices regardless of the value of the ID[1:0] inputs.

Address (hex): 1014

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 Turbo

PU_DIS

BUSY_EN

Reset Value

0 0 0 0 0 0 0 1

Bit No.

Description

BUSY_EN (Busy Enable). Controls the assertion of the BUSY# output during a download
initiated by a soft reset.
1: Enables the assertion of the BUSY# output
0: Disables the assertion of the BUSY# output
Upon the assertion of the RSTIN# input, this bit will be set automatically and the BUSY#
output signal will be asserted until the completion of the download process.

PU_DIS (Pull-up Disable). Controls the pull-up resistors D[15:8] as follows:
1: Always disable the pull-ups
0: Enable the pull-ups when IF_CFG = 0

TURBO. Activates turbo operation.
0: DiskOnChip is used in normal operation, without improved access time. Output buffers

are enabled only after a long enough delay to guarantee that there will be no more than a
single transition on each bit.

1. DiskOnChip is used in Turbo operation. Output buffers are enabled immediately after the

assertion of OE# and CE#, resulting in improved access time. Read cycles from the
Programmable Boot Block may result in additional noise and power dissipation due to
multiple transitions on the data bus.

7-3

Reserved for future use.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.15 DMA Control Register [1:0]

Description:

These two 16-bit registers specify the behavior of the DMA operation.

Address (hex): 1078/107A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 SECTOR_COUNT

Reset Value

0 0 0 0 0 0 0 0

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Read/Write

R R/W

Description

DMA_EN PAUSE EDGE POLRTY

RFU_0

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

6-0

SECTOR_COUNT. Specifies the number of 512-byte sectors to be transferred plus one.
Writing a v (a value of 0) indicates a transfer of one sector. Reading a value of 0 indicates
that there is still one sector to be transferred). This field is decremented by Mobile
DiskOnChip P3 after reading the ECC checksum from each sector. In the event of an ECC
error, this field indicates the number of sectors remaining to be transferred.

11-7

Reserved for future use.

POLRTY (Polarity). Specifies the polarity of the DMARQ# output:
0: DMARQ# is normally logic -1 and falls to initiate DMA
1: DMARQ# is normally logic -0 and rises to initiate DMA

EDGE. Controls the behavior of the DMARQ# output:
1: DMARQ# pulses to the asserted state for 250 nS (typical) to initiate the block transfer.
0: DMARQ# switches to the active state to initiate the block transfer and returns to the

negated state at the beginning of the cycle in which the DCNT field of the ECC Control
register[0] reaches the value specified by the NEGATE_COUNT field of the DMA Control
register[1].

PAUSE. This bit is set in the event of an ECC error during a DMA operation. After reading
the ECC parity registers and correcting the errors, the software must clear this bit to resume
the DMA operation.

DMA_EN (DMA Enable). Setting this bit enables DMA operation.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8.16 MultiBurst Mode Control Register

Description:

This 16-bit register controls the behavior of Mobile DiskOnChip P3 during
MultiBurst mode read cycles.

Address (hex): 101C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write

R R/W

Description

RFU_0 HOLD

CLK_INV

BST_EN

Reset Value

0 0 0 0 0 0 0 0

Bit 15

Bit 14

Bit 13

Bit 11

Bit 10

Bit 9

Bit 8

Read/Write

R/W

Description

LENGTH LATENCY

Reset Value

0 0 0 0 0 0 0 0

Bit No.

Description

BST_EN (MultiBurst Mode Enable). Enables MultiBurst mode read cycles.
0: The CLK input is disabled and may be left floating. Burst read cycles are not supported.
1: The CLK input is enabled. Subsequent read cycles must be MultiBurst mode.

CLK_INV (Clock Invert). Selects the edge of the CLK input on which CE# and OE# are
sampled.
0: CE# and OE# are sampled on the rising edge of CLK.
1: CE# and OE# are sampled on the falling edge of CLK, and there will be an additional ½

clock delay from CE#/OE# asserted until the first data word may be latched on D[15:0].

HOLD. Specifies if the data output on D[15:0] during MultiBurst mode read cycles should be
held for an additional clock cycle.
0: Data on the D[15:0] outputs is held for one clock cycle
1: Data on the D[15:0] outputs is held for two clock cycles

3-7

Reserved for future use.

8-11

LATENCY. Controls the number of clock cycles between when Mobile DiskOnChip P3
samples OE# and CE# asserted and the first word of data is available to be latched by the
host. This number of clock cycles is equal to 2 + LATECNCY. If HOLD = 1, then the data is
available to be latched on this clock and on the subsequent clock.

12-15

LENGTH. Specifies the number of byte/words (depending on IF_CFG) to be transferred in
each burst cycle:
HOLD=0: Number of bytes/words = 2 ^ LENGTH
HOLD=1: Number of bytes/words = 2 ^ (LENGTH 1)
Note: The maximum value of LENGTH is 10.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

9. B

OOTING FROM

OBILE

ISK

HIP

9.1 Introduction

Mobile DiskOnChip P3 can function both as a flash disk and as the system boot device. Mobile
DiskOnChip P3 default firmware contains drivers to enable it to perform as the OS boot device
under DOS (see Section 9.2). For other OSs, please refer to the readme file of the TrueFFS driver.
If Mobile DiskOnChip P3 is configured as a flash disk and as the system boot device, it contains the
boot loader, an OS image and a file system. In such a configuration, Mobile DiskOnChip P3 can
serve as the only non-volatile device on board. Refer to Section 9.3.2 for further information on
boot replacement.

9.2 Boot Procedure in PC-Compatible Platforms

When used in PC-compatible platforms, Mobile DiskOnChip P3 is connected to an 8KB memory
window in the BIOS expansion memory range, typically located between 0C8000H to 0EFFFFH.
During the boot process, the BIOS loads the TrueFFS firmware into the PC memory and installs
Mobile DiskOnChip P3 as a disk drive in the system. When the operating system is loaded, Mobile
DiskOnChip P3 is recognized as a standard disk. No external software is required to boot from
Mobile DiskOnChip P3.
Figure 16 illustrates the location of the Mobile DiskOnChip P3 memory window in the PC memory
map.

640k

Display

RAM

0C8000H

BIOS

0B0000H

0F0000H

0FFFFFH

DiskOnChip

Extended Memory

Figure 16: Mobile DiskOnChip P3 Memory Window in PC Memory Map

After reset, the BIOS code first executes the Power On Self-Test (POST) and then searches for all
expansion ROM devices. When Mobile DiskOnChip P3 is located, the BIOS code executes from it
the IPL code, located in the XIP portion of the Programmable Boot Block. This code loads the
TrueFFS driver into system memory, installs Mobile DiskOnChip P3 as a disk in the system, and
then returns control to the BIOS code. The operating system subsequently identifies Mobile
DiskOnChip P3 as an available disk. TrueFFS responds by emulating a hard disk.
From this point onward, Mobile DiskOnChip P3 appears as a standard disk drive. It is assigned a
drive letter and can be used by any application, without any modifications to either the BIOS set-up

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

or the autoexec.bat/config.sys files. Mobile DiskOnChip P3 can be used as the only disk in the
system, with or without a floppy drive, and with or without hard disks.
The drive letter assigned depends on how Mobile DiskOnChip P3 is used in the system, as follows:

· If Mobile DiskOnChip P3 is used as the only disk in the system, the system boots directly from

it and assigns it drive C.

· If Mobile DiskOnChip P3 is used with other disks in the system:

o Mobile DiskOnChip P3 can be configured as the last drive (the default configuration). The

system assigns drive C to the hard disk and drive D to Mobile DiskOnChip P3.

o Alternatively, Mobile DiskOnChip P3 can be configured as the system's first drive. The

system assigns drive D to the hard disk and drive C to Mobile DiskOnChip P3.

If Mobile DiskOnChip P3 is used as the OS boot device when configured as drive C, it must be
formatted as a bootable device by copying the OS files onto it. This is done by using the SYS
command when running DOS.

9.3 Boot

Replacement

9.3.1 PC

Architectures

In current PC architectures, the first CPU fetch (after reset is negated) is mapped to the boot device
area, also known as the reset vector. The reset vector in PC architectures is located at address
FFFF0, by using a Jump command to the beginning of the BIOS chip (usually F0000 or E0000).
The CPU executes the BIOS code, initializes the hardware and loads Mobile DiskOnChip P3
software using the BIOS expansion search routine (e.g. D0000). Refer to Section 9.2 for a detailed
explanation on the boot sequence in PC-compatible platforms.
Mobile DiskOnChip P3 implements both disk and boot functions when it replaces the BIOS chip.
To enable this, Mobile DiskOnChip P3 requires a location at two different addresses:

· After power-up, Mobile DiskOnChip P3 must be mapped in F segment, so that the CPU fetches

the reset vector from address FFFF0, where Mobile DiskOnChip P3 is located.

· After the BIOS code is loaded into RAM and starts execution, Mobile DiskOnChip P3 must be

reconfigured to be located in the BIOS expansion search area (e.g. D0000) so it can load the
TrueFFS software.

This means that the CS# signal must be remapped between two different addresses. For further
information on how to achieve this, refer to application note AP-DOC-047, Designing DiskOnChip
as a Flash Disk and Boot Device Replacement.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

9.3.2 Non-PC

Architectures

In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually
loaded from the storage device.
When using Mobile DiskOnChip P3 as the system boot device, the CPU fetches the first
instructions from the Mobile DiskOnChip P3 Programmable Boot Block, which contains the IPL.
Since in most cases this block cannot hold the entire boot loader, the IPL runs minimum
initialization, after which the Secondary Program Loader (SPL) is copied to RAM from flash. The
remainder of the boot loader code then runs from RAM.
The IPL and SPL are located in a separate (binary) partition on Mobile DiskOnChip P3, and can be
hardware protected if required. .

9.3.3 Asynchronous Boot Mode

Platforms that host CPUs that wake up in MultiBurst mode should use Asynchronous Boot mode
when using Mobile DiskOnChip P3 as the system boot device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch
cycles continuously. An XScale CPU, for example, initiates a 16-bit read cycle, but after the first
word is read, it continues to hold CE# and OE# asserted while it increments the address and reads
additional data as a burst. A StrongARM CPU wakes up in 32-bit mode and issues double-word
instruction fetch cycles.
Since Mobile DiskOnChip P3 derives its internal clock signal from the CE#, OE# and WE# inputs,
it cannot distinguish between these burst cycles. To support this type of access, Mobile DiskOnChip
P3 must be set in Asynchronous Boot mode by setting the RAM MODE SELECT byte to 8FH. This
can be done through the Mobile DiskOnChip P3 format utility or by customizing the IPL code. For
more information on the format utility, refer to the DiskOnChip Software Utilities user manual or
the TrueFFS Software Development Kit (SDK) developer guide.
Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the Mobile
DiskOnChip P3 Programmable Boot Block. After reading from this block and completing boot,
Mobile DiskOnChip P3 returns to derive its internal clock signal from the CE#, OE# and WE#
inputs. Please refer to Section 11.3 for read timing specifications for Asynchronous Boot mode.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10. D

ESIGN

ONSIDERATIONS

10.1 General Guidelines

A typical RISC processor memory architecture is shown in Figure 17. It may include the following
devices:
· Mobile DiskOnChip P3: Contains the OS image, applications, registry entries, back-up data,

user files and data, etc. It can also be used to perform boot operation, thereby replacing the
need for a separate boot device.

· CPU: Mobile DiskOnChip P3 is compatible with all major CPUs in the mobile market,

including:
o ARM-based

CPUs

o Texas Instruments OMAP
o Intel StrongARM SA-1100/1 and XScale
o SuperH

SH-3/4

o Motorola PowerPC MPC8xx and DragonBall MX1
o Philips PR31700
o NEC VRSeries VR3/4xxxx

· Boot Device: ROM or NOR flash that contains the boot code required for system initialization,

kernel relocation, loading the operating systems and/or other applications and files into the
RAM and executing them.

· RAM/DRAM Memory: This memory is used for code execution.
· Other Devices: A DSP processor, for example, may be used in a RISC architecture for

enhanced multimedia support.

Mobile

DiskOnChip P3

Boot ROM or NOR Flash

Boot Device

CPU

RAM/DRAM

Other Devices

When used as a boot device, Mobile DiskOnChip P3 eliminates the need for a dedicated boot ROM/NOR device.

Figure 17: Typical System Architecture Using Mobile DiskOnChip P3

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.2 Standard NOR-Like Interface

Mobile DiskOnChip P3 uses a NOR-like interface that can easily be connected to any
microprocessor bus. With a standard interface, it requires 13 address lines, 8 data lines and basic
memory control signals (CE#, OE#, WE#), as shown in Figure 18 below. Typically, Mobile
DiskOnChip P3 can be mapped to any free 8KB memory space. In a PC-compatible platform, it is
usually mapped into the BIOS expansion area. If the allocated memory window is larger than 8KB,
an automatic anti-aliasing mechanism prevents the firmware from being loaded more than once
during the ROM expansion search.

Mobile

DiskOnChip P3

Address*

Data

Output Enable

Write Enable

Chip Enable

Reset

Chip ID

VSS

3.3 V

BUSY#

10 nF

0.1 uF

VCC

VCCQ

D[15:0]

OE#

WE#

CE#

RSTIN

ID[1:0]

A[12:0]

10 nF

0.1 uF

1.8V or 3.3V

LOCK#

CLK

IRQ#

DMARQ#

DPD

1-20 KOhm

(*) Address A0 is multiplexed with the DPD signal.

Figure 18: Standard System Interface

Notes: 1. The 0.1 µF and the 10 nF low-inductance high-frequency capacitors must be attached to

each of the device's VCC and VSS pins/balls. These capacitors must be placed as close
as possible to the package leads.

2. Mobile DiskOnChip P3 is an edge-sensitive device. CE#, OE# and WE# should be

properly terminated (according to board layout, serial parallel or both terminations) to
avoid signal ringing.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.3 Multiplexed Interface

With a multiplexed interface, Mobile DiskOnChip P3 requires the signals shown in Figure 19
below.

Mobile

DiskOnChip P3

Address/Data

AVD#

Output Enable

Write Enable

Chip Enable

Reset

Chip ID

VSS

3.3 V

BUSY#

10 nF

0.1 uF

VCC

VCCQ

AVD#

OE#

WE#

CE#

RSTIN

ID0

AD[15:0]

10 nF

0.1 uF

1.8V or 3.3V

LOCK#

DMARQ#

CLK

IRQ#

DPD

1-20 KOhm

Figure 19: Multiplexed System Interface

10.4 Connecting Control Signals

10.4.1 Standard Interface

When using a standard NOR-like interface, connect the control signals as follows:

· A[12:0] Connect these signals to the host's address signals (see Section 10.8 for

platform-related considerations). Address signal A[0] is multiplexed with the DPD signal.

· D[15:0] Connect these signals to the host's data signals (see Section 10.8 for platform-related

considerations).

· Output Enable (OE#) and Write Enable (WE#) Connect these signals to the host RD# and

WR# signals, respectively.

· Chip Enable (CE#) Connect this signal to the memory address decoder. Most RISC

processors include a programmable decoder to generate various Chip Select (CS) outputs for
different memory zones. These CS signals can be programmed to support different wait states
to accommodate Mobile DiskOnChip P3 timing specifications.

· Power-On Reset In (RSTIN#) Connect this signal to the host active-low Power-On Reset

signal.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

· Chip Identification (ID[1:0]) Connect these signals as shown in Figure 18. Both signals must

be connected to VSS if the host uses only one DiskOnChip. If more than one device is being
used, refer to Section 10.6 for more information on device cascading.

· Busy (BUSY#) This signal indicates when the device is ready for first access after reset. It

may be connected to an input port of the host, or alternatively it may be used to hold the host in
a wait-state condition. The later option is required for hosts that boot from Mobile DiskOnChip
P3.

· DMARQ# (DMA Request) Output used to control multi-page DMA operations. Connect this

output to the DMA controller of the host platform.

· IRQ# (Interrupt Request) Connect this signal to the host interrupt.
· Lock (LOCK#) Connect to a logical 0 to prevent the usage of the protection key to open a

protected partition. Connect to logical 1 in order to enable usage of protection keys.

· Deep-Power Down (DPD) multiplexed with A[0].
· 8/16 Bit Interface Configuration (IF_CFG) This signal is required for configuring the device

for 8- or 16-bit access mode. When negated, the device is configured for 8-bit access mode.
When asserted, 16-bit access mode is operative.

· Clock (CLK) This input is used to support MultiBurst operation when reading flash data.

Refer to Section 4.1 for further information on MultiBurst operation.

10.4.2 Multiplexed Interface

Mobile DiskOnChip P3 can use a multiplexed interface to connect to the multiplexed bus
(asynchronous read/write protocol). In this configuration, the ID[1] input is driven by the host's
AVD# signal, and the D[15:0] pins/balls, used for both address inputs and data, are connected to the
host AD[15:0] bus. As with a standard interface, only address bits [12:0] are significant.
This mode is automatically entered when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read cycle made to
DiskOnChip must observe the multiplexed mode protocol. See Section 11.3 for more information
about the related timing requirements.
Please refer to Section 2.3 for pinout and signal descriptions and to Section 11.3 for timing
specifications for a multiplexed interface.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.5 Implementing the Interrupt Mechanism

10.5.1 Hardware Configuration

To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to
the host interrupt input.
Note: A nominal 10 K pull-up resistor must be connected to this pin/ball.

10.5.2 Software Configuration

Configuring the software to support the IRQ# interrupt is performed in two stages.

Stage 1

Configure the software so that when the system is initialized, the following steps occur:
1. The correct value is written to the Interrupt Control register to configure Mobile DiskOnChip

P3 for:

· Interrupt source: Flash ready, data protection, last byte during DMA has been transferred,

or BCH ECC error has been detected (used during multi-page DMA operations).

· Output sensitivity: Either edge or level-triggered
Note: Refer to Section 8 for further information on the value to write to this register.

2. The host interrupt is configured to the selected input sensitivity, either edge or level-triggered.
3. The handshake mechanism between the interrupt handler and the OS is initialized.
4. The interrupt service routine to the host interrupt is connected and enabled.

Stage 2

Configure the software so that for every long flash I/O operation, the following steps occur:
1. The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.

Note: Refer to Section 8 for further information on the value to write to this register.

2. The flash I/O operation starts.
3. Control is returned to the OS to continue other tasks. When the IRQ# interrupt is received,

other interrupts are disabled and the OS is flagged.

4. The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate

condition to return control to the TrueFFS driver.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.6 Device Cascading

When connecting Mobile DiskOnChip P3 256Mb using a standard interface, up to four devices can be
cascaded with no external decoding circuitry. Figure 20 illustrates the configuration required to
cascade four devices on the host bus (only the relevant cascading signals are included in this figure,
although all other signals must also be connected). All pins/balls of the cascaded devices must be
wired in common, except for ID0 and ID1. The ID input pins/balls are strapped to VCC or VSS,
according to the location of each DiskOnChip. The ID pin/ball values determine the identity of each
device. For example, the first device is identified by connecting the ID pins/balls as 00, and the last
device by connecting the ID pins/balls as 11. Systems that use only one Mobile DiskOnChip P3
256Mb must connect the ID pins/balls as 00. Additional devices must be configured consecutively as
01, 10 and 11.
When Mobile DiskOnChip P3 256 Mb uses a multiplexed interface, the value of ID[1] is set to
logic 0. Therefore, only two devices can be cascaded using ID[0].

ID0

ID1

CE#

OE#

WE#

CE#

WE#

OE#

VSS

ID0
ID1

CE#
OE#
WE#

VSS

VCC

2nd

ID0
ID1

CE#
OE#
WE#

VCC

VSS

3rd

ID0

ID1

CE#

OE#

WE#

VCC

4th

1st

Figure 20: Standard Interface, Cascaded Configuration

Note: When more than one Mobile DiskOnChip P3 is cascaded, a boot block of 4KB is available.

The Programmable Boot Block of each device is mapped to a unique address space.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.7 Boot Replacement

A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also
required to access Mobile DiskOnChip P3 during the boot sequence in order to load OS images and
the device drivers.
M-Systems' Boot Software Development Kit (BDK)

and DOS utilities enable full control of Mobile

DiskOnChip P3 during the boot sequence. For a complete description of these products, refer to the
DiskOnChip Boot Software Development Kit (BDK) developer guide and the DiskOnChip Software
Utilities user manual. These tools enable the following operations:

· Formatting Mobile DiskOnChip P3
· Creating multiple partitions for different storage needs (OS images files, register entry files,

back-up partitions, and FAT/NFTL partition)

· Loading the OS image file
Figure 21 illustrates the system boot flow using Mobile DiskOnChip P3 in a RISC architecture.

Boot Loader

OS Image

BInary Partition

(OS Image Storage)

Flash Disk Partition

(File Storage)

Power-Up

RAM

Basic System Initialization

Boot Loader Copies
OS Image to RAM

OS Start-Up Code

Mobile DiskOnChip P3

Copy Image

to RAM

Take Image from

DiskOnChip P3

Figure 21: System Boot Flow with Mobile DiskOnChip P3

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

10.8 Platform-Specific Issues

Following is a description of hardware design issues for major embedded RISC processor families.

10.8.1 Wait State

Wait states can be implemented only when Mobile DiskOnChip P3 is designed in a bus that
supports a Wait state insertion, and supplies a WAIT signal.

10.8.2 Big and Little Endian Systems

Mobile DiskOnChip P3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least
Significant Byte (LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the
byte lanes, bit D0 and bit D8 are the least significant bits of their respective byte lanes. Mobile
DiskOnChip P3 can be connected to a Big Endian device in one of two ways:
1. Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data bus

so that the byte lanes of the CPU match the byte lanes of Mobile DiskOnChip P3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of Mobile DiskOnChip
P3, and prevents the TrueFFS driver from identifying it.

2. Set the bits SWAPH and SWAPL in the Endian Control register. This enables byte swapping

when used with 16-bit hosts.

10.8.3 Busy Signal

The Busy signal (BUSY#) indicates that Mobile DiskOnChip P3 has not yet completed internal
initialization. After reset, BUSY# is asserted while the IPL is downloaded into the internal boot
block and the Data Protection Structures (DPS) are downloaded to the Protection State Machines.
Once the download process is completed, BUSY# is negated. It can be used to delay the first access
to Mobile DiskOnChip P3 until it is ready to accept valid cycles.
Note: The TrueFFS driver does NOT use this signal to indicate that the flash is in busy state (e.g.

program, read, or erase).

10.8.4 Working with 8/16/32-Bit Systems

Mobile DiskOnChip P3 uses a 16-bit data bus and supports 16-bit data access by default. However,
it can be configured to support 8 or 32-bit data access mode. This section describes the connections
required for each mode.
The default of the TrueFFS driver for Mobile DiskOnChip P3 is set to work in 16-bit mode. It must
be specially configured to support 8 and 32-bit mode. Please see TrueFFS documentation for further
details.
Note: The DiskOnChip data bus must be connected to the Least Significant Bits (LSB) of the

system. The system engineer must verify whether the matching host signals are SD[7:0],
SD[15:8] or D[31:24].

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

8-Bit (Byte) Data Access Mode

When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines
D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even
address accesses to the appropriate byte lane of the flash and RAM.
Host address SA0 must be connected to Mobile DiskOnChip P3 A0, SA1 must be connected to A1, etc.

16-Bit (Word) Data Access Mode

To set Mobile DiskOnChip P3 to work in 16-bit mode, the IF_CFG pin/ball must be connected to VCC.
In 16-bit mode, the Programmable Boot Block is accessed as a true 16-bit device. It responds with
the appropriate data when the CPU issues either an 8-bit or 16-bit read cycle. The flash area is
accessed as a 16/32-bit device, regardless of the interface bus width. This has no affect on the
design of the interface between Mobile DiskOnChip P3 and the host. The TrueFFS driver handles
all issues regarding moving data in and out of Mobile DiskOnChip P3.
See Table 6 for A0 and IF_CFG settings for various functionalities with 8/16-bit data access.

Table 6: Active Data Bus Lines in 8/16-Bit Configuration

A0 IF_CFG

Functionality

16-bit access through both buses

8-bit access to even bytes through low 8-bit bus

8-bit access to odd bytes through low 8-bit bus

1 1

Illegal

32-Bit (Double Word) Data Access Mode

In a 32-bit bus system that cannot execute byte or word aligned accesses, the system address lines
SA0 and SA1 are always 0. Consecutive double words (32-bit words) are differentiated by SA2
toggling. Therefore, in 32-bit systems that support only 32-bit data access cycles, Mobile
DiskOnChip P3 signal A0 is connected to VSS and A1 is connected to the first system address bit
that toggles; i.e., SA2.

System

Host

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

A12

A11

A10

Mobile DiskOnChip P3

Note: The prefix "S" indicates system host address lines

Figure 22: Address Shift Configuration for 32-Bit Data Access Mode

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11. P

RODUCT

PECIFICATIONS

11.1 Environmental Specifications

11.1.1 Operating Temperature

Commercial temperature range:

0°C to +70°C

Extended temperature range: -40°C to +85°C

11.1.2 Thermal Characteristics

Table 7: Thermal Characteristics

Thermal Resistance (

°C/W)

Junction to Case (

): 30

Junction to Ambient (

): 85

11.1.3 Humidity

10% to 90% relative, non-condensing

11.1.4 Endurance

Mobile DiskOnChip P3 is based on NAND flash technology, which guarantees a minimum of
100,000 erase cycles. Due to the TrueFFS wear-leveling algorithm, the life span of all DiskOnChip
products is significantly prolonged. M-Systems' website (

www.m-sys.com

) provides an online life-

span calculator to facilitate application-specific endurance calculations.

11.2 Electrical Specifications

11.2.1 Absolute Maximum Ratings

Table 8: Absolute Maximum Ratings

Symbol Parameter Rating1

Unit

VCC

DC core supply voltage

-0.6 to 4.6

VCCQ

DC I/O supply voltage

-0.6 to 4.6

1SUPPLY

Maximum duration of applying
VCCQ without VCC, or VCC
without VCCQ

1000

mse

Input pin/ball current (25

°C)

-10 to 10

Input pin/ball voltage

-0.6 to VCCQ+0.3V, 4.6V max

STG

Storage temperature

-55 to 150

°C

ESD: Charged Device Model ESD

CDM

1000 V

ESD: Human Body Model

ESD

HBM

2000

Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

The voltage on any ball may undershoot to -2.0 V or overshoot to 6.6V for less than 20 ns.

When operating Mobile DiskOnChip P3 with separate power supplies for VCC and VCCQ, it is recommended to turn both supplies on
and off simultaneously. Providing power separately (either at power-on or power-off) can cause excessive power dissipation. Damage to
the device may result if this condition persists for more than 1 second.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.2.2 Capacitance

Table 9: Capacitance

Symbol Parameter Conditions

Min

Typ

Max

Unit

Input capacitance

= 0V

OUT

Output capacitance

= 0V

Capacitance is not 100% tested.

11.2.3 DC Electrical Characteristics Over Operating Range

See Table 10 and Table 11 for DC characteristics for VCCQ ranges 1.65-2.0V and 2.5-3.6V I/O,
respectively.

Table 10: DC Characteristics, VCCQ = 1.65-2.0V I/O

Symbol Parameter

Conditions

Min

Typ

Max

Unit

VCC

Core supply voltage

2.5

3.0

3.6

VCCQ

Input/Output supply voltage

1.65

1.8

2.00

High-level input voltage

VCCQ

0.4

Low-level input voltage

0.4

High-level output voltage

= -100µA VCCQ

0.1

D[15:0] I

= 100µA

0.1

Low-level output voltage

IRQ#, BUSY#, DMARQ#
4mA

0.3

ILK

Input leakage current

±10

µA

IOLK

Output leakage current

±10

µA

Active supply current

, VCC

pin/ball

Cycle Time = 100 ns

CCS

Standby supply current, VCC
pin/ball

Deep Power-Down mode³

µA

VCC = 3V,

VCCQ

= 1.8V, Outputs open

The CE# input includes a pull-up resistor which sources 0.3~1.4 (TBD) uA at Vin=0V

Deep Power-Down mode is achieved by asserting RSTIN# (when in Normal mode) or writing the proper write sequence to the
DiskOnChip registers, and asserting the CE# input = VCCQ.

Table 11: DC Characteristics, VCCQ = 2.5V-3.6V

Symbol Parameter

Conditions Min

Typ

Max

Unit

VCC

Core supply voltage

2.5

3.3

3.6

VCCQ

Input/Output supply voltage

2.5

3.3

3.6

High-level input voltage

2.1

Low-level input voltage

0.7

3.0V < VCCQ < 3.6V

-4

OHmax

Maximum high level output
current

2.5V < VCCQ < 3.0V

-4

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Symbol Parameter

Conditions Min

Typ

Max

Unit

3.0V < VCCQ < 3.6V

OLmax

Maximum low-level output
current

2.5V < VCCQ < 3.0V

ILK

Input leakage current

±10

µA

IOLK

Output leakage current

±10

µA

OH =

Ohmax

2.5V < VCCQ < 2.7V

VCCQ-

0.3

High-level output voltage

OH =

Ohmax

2.5V < VCCQ < 3.6V

2.4

Low-level output voltage

OL=

OLmax

0.4

Active supply current,
VCC+VCCQ pins/balls

Cycle Time = 100 ns

CCS

Standby supply current,
VCC+VCCQ pins/balls

Deep Power-Down mode

10 40 µA

VCC = VCCQ = 3.3V, Outputs open

The CE# input includes a pull-up resistor which sources 0.3~1.4 (TBD)

µA at Vin=0V

Deep Power-Down mode is achieved by asserting RSTIN# (when in Normal mode) or writing the proper write sequence to the
DiskOnChip registers, and asserting the CE# input = VCCQ.

11.2.4 AC Operating Conditions

Timing specifications are based on the conditions defined below.

Table 12: AC Characteristics

Parameter

VCCQ = 1.65-2.0V

VCCQ = 2.5-3.6V

Ambient temperature (TA)

-40°C to +85°C

Core supply voltage (VCC)

2.5V to 3.6V

Input pulse levels

0.2/VCCQ-0.2V

0V/2.5V

Input rise and fall times

3 ns

Input timing levels

0.9V

1.5V

Output timing levels

0.9V

1.5V

Output load

30 pF

100 pF

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

Table 13: Standard Interface Read Cycle Timing Parameters

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

Tsu(A)

Address to OE#

setup

time

-2 -2

Tho(A) OE#

to Address hold time

24 24

Tsu(CE0) CE# to OE# setup time

-- --

Tho(CE0) OE# to CE# hold time

-- --

Tho(CE1) OE# or WE# to CE#

hold

time

5 5

Tsu(CE1) CE# to WE# or OE#

setup

time 5 5

Trec(OE)

OE# negated to start of next cycle

Turbo operation

Read access time
(RAM)

Normal operation

Turbo operation

Tacc

Read access time (all
other addresses)

Normal operation

OE# to D driven

Turbo

operation

5 5

Tloz(D)

OE# to D driven

Normal

operation

14 14

Thiz(D) OE#

to D Hi-Z delay

TBD TBD

tacc(A)

RAM Read access
time from A[9:0]

Asynchronous
Boot mode

tho(A-D)

Data hold time from
A[9:0] (RAM)

Asynchronous
Boot mode

0 0

Add 260 ns (TBD) on the first read cycle when exiting Power-Down mode. See Section 6.3 for more information.

CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to when OE# was asserted
will be referenced to the time CE# was asserted.

CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to when OE# was negated
will be referenced to the time CE# was negated.

No load (C

= 0 pF).

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.3.2 Write Cycle Timing Standard Interface

CE#

A[12:0]

REC

(WE)

(CE1)

(CE0)

(D)

(WE)

(D)

(A)

OE#

D[15:0]

WE#

(CE1)

WCYC

Figure 25: Standard Interface Write Cycle Timing

Table 14: Standard Interface Write Cycle Parameters

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

(A)

Address to WE#

setup

time

-2 -2

Tho(A) WE#

to Address hold time

WE# asserted width (RAM)

Tw(WE)

WE# asserted width (all other addresses)

Tsu(CE0) CE# to WE# setup time

-- --

Tho(CE0) WE# to CE# hold time

-- --

Tho(CE1)

OE# or WE# to CE#

hold

time 5 5

Tsu(CE1) CE# to WE# or OE#

setup

time

5 5

Trec(WE) WE# to start of next cycle

Tsu(D)

D to WE#

setup

time

27 27

Tho(D) WE#

to D hold time

CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted should be
referenced to the time CE# was asserted.

CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will be
referenced to the time CE# was negated.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.3.3 Read Cycle Timing Multiplexed Interface

CE#

AD[15:0]

REC

(OE)

(CE1)

(CE0)

(CE1)

(CE0)

HIZ

(D)

ACC

(AVD)

OE#

WE#

AVD#

(AVD)

ADDR DATA

(AVD-OE)

Figure 26: Multiplexed Interface Read Cycle Timing

Table 15: Multiplexed Interface Read Cycle Parameters

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

(AVD-OE) AVD# to OE# hold time

tsu(CE0) CE#

to OE# setup time

tho(CE0) OE#

to CE# hold time

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1) CE#

to WE# or OE# setup time

trec(OE)

OE# negated to start of next cycle

Turbo operation

Read access time
(RAM)

Normal operation

Turbo operation

Tacc

Read access time
(all other addresses) Normal operation

Turbo operation

tloz(D)

OE# to D driven

Normal operation

Thiz(D) OE#

to D Hi-Z delay

TBD

CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time of CE# asserted.

CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.

No load (C

= 0 pF).

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.3.4 Write Cycle Timing Multiplexed Interface

CE#

REC

(WE)

(CE1)

(CE0)

(D)

tw(WE)

(D)

OE#

WE#

(CE1)

WCYC

AD[15:0]

(AVD)

AVD#

tw(AVD)

ADDR

DATA

(AVD-WE)

REC

(WE-AVD)

NEXT ADDR

Figure 27: Multiplexed Interface Write Cycle Timing

Table 16: Multiplexed Interface Write Cycle Parameters

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

tsu(AVD-WE) AVD# to WE# setup time

WE# asserted width (RAM)

tw(WE)

WE# asserted width (all other addresses)

tsu(CE0) CE#

to WE# setup time

tho(CE0) WE#

to CE# hold time

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1) CE#

to WE# or OE# setup time

trec(WE) WE#

to start of next cycle

Tsu(D)

D to WE# setup time

Tho(D) WE#

to D hold time

CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted will be
referenced instead to the time of CE# asserted.

CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will be
referenced instead to the time of CE# negated.

WE# may be asserted before or after the rising edge of AVD#. The beginning of the WE# asserted pulse width spec is measured from the
later of the falling edge of WE# or the rising edge of AVD#.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

11.3.5 Read Cycle Timing MultiBurst

In Figure 28, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0.

CLK

OE#

D[15:0]

(HOLD=0)

D[15:0]

(HOLD=1)

(CLK-D)

LOZ

(D)

REC

(OE)

(OE0-CLK1)

HIZ

(D)

Insert LATENCY clock cycles

t(CLK)

(OE0-CLK0)

(OE0-CLK1)

(CLK0)

(CLK1)

Figure 28: MultiBurst Read Timing

Note: Shown with Burst Mode Controller register values: LATENCY=0, LENGTH=4.

Table 17: MultiBurst Read Cycle Parameters

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

(OE0-CLK1) OE# to CLK setup time

1, 4

(OE0-CLK0) OE# to CLK setup time

1, 5

(OE0-CLK1) CLK to OE# hold time

1, 4

(OE0-CLK0) CLK to OE# hold time

1, 5

(CLK-D) CLK

to D delay

CLK high pulse width

(CLK1)

CLK high pulse width

CLK low pulse width

(CLK0)

CLK low pulse width

CLK period

t(CLK)

CLK period

REC

(OE)

OE# negated to start of next cycle

9 9 ns

LOZ

(D)

OE# to D
driven

1,3

Turbo operation

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-2.0V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

OE#

to D

driven

1,3

Normal operation

HIZ

(D) OE#

to D Hi-Z delay

TBD

CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time of CE# asserted.

CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.

No load (CL = 0 pF).

Applicable only if the CLK_INV bit of the MultiBurst Mode Control register is 0.

Applicable only if the CLK_INV bit of the MultiBurst Mode Control register is 1.

Applicable only if the HOLD bit of the MultiBurst Mode Control register is 0.

Applicable only if the HOLD bit of the MultiBurst Mode Control register is 1

11.3.6 Power Supply Sequence

When operating Mobile DiskOnChip P3 with separate power supplies powering the VCCQ and
VCC rails, it is desirable to turn both supplies on and off simultaneously. Providing power to one
supply rail and not the other (either at power-on or power-off) can cause excessive power
dissipation. Damage to the device may result if this condition persists for more than 500 msec.

11.3.7 Power-up Timing

Mobile DiskOnChip P3 is reset by assertion of the RSTIN# input. When this signal is negated,
Mobile DiskOnChip P3 initiates a download procedure from the flash memory into the internal
Programmable Boot Block. During this procedure, Mobile DiskOnChip P3 does not respond to read
or write accesses.
Host systems must therefore observe the requirements described below for first access to Mobile
DiskOnChip P3. Any of the following methods may be employed to guarantee first-access timing
requirements:

· Use a software loop to wait at least Tp (BUSY1) before accessing the device after the reset

signal is negated.

· Poll the state of the BUSY# output.
· Poll the DL_RUN bit of the Download Status register until it returns 0. The DL_RUN bit will

be 0 when BUSY# is negated.

· Use the BUSY# output to hold the host CPU in wait state before completing the first access

which will be a RAM read cycle. The data will be valid when BUSY# is negated.

Hosts that use Mobile DiskOnChip P3 to boot the system must employ option 4 above or use
another method to guarantee the required timing of the first-time access.

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

RSTIN#

VCC

BUSY#

VCC = 2.5V

VCCQ = 1.65 or 2.5V

(BUSY1)

REC

(VCC-RSTIN)

CE#, OE#
(WE# = 1)

(VCC-BUSY0)

(D-BUSY1)

D (Read cycle)

(RSTIN)

(BUSY0)

AVD#

(Muxed Mode Only)

(DPD/RSTIN-AVD)

A[12:0]

VALID

DPD (A[0])

(DPD/RSTIN-D)

Figure 29: Reset Timing

Table 18: Power-Up Timing Parameters

Symbol Description

Min

Max

Units

REC

(VCC-RSTIN)

VCC/VCCQ stable to RSTIN#

500

µs

(RSTIN)

RSTIN# asserted pulse width

(BUSY0)

RSTIN# to BUSY#

(BUSY1)

RSTIN# to BUSY#

1055

µs

(D-BUSY1)

Data valid to BUSY#

(VCC-BUSY0)

VCC/VCCQ stable to BUSY#

500

µs

(DPD/RSTIN-AVD)

4,6

DPD transition or RSTIN# to AVD# 600 nS

(DPD/RSTIN-D)

5,6

DPD transition or RSTIN# to Data valid

660

Specified from the final positive crossing of VCC above 2.7V and VCCQ above 1.65 or 2.5V.

If the assertion of RSTIN# occurs during a flash erase cycle, this time could be extended by up to 500

µS.

Normal read/write cycle timing applies. This parameter applies only when the cycle is extended until the negation of the BUSY# signal.

Applies to multiplexed interface only.

Applies to SRAM mode only.

DPD transition refers to exiting Deep Power Down mode by toggling DPD (A[0]).

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

12. O

RDERING

NFORMATION

MDxxxx-Dxxx-xxx-T-C

Device Code

5811 - DiskOnChip P3 TSOP-I
5832 - DiskOnChip P3 FBGA (7x10)

Capacity

D- MByte
d- Mbit

xxx - Value

Supply Voltage

V3Q18 - 3.3V core, 1.8V I/O

Temperature

X - Extended: -40

C to +85

Blank - Commerical 0

C to 70

Composition

P - Lead (Pb) free

Blank - Regular

Figure 34: Ordering Information Structure

Refer to Table 21 for combinations currently available and the associated order numbers.

Table 21: Available Combinations

Capacity

Ordering code

MB Mb

Package

Temperature

Range

MD5811-d256-V3Q18 Commercial
MD5811-d256-V3Q18-X

48-pin TSOP-I

Extended

MD5811-d256-V3Q18-P Pb-free

Commercial

MD5811-d256-V3Q18-X-P

48-pin TSOP-I

Pb-free Extended

MD5832-d256-V3Q18-X

85-ball FBGA 7x10

Extended

MD5832-d256-V3Q18-X-P

32 256

85-ball FBGA 7x10

Pb-free

Extended

MD5832-d00-DAISY 00

000

85-ball FBGA 7x10

Daisy-Chain

Daisy-chain format for package

reliability testing

MD5811-d256-MECH 00

000

48-pin TSOP-I

MD5832-d256-MECH 00

000

85-ball FBGA 7x10

Mechanical sample

Mobile DiskOnChip P3

Data Sheet, Rev. 0.3

93-SR-009-8L

OW TO

ONTACT

USA
M-Systems Inc.
8371 Central Ave, Suite A
Newark CA 94560
Phone: +1-510-494-2090
Fax: +1-510-494-5545

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Shenzhen, China 518001
Phone: +86-755-2519-4732
Fax: +86-755-2519-4729

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Kfar Saba 44425, Israel
Tel: +972-9-764-5000
Fax: +972-3-548-8666

Internet

http://www.m-sys.com

General Information

info@m-sys.com

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M-Systems Japan Inc.
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5-25-16 Higashi-Gotanda
Shinagawa-ku Tokyo, 141-0022
Phone: +81-3-5423-8101
Fax: +81-3-5423-8102

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M-Systems Asia Ltd.
Room B, 13 F, No. 133 Sec. 3
Min Sheng East Road
Taipei, Taiwan
R.O.C.
Tel: +886-2-8770-6226
Fax: +886-2-8770-6295

Sales and Technical Information

techsupport@m-sys.com

This document is for information use only and is subject to change without prior notice. M-Systems Flash Disk Pioneers Ltd. assumes no
responsibility for any errors that may appear in this document. No part of this document may be reproduced, transmitted, transcribed, stored in a
retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic,
optical, chemical, manual or otherwise, without prior written consent of M-Systems.

M-Systems products are not warranted to operate without failure. Accordingly, in any use of the Product in life support systems or other
applications where failure could cause injury or loss of life, the Product should only be incorporated in systems designed with appropriate and
sufficient redundancy or backup features.

Contact your local M-Systems sales office or distributor, or visit our website at www.m-sys.com to obtain the latest specifications before placing
your order.

M-Systems® is a registered trademark. DiskOnChip®, DiskOnChip Millennium®, DiskOnKey®, Smart DiskOnKey® and TrueFFS® are
registered trademarks of M-Systems. DiskOnKey MyKeyTM, FFDTM, Fly-ByTM, iDiskOnChipTM, iDOCTM, mDiskOnChipTM, mDOCTM,
Mobile DiskOnChipTM, SuperMAPTM, uDiskOnChipTM and uDOCTM are trademarks of M-Systems. Other product names mentioned in this
document may be trademarks or registered trademarks of their respective owners and are hereby acknowledged.

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