DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 256Mb F-die
with 64/72-bit Non-ECC / ECC
Revision 1.2
May. 2004
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Revision History
Revision 1.0 (August, 2003
)
- First release
Revision 1.1 (August, 2003)
- Added K4H560838F based Module.
Revision 1.2 (May, 2004)
- Modified IDD current spec.
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Ordering Information
Operating Frequencies
Part Number
Density
Organization
Component Composition
Height
M368L1624FTM-C(L)B3/AA/A2/B0
128MB
16M x 64
16Mx16 (K4H561638F) * 4EA
1,250mil
M368L3223FTN-C(L)B3/AA/A2/B0
256MB
32M x 64
32Mx8 (K4H560838F) * 8EA
1,250mil
M381L3223FTM-C(L)B3/AA/A2/B0
256MB
32M x 72
32Mx8 (K4H560838F) * 9EA
1,250mil
M368L6423FTN-C(L)B3/AA/A2/B0
512MB
64M x 64
32Mx8 (K4H560838F) * 16EA
1,250mil
M381L6423FTM-C(L)B3/AA/A2/B0
512MB
64M x 72
32Mx8 (K4H560838F) * 18EA
1,250mil
B3(DDR333@CL=2.5)
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
133MHz
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
133MHz
CL-tRCD-tRP
2.5-3-3
2-2-2
2-3-3
2.5-3-3
Feature
Power supply : Vdd: 2.5V
0.2V, Vddq: 2.5V
0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1,250 (mil), single (128MB, 256MB), double (512MB) sided
184Pin Unbuffered DIMM based on 256Mb F-die (x8, x16)
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Pin Configuration (Front side/back side)
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72(M381 ~ ) module, and are not used on x64(M368 ~ ) module.
3. Pins 111, 158 are NC for 1row modules [ M368L1624FTM, M368(81)L3223FTN(M)] & used for 2row modules
[M368(81)L6423FTN(M) ] .
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
CB6
VDDQ
CB7
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
KEY
KEY
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
DM0 ~ 7, 8(for ECC)
Data - in mask
BA0 ~ BA1
Bank Select Address
VDD
Power supply (2.5V)
DQ0 ~ DQ63
Data input/output
VDDQ
Power Supply for DQS(2.5V)
DQS0 ~ DQS8
Data Strobe input/output
VSS
Ground
CK0,CK0 ~ CK2, CK2
Clock input
VREF
Power supply for reference
CKE0, CKE1(for double banks) Clock enable input
VDDSPD
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
CS0, CS1(for double banks)
Chip select input
SDA
Serial data I/O
RAS
Row address strobe
SCL
Serial clock
CAS
Column address strobe
SA0 ~ 2
Address in EEPROM
WE
Write enable
NC
No connection
CB0 ~ CB7 (for x72 module)
Check bit(Data-in/data-out)
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
DQ8
DQ9
DQ10
DQ11
LDM
I/O 6
I/O 4
I/O 1
I/O 3
D0
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 0
I/O 5
I/O 7
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ24
DQ25
DQ26
DQ27
LDQS
I/O 6
I/O 4
I/O 1
I/O 3
D1
DQ28
DQ29
DQ30
DQ31
I/O 2
I/O 0
I/O 5
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ56
DQ57
DQ58
DQ59
I/O 6
I/O 4
I/O 1
I/O 3
D3
DQ60
DQ61
DQ62
DQ63
I/O 2
I/O 0
I/O 5
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ40
DQ41
DQ42
DQ43
I/O 6
I/O 4
I/O 1
I/O 3
D2
DQ44
DQ45
DQ46
DQ47
I/O 2
I/O 0
I/O 5
I/O 7
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ32
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DM1
CS
CS
CS
CS
LDQS
DQS1
DM0
DQS0
DM3
DQS3
DM2
DQS2
DM5
DQS5
DM4
DQS4
DM6
DQS6
DM7
DQS7
UDQS
LDM
UDM
UDQS
LDM
UDM
LDQS
UDQS
A0 - A12
A0-A12: DDR SDRAMs D0 - D3
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D3
RAS
RAS: DDR SDRAMs D0 - D3
CAS
CAS: DDR SDRAMs D0 - D3
CKE0
CKE: DDR SDRAMs D0 - D3
WE
WE: DDR SDRAMs D0 - D3
UDM
UDQS
LDM
LDQS
Clock Wiring
CK0/CK0
Clock
Input
DDR SDRAMs
CK1/CK1
0 DDR SDRAM
2 DDR SDRAMs
2 DDR SDRAMs
CK2/CK2
CS0
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
V
SS
D0 - D3
D0 - D3
V
DD
/V
DDQ
D0 - D3
D0 - D3
VREF
V
DDSPD
SPD
Notes:
1. DQ-to-I/O wiring is shown as recomended but
may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms
+ 5%
128MB, 16M x 64 Non ECC Module (M368L1624FTM)
(Populated as 1 bank of x16 DDR SDRAM Module)
Functional Block Diagram
Card
Edge
Cap/D0/*Cap
Cap/Cap/Cap
Cap/*Cap/D2
Cap/Cap/Cap
Cap/D1/D3
Cap/Cap/Cap
R=120
CK0/1/2
CK0/1/2
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
CS0
DQS0
DM0
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/
CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/
CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/
CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/
CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
256MB, 32M x 64 Non ECC Module (M368L3223FTN)
(Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
A0 - A12
A0-A12 : DDR SDRAMs D0 - D7
RAS
RAS : DDR SDRAMs D0 - D7
CAS
CAS : DDR SDRAMs D0 - D7
WE
WE : DDR SDRAMs D0 - D7
CKE0
CKE : DDR SDRAMs D0 - D7
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D7
V
SS
D0 - D7
V
DD
/V
DDQ
D0 - D7
D0 - D7
VREF
V
DDSPD
SPD
D0 - D7
*Clock Net Wiring
* Clock Wiring
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR SDRAMs
3 DDR SDRAMs
2 DDR SDRAMs
Card
Edge
D3/D0/D6
Cap/Cap/Cap
D4/D1/D7
Cap/Cap/Cap
D5/D2/Cap
Cap/Cap/Cap
R=120
CK0/1/2
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
CK0/1/2
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
256MB, 32M x 72 ECC Module (M381L3223FTM)
(Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
A0 - A12
A0-A12 : DDR SDRAMs D0 - D8
RAS
RAS : DDR SDRAMs D0 - D8
CAS
CAS : DDR SDRAMs D0 - D8
WE
WE : DDR SDRAMs D0 - D8
CKE0
CKE : DDR SDRAMs D0 - D8
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D8
V
SS
D0 - D8
V
DD
/V
DDQ
D0 - D8
D0 - D8
VREF
V
DDSPD
SPD
D0 - D8
*Clock Net Wiring
* Clock Wiring
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
CS0
DQS0
DM0
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/
CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/
CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/
CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/
CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS8
DM8
DM/
CS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
Card
Edge
D3/D0/D6
Cap/Cap/Cap
D4/D1/D7
Cap/Cap/Cap
D5/D2/D8
Cap/Cap/Cap
R=120
CK0/1/2
CK0/1/2
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
512MB, 64M x 64 Non ECC Module (M368L6423FTN)
(Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/
CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/
CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/
CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/
CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM/
CS DQS
D8
DM/
CS DQS
D9
DM/
CS DQS
D10
DM/
CS DQS
D11
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM/
CS DQS
D12
DM/
CS DQS
D13
DM/
CS DQS
D14
DM/
CS DQS
D15
CS1
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
A0 - A12
A0-A12: DDR SDRAMs D0 - D15
RAS
RAS : DDR SDRAMs D0 - D15
CAS
CAS : DDR SDRAMs D0 - D15
WE
WE : DDR SDRAMs D0 - D15
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D15
V
SS
D0 - D15
V
DD
/V
DDQ
D0 - D15
D0 - D15
VREF
V
DDSPD
SPD
D0 - D15
*Clock Net Wiring
* Clock Wiring
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
Card
Edge
D3/D0/D5
D11/D8/D13
Cap/D1/D6
Cap/D9/D14
D4/D2/D7
D12/D10/D15
R=120
CK0/1/2
*
*
CKE 0/1
CKE : DDR SDRAMs D0 - D15
CK0/1/2
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms +
5%
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
512MB, 64M x 72 ECC Module (M381L6423FTM)
(Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/
CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/
CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/
CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/
CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM/
CS DQS
D9
DM/
CS DQS
D10
DM/
CS DQS
D11
DM/
CS DQS
D12
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM/
CS DQS
D13
DM/
CS DQS
D14
DM/
CS DQS
D15
DM/
CS DQS
D16
CS1
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
A0 - A12
A0-A12 : DDR SDRAMs D0 - D17
RAS
RAS : DDR SDRAMs D0 - D17
CAS
CAS : DDR SDRAMs D0 - D17
WE
WE : DDR SDRAMs D0 - D17
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D17
V
SS
D0 - D17
V
DD
/V
DDQ
D0 - D17
D0 - D17
VREF
V
DDSPD
SPD
D0 - D17
*Clock Net Wiring
* Clock Wiring
Clock
Input
DDR SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
CKE0/1
CKE : DDR SDRAMs D0 - D17
DQS8
DM8
DM/
CS DQS
D8
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM/
CS DQS
D17
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms +
5%
Card
Edge
D3/D0/D5
D12/D9/D14
D8/D1/D6
D17/D10/D15
D4/D2/D7
D13/D11/D16
R=120
CK0/1/2
CK0/1/2
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
& V
DDQ
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1.5 * # of component
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70
C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V)
V
DD
2.3
2.7
I/O Supply voltage
V
DDQ
2.3
2.7
V
I/O Reference voltage
V
REF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
Input Voltage Level, CK and CK inputs
V
IN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and CK inputs
V
ID
(DC)
0.36
V
DDQ
+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver) ;V
OUT
= V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver) ;V
OUT
= V
TT
- 0.45V
I
OL
9
mA
1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
Note :
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
DDR SDRAM IDD spec table
(V
DD
=2.7V, T = 10
C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
360
320
320
320
mA
IDD1
500
460
460
460
mA
IDD2P
12
12
12
12
mA
IDD2F
100
80
80
80
mA
IDD2Q
80
72
72
72
mA
IDD3P
140
120
120
120
mA
IDD3N
220
180
180
180
mA
IDD4R
800
680
680
680
mA
IDD4W
760
620
620
620
mA
IDD5
720
660
660
660
mA
IDD6
Normal
12
12
12
12
mA
Low power
6
6
6
6
mA
Optional
IDD7A
1,400
1,200
1,200
1,200
mA
M368L1624FTM [ (16M x 16) * 4, 128MB Non ECC Module ]
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
(V
DD
=2.7V, T = 10
C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
720
720
640
640
mA
IDD1
920
920
840
840
mA
IDD2P
24
24
24
24
mA
IDD2F
240
200
200
200
mA
IDD2Q
200
185
185
185
mA
IDD3P
280
240
240
240
mA
IDD3N
440
360
360
360
mA
IDD4R
1,280
1,120
1,120
1,120
mA
IDD4W
1,280
1,080
1,080
1,080
mA
IDD5
1,360
1,280
1,280
1,280
mA
IDD6
Normal
24
24
24
24
mA
Low power
12
12
12
12
mA
Optional
IDD7A
2,240
2,240
2,080
2,080
mA
DDR SDRAM IDD spec table
M368L3223FTN [ (32M x 8) * 8, 256MB Non ECC Module ]
(V
DD
=2.7V, T = 10
C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
810
810
720
720
mA
IDD1
1,035
1,035
950
950
mA
IDD2P
27
27
27
27
mA
IDD2F
270
225
225
225
mA
IDD2Q
225
210
210
210
mA
IDD3P
320
270
270
270
mA
IDD3N
500
410
410
410
mA
IDD4R
1,440
1260
1260
1,260
mA
IDD4W
1,440
1,220
1,220
1,220
mA
IDD5
1,530
1,440
1,440
1,440
mA
IDD6
Normal
27
27
27
27
mA
Low power
14
14
14
14
mA
Optional
IDD7A
2,520
2,520
2,340
2,340
mA
M381L3223FTM [ (32M x 8) * 9, 256MB ECC Module ]
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
(V
DD
=2.7V, T = 10
C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
1,160
1,080
1,000
1,000
mA
IDD1
1,360
1,280
1,200
1,200
mA
IDD2P
48
48
48
48
mA
IDD2F
480
400
400
400
mA
IDD2Q
320
290
290
290
mA
IDD3P
560
480
480
480
mA
IDD3N
880
720
720
720
mA
IDD4R
1,720
1,480
1,480
1,480
mA
IDD4W
1,720
1,440
1,440
1,440
mA
IDD5
1,800
1,640
1,640
1,640
mA
IDD6
Normal
48
48
48
48
mA
Low power
24
24
24
24
mA
Optional
IDD7A
2,680
2,600
2,440
2,440
mA
DDR SDRAM IDD spec table
M368L6423FTN [ (32M x 8) * 16, 512MB Non ECC Module ]
(V
DD
=2.7V, T = 10
C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2 (DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
1,310
1,220
1,130
1,130
mA
IDD1
1,530
1,440
1,350
1,350
mA
IDD2P
54
54
54
54
mA
IDD2F
540
450
450
450
mA
IDD2Q
450
420
420
420
mA
IDD3P
630
540
540
540
mA
IDD3N
990
810
810
810
mA
IDD4R
1,940
1,670
1,670
1,670
mA
IDD4W
1,940
1,620
1,620
1,620
mA
IDD5
2,030
1,850
1,850
1,850
mA
IDD6
Normal
54
54
54
54
mA
Low power
27
27
27
27
mA
Optional
IDD7A
3,020
2,930
2,750
2,750
mA
M381L6423FTM [ (32M x 8) * 18, 512MB ECC Module ]
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25
C, f=1MHz)
Parameter
Symbol
M368L1624FTM M368L3223FTN M381L3223FTM
Unit
Min
Max
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
41
45
49
57
51
60
pF
Input capacitance(CKE0)
CIN2
34
38
42
50
44
53
pF
Input capacitance( CS0)
CIN3
34
38
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
25
30
pF
Input capacitance(DM0~DM7, DM8 (for ECC))
CIN5
6
7
6
7
6
7
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6
7
6
7
6
7
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
-
-
6
7
pF
Parameter
Symbol
M368L6423FTN
M381L6423FTM
Unit
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
65
81
69
87
pF
Input capacitance(CKE0,CKE1)
CIN2
42
50
44
53
pF
Input capacitance( CS0, CS1)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
28
34
28
34
pF
Input capacitance(DM0~DM7, DM8 (for ECC))
CIN5
10
12
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
12
10
12
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
10
12
pF
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
AC Timming Parameters & Specifications
Parameter
Symbol
B3
(DDR333@CL=2.5)
AA
(DDR266@CL=2.0
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5) Unit Note
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
60
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
75
ns
Row active time
tRAS
42
70K
45
120K
45
120K
45
120K
ns
RAS to CAS delay
tRCD
18
15
20
20
ns
Row precharge time
tRP
18
15
20
20
ns
Row active to Row active delay
tRRD
12
15
15
15
ns
Write recovery time
tWR
15
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
1
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.5
ns
12
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
0
ns
3
DQS-in hold time
tWPRE
0.25
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
1.0
ns
i, 6~9
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
1.0
ns
i, 6~9
Data-out high impedence time from CK/CK
tHZ
+0.7
+0.75
+0.75
+0.75
ns
1
Data-out low impedence time from CK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75
ns
1
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Parameter
Symbol
B3
(DDR333@CL=2.5))
AA
(DDR266@CL=2.0)
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5))
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
tMRD
12
15
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
0.5
ns
j, k
Control & Address input pulse width
tIPW
2.2
2.2
2.2
2.2
ns
8
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
1.75
ns
8
Power down exit time
tPDEX
6
7.5
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
75
ns
Exit self refresh to read command
tXSRD
200
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
7.8
us
4
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
11
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
10, 11
Data hold skew factor
tQHS
0.55
0.75
0.75
0.75
ns
11
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
Active to Read with Auto precharge
command
tRAP
18 20
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333& DDR266 devices to ensure proper system
performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
AC CHARACTERISTICS
DDR333
DDR266
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
TBD
TBD
TBD
V/ns
a, m
Input Slew Rate
tIS
tIH
Units
Notes
0.5 V/ns
0
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Input Slew Rate
tDS
tDH
Units
Notes
0.5 V/ns
0
0
ps
k
0.4 V/ns
+75
+75
ps
k
0.3 V/ns
+150
+150
ps
k
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Table 7 : Output Slew Rate Matching Ratio Characteristics
Delta Slew Rate
tDS
tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
j
+/- 0.25 V/ns
+50
+50
ps
j
+/- 0.5 V/ns
+100
+100
ps
j
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g,h
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g,h
AC CHARACTERISTICS
DDR333
DDR266
PARAMETER
MIN
MAX
MIN
MAX
Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown)
TBD
TBD
TBD
TBD
e,m
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Component Notes
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address input slew rate
1.0 V/ns
6. For command/address input slew rate
0.5 V/ns and
<
1.0 V/ns
7. For CK & CK slew rate
1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
12. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Output
Test point
VSSQ
50
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
Output
Test point
VDDQ
50
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25
C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70
C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0
C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Command Truth Table
(V=Valid, X=Don
t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE BA0,1 A10/AP
A0 ~ A9
A11, A12
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
Refresh
Auto Refresh
H
H
L
L
L
H
X
3
Self
Refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
3
H
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
V
Row Address
Read &
Column Address
Auto Precharge Disable
H
X
L
H
L
H
V
L
Column
Address
4
Auto Precharge Enable
H
4
Write &
Column Address
Auto Precharge Disable
H
X
L
H
L
L
V
L
Column
Address
4
Auto Precharge Enable
H
4, 6
Burst Stop
H
X
L
H
H
L
X
7
Precharge
Bank Selection
H
X
L
L
H
L
V
L
X
All Banks
X
H
5
Active Power Down
Entry
H
L
H
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
Precharge Power Down Mode
Entry
H
L
H
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
L
V
V
V
DM
H
X
X
8
No operation (NOP) : Not defined
H
X
H
X
X
X
X
9
L
H
H
H
9
Note : 1. OP Code : Operand Code. A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
5. If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Physical Dimensions : 16Mx64 (M368L1624FTM)
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 16Mx16 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H561638F-T***
5.25
0.005
5.077
Units : Inches (Millimeters)
0.050
0.0078
0.006
(0.20
0.15)
0.100
M
i
n
(
2
.30 Min
)
0.
39
3
(1
0.00)
(1.270)
0.
10
0
(2.50
)
Detail B
A
B
(128.950)
(133.350
0.13
)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(
1
7.
80
)
2.55
1.95
0.26
2.500
0.
7
0.10 M
C B A
0.10 M C A
0.1496
(3.00)
0.118
R (2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4.00
)
(2X) 0.157
0.098 Max
0.050
0.0039
(1.270
0.10)
(2.47 Max)
M B
(3.00)
0.118
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H560838F-T***
5.25
0.006
5.077
Units : Inches (Millimeters)
0.050
0.0078
0.006
(0.20
0.15)
0
.
1
00 Min
(2.30
Mi
n)
0.393
(10.00
)
(1.270)
0.100
(2
.
5
0 )
Detail B
A
B
(128.950)
(133.350
0.15)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(1
7.80)
2.55
1.95
0.26
2.500
0.7
0.10 M
C B A
0.1496
(3.00)
0.118
R (2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4
.
0
0)
(2X) 0.15
7
0.10 M C A M B
(3.00)
0.118
Physical Dimensions : 32Mx64 (M368L3223FTN)
0.07 Max
0.050
0.0039
(1.270
0.10)
(1.20 Max)
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H560838F-T***
5.25
0.006
5.077
Units : Inches (Millimeters)
0.050
0.0078
0.006
(0.20
0.15)
0
.
1
00 Min
(2.30
Mi
n)
0.393
(10.00
)
(1.270)
0.100
(2
.
5
0 )
Detail B
A
B
(128.950)
(133.350
0.15)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(1
7.80)
2.55
1.95
0.26
2.500
0.7
0.10 M
C B A
0.1496
(3.00)
0.118
R (2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4
.
0
0)
(2X) 0.15
7
0.10 M C A M B
(3.00)
0.118
Physical Dimensions : 32Mx72 (M381L3223FTM)
0.07 Max
0.050
0.0039
(1.270
0.10)
(1.20 Max)
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H560838F-T***
5.25
0.006
5.077
Units : Inches (Millimeters)
0.050
0.0078
0.006
(0.20
0.15)
0.145 Max
0.050
0.0039
(1.270
0.10)
0
.
1
00 Min
(2.30
Mi
n)
0.393
(10.00
)
(1.270)
0.100
(2
.
5
0 )
Detail B
A
B
(128.950)
(133.350
0.15)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
(3.67 Max)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(1
7.80)
2.55
1.95
0.26
2.500
0.7
0.10 M
C B A
0.1496
(3.00)
0.118
R (2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4
.
0
0)
(2X) 0.15
7
0.10 M C A M B
(3.00)
0.118
Physical Dimensions : 64Mx64 (M368L6423FTN)
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 May, 2004
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H560838F-T***
5.25
0.006
5.077
Units : Inches (Millimeters)
0.050
0.0078
0.006
(0.20
0.15)
0.145 Max
0.050
0.0039
(1.270
0.10)
0
.
1
00 Min
(2.30
Mi
n)
0.393
(10.00
)
(1.270)
0.100
(2
.
5
0 )
Detail B
A
B
(128.950)
(133.350
0.15)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
(3.67 Max)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(1
7.80)
2.55
1.95
0.26
2.500
0.7
0.10 M
C B A
0.1496
(3.00)
0.118
R (2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4
.
0
0)
(2X) 0.15
7
0.10 M C A M B
(3.00)
0.118
Physical Dimensions : 64Mx72 (M381L6423ETM)
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