LA6542M
No. 5717-1/7
LA6542M
4-Channel Bridge (BTL) Driver for CD-ROM
Monolithic Linear IC
The LA6542M is a 4-channel bridge (BTL) driver
developed for CD-ROM applications.
Package Dimensions
unit: mm
3204-MFP36SLF
Maximum Ratings
at Ta = 25
C
Operating Conditions
at Ta = 25
C
Specifications
Overview
SANYO : MFP36SLF
[LA6542]
Functions
4-channel power amplifier with bridge circuit (BTL)
I
O
max: 1A
Integrated muting circuit
(MUTE: Output OFF at Low, output ON at High.
MUTE1 is for channels 1 and 2, and MUTE2 for
channels 3 and 4.)
Slew rate 0.5 V/
s
Integrated thermal shutdown circuit
*V
CC
V
S
1, 2
N1798RM(KI)
Ordering number : EN5717
Parameter
Symbol
Conditions
Ratings
Unit
Recommended operation voltage 1
4 to 13
V
Recommended operation voltage 2-1
4 to 13
V
Recommended operation voltage 2-2
4 to 13
V
V
CC
V
S
1
V
S
2
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage 1
14
V
Maximum supply voltage 2
14
V
Maximum input voltage
Input pins
13
V
Mute pin voltage
13
V
Allowable power dissipation
Pd max
IC only
0.9
W
Operating temperature
Topr
C
Storage temperature
Tstg
C
20 to +75
55 to +150
V
CC
max
V
S
max
V
IN
max
V
S
1, 2
V
IN
1 to 4
V
MUTE
max
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
0.15
15.3
1
18
36
19
0.85
0.35
0.8
2.5max
2.15
0.1
7.9
9.2
10.5
0.65
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
LA6542M
No. 5717-2/7
Electrical Characteristics
at V
CC
= 12V, V
S
= 5V, Ta = 25
C
Note 1: Guaranteed design value
Note 2: MUTE works on all channels. At High, amplifier output is ON and at Low amplifier output is OFF (output impedance
becomes HI).
min
typ
max
All outputs ON (MUTE1, MUTE2: High)
5
10
20
mA
All outputs OFF (MUTE1, MUTE2: Low)
5
10
mA
CH1, 2 ON (MUTE1, MUTE2: High)
10
30
mA
CH1, 2 OFF (MUTE1, MUTE2: Low)
4
mA
CH3, 4 ON (MUTE1, MUTE2: High)
10
30
mA
CH3, 4 OFF (MUTE1, MUTE2: Low)
4
mA
Output offset voltage
Potential difference between plus and minus outputs
for CH1 to CH4
50
50 mV
Input voltage range
Input voltage range for
0.5
5
V
Output voltage (source)
Vsource
Plus and minus outputs at high level
4.4
4.7
V
(sink)
Vsink
Plus and minus outputs at low level
0.3
0.6
V
Closed circuit voltage gain
VG
Voltage gain between BTL amplifiers
6
dB
Slew rate
SR
(Note 1)
0.5
V/
s
Mute ON voltage
MUTE1, MUTE2 voltage when output is ON (Note 2)
1.5 2
V
Mute ON current
MUTE1, MUTE2 current when output is ON (Note 2)
6
10
A
Ratings
Parameter
Symbol
Conditions
Unit
V
CC
no-load current drain
V
S
1 no-load current drain
V
S
2 no-load current drain
I
CC
2
I
S
1-1
I
S
1-2
I
S
2-1
I
CC
1
I
S
2-2
V
MUTE
I
MUTE
V
OF
1 to 4
V
IN
V
IN
1 to V
IN
4
I
O
= 700 mA
I
O
= 700 mA
20
0
20
40
60
80
100
0
0.2
0.4
0.6
1.0
0.8
0.9
1.2
Ambient temperature, Ta C
Allowable power dissipation, Pd max W
Pd max Ta
IC only
0.54
LA6542M
No. 5717-3/7
Pin Assignment
A11265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RF
RF
VOUT
VIN
VIN
+
MUTE1
VIN1
VG1
VIN2
VG2
VIN3
VG3
VIN4
VG4
MUTE2
VCC
RF
LA6542M
RF
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RF
RF
VSS
VSS OUT
VO1
VO2
VS1
VO3
VO4
VO5
VO6
VS2
VO7
VO8
VREF OUT
VREF IN
RF
RF
Top view
LA6542M
No. 5717-4/7
Pin number
Pin name
Equivalent circuit
Pin function
1, 2
17, 18
Substrate
19, 20
(minimum potential)
35, 36
7, 9
Input pins for CH1 and CH2
11, 13
Input pins for CH3 and CH4
8, 10
VG1, VG2
Input pins for CH1 and CH2 (for gain adjustment)
12, 14
VG3, VG4
Input pins for CH3 and CH4 (for gain adjustment)
16
Power supply
22
Level shift circuit reference voltage
3
OP amp output
4
OP amp inverted input
5
OP amp non-inverted input
6
MUTE1
CH1, CH2 output ON/OFF
15
MUTE2
CH3, CH4 output ON/OFF
21
Level shift circuit reference voltage input
23
CH4 inverted output (AMP8 output)
24
CH4 non-inverted output (AMP7 output)
26
CH3 inverted output (AMP6 output)
27
CH3 non-inverted output (AMP5 output)
28
CH2 inverted output (AMP4 output)
29
CH2 non-inverted output (AMP3 output)
31
CH1 inverted output (AMP2 output)
32
CH1 non-inverted output (AMP1 output)
25
CH3 (AMP5, AMP6), CH4 (AMP7, AMP8)
output stage power supply
30
CH1 (AMP1, AMP2), CH2 (AMP3, AMP4)
output stage power supply
33
Output stage reference voltage
34
Connect to VS1, VS2 (resistance split) to
generate
R F
Pin Function
*See block diagram on next page.
V
IN
1, V
IN
2
V
CC
V
O
2
V
O
3
V
O
1
V
O
4
V
O
6
V
O
7
V
O
5
V
O
8
V
REF
OUT
V
OUT
V
S
1
V
SS
-OUT
V
IN
+
V
S
2
V
IN
-
(V
REF
1 buffer amplifier output*)
(V
SS
1/2: typ)
(V
REF
2 buffer amplifier output*)
(V
REF
buffer amplifier input*)
V
IN
3, V
IN
4
V
REF
IN
V
SS
V
SS
OUT
A
GND
VREF OUT
A11136
VIN
7
11
13
9
VG
8
1
2
20
17
35
18
36
19
12
14
22
10
VCC
16
Drive
A11138
MUTE1, 2
To bias circuit
GND
VCC
16
6
15
1
19 20 35 36
2 17 18
GND
VO
A11137
Drive
VCC
16
1
23
26
31
27
28
32
24
29
19 20 35 36
2 17 18
LA6542M
No. 5717-5/7
Block Diagram
System Diagram (relationship between power supply and MUTE)
A11140
CH1
MUTE1
VS1
CH2
CH3
MUTE2
VS2
CH4
A11139
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RF
RF
VOUT
VIN
VIN
+
MUTE1
VO1 to VO4
VIN1
VG1
VIN2
VG2
VIN3
VG3
VIN4
VG4
MUTE2
VCC
RF
RF
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RF
RF
VSS
VSS OUT
VO1
VO2
VS1
VO3
VO4
VO5
VO6
VS2
VO7
VO8
VREF OUT
VREF IN
RF
RF
+
+
+
+
+
+
+
+
+
+
+
VO5 to VO8
VREF1
VREF2
Level shift
Level shift
Level shift
Level shift
Thermal shutdown
MUTE1
MUTE2
LA6542M
No. 5717-6/7
Sample Application Circuit
A11141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RF
RF
VOUT
VIN
VIN
+
MUTE1
Microprocessor
VIN1
VG1
VIN2
VG2
VIN3
VG3
VIN4
VG4
MUTE2
VCC
RF
RF
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RF
RF
VSS
VSS OUT
VO1
VO2
VS1
VO3
VO4
VO5
M
VO6
VS2
VO7
VO8
VREF OUT
VREF IN
RF
RF
Focus input
Tracking input
Focus
Tracking
Sled
Spindle
Reference voltage
Sled input
Spindle input
Microprocessor
12V power supply
5V power supply
M
LA6542M
LA6542M
No. 5717-7/7
A simplified diagram of V
IN
and VG is shown below.
1) Consider an 11 k
(typ.) resistor inserted between V
IN
and VG.
2) When not the pin VG but the pin V
IN
is used alone, the BTL gain (between V
O
+
and V
O
) is set to 6 dB (0 dB for AMP only). This
also applies for the case when V
IN
is not used and an 11 k
external resistor is connected to VG for input.
3) Gain is set by the input impedance as seen from point A.
When VG only is used and the external resistor is R, the BTL gain (between V
O
+
and V
O
) is
20 log (11 k
/R) + 6 dB.
When an 11 k
resistor is inserted between V
IN
and VG, and input is via V
IN
, the combined resistance Rz as seen from point A is
Rz = 5.5 k
. Gain is
20 log (11 k
/5.5 k
) + 6 dB = 12 dB.
This catalog provides information as of December, 1998. Specifications and information herein are subject to change
without notice.
Gain Setting (input pins and adjustment pins)
This IC incorporates a level shifter circuit. The input references the V
REF
to be applied, and references the voltage (V
SS
V
BE
(0.7))/2V to be output.
Offset Voltage
PS
+
+
AMP1
AMP2
+
VREF2
+
VREF1
VSS
VREF
VIN
VG
A
11 k
11 k
11 k
GND
VO
VO
+
A11142
Level
shift
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
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