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Электронный компонент: LA8522M

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Ordering number : ENN6951
O1802RM (OT) No. 6951-1/17
Overview
The LA8522M is an I/O switching audio signal-processing
IC for use in facsimile units and telephones. It integrates a
crosspoint switch, a BTL power amplifier, an electronic
volume control, a microphone amplifier, and other
functions on a single chip.
Applications
Personal facsimile units and telephones
Functions
Crosspoint switch (equivalent to an 4
4 switch)
BTL power amplifier
Electronic volume control
Output level switching (ATT1: 0, 4, 8, 12 dB,
ATT2: 0, 6 dB)
Serial interface
Features
Built-in BTL power amplifier (8 to 32
load): V
CC
=
5 V, R
L
= 16
, Pomax = 250 mW
Built-in electronic volume (seven 4.0 dB steps)
Two output level switching circuits (4 positions and 2
positions)
Crosspoint switch that supports mixing
Package Dimensions
unit: mm
3112A-MFP24S
1
12
24
13
12.5
(0.75)
1.0
0.15
0.35
5.4
7.6
0.63
1.7max
1.5
0.1
SANYO: MFP24S
[LA8522M]
LA8522M
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Audio Signal-Processing IC with I/O Switching
Monolithic Linear IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
CC
max
7
V
Allowable power dissipation
Pd max
Ta
70C
550
mW
(Mounted on a glass-epoxy board: 114.3
76.1
1.6 mm
3
)
Operating temperature
Topr
20 to +70
C
Storage temperature
Tstg
40 to +150
C
Specifications
Maximum Ratings
at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Recommended supply voltage
V
CC
5
V
Allowable operating supply voltage range
V
CCop
4.5 to 6.0
V
Operating Conditions
at Ta = 25C
No. 6951-2/17
LA8522M
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Crosspoint switch]
Voltage gain
Gsw
Vin = 14 dBV
2.5
0.5
1.5
dB
Maximum input level
Vimax
THD = 1.5 %
14
10
dBV
Output noise voltage
Nosw
20 to 20 kHz
15
60
Vrms
[AMP1]
Voltage gain
G1
Vin = 43 dBV
28.2
29.2
30.2
dB
Output total harmonic distortion
THD1
Vin = 43 dBV
0.15
1.5
%
Equivalent input noise voltage
Niamp1
Rg = 620
, 20 to 20 kHz
2.0
7.0
Vrms
[AMP2]
Voltage gain
G2
Vin = 34 dBV
18.2
19.2
20.2
dB
Output total harmonic distortion
THD2
Vin = 34 dBV
0.16
1.5
%
[AMP3]
Output level
V
O
3
Vin = 14 dBV, IN (7), OUT (22),
10.8
8.3
5.8
dBV
sw (101101) on
Output total harmonic distortion
THD3
Vin = 14 dBV, IN (7), OUT (22),
0.31
1.5
%
sw (101101) on
[AMP4]
Output level
V
O
4
Vin = 14 dBV, IN (8), OUT (21),
10.7
8.2
5.7
dBV
sw (110111) on
Output total harmonic distortion
THD4
Vin = 14 dBV, IN (8), OUT (21),
0.30
1.5
%
sw (110111) on
[AMP5]
Output level
V
O
5
Vin = 26 dBV, IN (7), OUT (23),
11.5
9.0
6.5
dBV
sw (010001) on
Output total harmonic distortion
THD5
Vin = 26 dBV, IN (7), OUT (23),
0.17
1.5
%
sw (010001) on
Maximum voltage gain
AMP1
G1max
30
dB
AMP2
G2max
25
dB
AMP3
G3max
20
dB
AMP4
G4max
18
20
dB
AMP5
G5max
18
20
dB
Attenuator attenuation 1-1
Att1-1
Address (010101)
3.5
4.2
4.9
dB
Attenuator attenuation 1-2
Att1-2
Address (011001)
7.5
8.2
8.9
dB
Attenuator attenuation 1-3
Att1-3
Address (011101)
11.7
12.4
13.1
dB
Attenuator attenuation 2-1
Att2-1
Address (000101)
5.5
6.2
6.9
dB
Electronic volume control output level
V
O
evr
Vin = 42 dBV, IN (2), OUT (20),
14.3
12.2
10.3
dBV
sw (010001) on
Electronic volume control step size
Wevr
Vin = 42 dBV, IN (2), OUT (20),
3.1
4.0
4.9
dB
sw (010010) on
Electronic volume control output noise voltage
N
O
evr
20 to 20 kHz, OUT (20)
25
60
Vrms
[BTL Power Amplifier]
Voltage gain
VG
SPW
Vin = 20 dBV, R
L
= 16
18.1
19.6
21.1
dB
Maximum voltage gain
VGp max
30
dB
Total harmonic distortion
THDpw
Vin = 30 dBV, R
L
= 16
0.8
1.5
%
Maximum BTL output power
Po max
THD = 10 %, R
L
= 16
250
400
mW
Ripple rejection ratio
SVRR
Rg = 620
, frin = 100 Hz, Vrin = 20 dBV,
40
50
dB
R
L
= 16
Output noise voltage
VNOpw
Rg = 620
, 20 to 20 kHz, R
L
= 16
23
60
Vrms
[CPU Interface]
Clock frequency
Fck
500
kHz
Input signal high level
V
H
2.1
V
Input signal low level
V
L
1.0
V
[V
REF
and Current Drain]
Internal reference voltage (the pin 10 voltage)
Vref
2.09
2.26
2.41
V
Quiescent current 1
Icco1
With the BTL power amplifier on and
12.5
20
mA
the crosspoint switch off
Quiescent current 2
Icco2
With the BTL power amplifier off and
7
11
mA
the crosspoint switch off
Electrical Characteristics
at Ta = 25C, V
CC
= 5 V, fin = 1 kHz, R
L
= 10 k
No. 6951-3/17
LA8522M
24
AMP5
REG
VREF
OP1-IN
OP2-IN
AMP2
AMP3
OP3-IN
AMP1
+
23
22
21
20
19
18
17
16
15
SP
14
13
1
2
3
4
5
6
7
8
9
10
1
1
12
A
TT2
2
6dB
EVR
7
6dB
A
TT1
4
+
AMP4
BTL-VREF
SW-OUT1
SW-OUT2
SW-OUT3
SW-OUT4
BTL-IN
BTL.GND
BTL-OUT1
BTL-OUT2
BTL.VCC
VCC
V
CC
OP4-IN
GND
CE
CPU
CPU
Interface
DI
CL
BTL
AMP
+
A13727
+
+
+
+
+
+
Block Diagram
No. 6951-4/17
LA8522M
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
V
OUT
10k
15k
100k
100k
SW1
V
IN
1kHz
SW2
IN2
IN1
IN3
IN4
100k
620
3.3k
0.1
F
0.22
F
OUT1
OUT2
OUT3
OUT4
10
F
VREF
OP1-IN
OP1-NF
OP1-OUT
OP2-IN
OP3-IN
OP4-IN
GND
CE
DI
CL
OP2-OUT
OP5-NT
SW-OUT1
SW-OUT2
SW-OUT3
SW-OUT4
BTL-IN
BTL-GND
BTL-OUT1
BTL-OUT2
BTL-VCC
VCC
V
CC
T
op view
Data generator
LA8522M
BTL-VREF
0.033
F
1
F
+
620
100k
100k
16
BTL-IN
BTL-OUT
1
10k
0.1
F
0.1
F
SW3
620
43k
10k
BTL-OUT
2
0.1
F
SW4
620
43k
0.33
F
0.1
F
0.1
F
47
F
+
620
0.1
F
0.1
F
100
F
+
100
F
+
A13728
Test Circuit Diagram
No. 6951-5/17
LA8522M
24
+
23
22
21
20
19
18
17
16
15
SP
8 to 32
14
13
1
2
3
4
5
6
7
8
9
10
1
1
12
+
V
CC
=5V
CPU
+
A13729
VREF
OP1-IN
OP1-NF
OP1-OUT
OP2-IN
OP3-IN
OP4-IN
GND
CE
DI
CL
OP2-OUT
AMP5-NF
SW-OUT1
SW-OUT2
SW-OUT3
SW-OUT4
BTL-IN
BTL-GND
BTL-OUT1
BTL-OUT2
BTL-VCC
VCC
BTL-VREF
15k
100k
0.22
F
100
F
0.33
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
1
F
0.033
F
0.1
F
0.1
F
0.1
F
220
F
100k
10k
2.2k
2.2k
2.2k
10k
10k
100k
100k
100k
10k
3.3k
10k
T
op view
LA8522M
Application Circuit Diagram
No. 6951-6/17
LA8522M
Pin Functions
Pin No.
Pin
Pin
Notes
Equivalent circuit
voltage (V)
Internal circuit reference voltage (about 2.25 V)
Circuits other than the BTL amplifier operate
using this potential as a reference.
1
VREF
2.25
1
VCC
2.25V
A13743
Amplifier 1 noninverting input
Amplifier 1 inverting input
Amplifier 1 output
2
3
4
OP1-IN
OP1-NF
OP1-OUT
2.25
2.25
2.25
300
300
4
2
3
VCC
A13744
Amplifier 2 inverting input
Amplifier 2 output
5
6
OP2-IN
OP2-OUT
2.25
2.25
30k
300
VREF
6
5
VCC
A13745
Amplifier 3 input
Amplifier 4 input
7
8
OP3-IN
OP4-IN
2.25
2.25
30k
5k
50k
VREF
7
8
VCC
A13746
Continued on next page.
No. 6951-7/17
LA8522M
Continued from preceding page.
Pin No.
Pin
Pin
Notes
Equivalent circuit
voltage (V)
Electronic volume control output
(Fourth SW output)
20
SW-OUT4
2.25
20
40k
VCC
A13750
16
18
300
5k
To 19 pin
P-VCC
A13748
BTL power amplifier output 1
BTL power amplifier inverting input
16
18
BTL-OUT1
BTL-IN
0.44V
CC
0.44V
CC
15
19
To 16 pin
50k
40k
20k
20k
P-VCC
5k
A13749
BTL power amplifier output 2
BTL power amplifier reference voltage
15
19
BTL-OUT2
BTL-VREF
0.44V
CC
0.44V
CC
Continued on next page.
Chip enable input
Data input
Clock input
10
11
12
CE
DI
CL
V
CC
V
CC
V
CC
11
10
12
100k
1k
VCC
A13747
No. 6951-8/17
LA8522M
Continued from preceding page.
Pin No.
Pin
Pin
Notes
Equivalent circuit
voltage (V)
Amplifier 7 output
(Third SW output)
21
SW-OUT3
2.25
21
60k
VREF
10k
30k
VCC
A13751
Amplifier 6 output
(Second SW output)
22
SW-OUT2
2.25
A13752
22
VCC
Amplifier 5 output
(First SW output)
Amplifier 5 noise filter connection
23
24
SW-OUT1
OP5-NF
2.25
2.25
A13753
23
24
VCC
300
Ground
Power supply
Power amplifier power supply
Power amplifier ground
9
13
14
17
GND
V
CC
BTL-V
CC
BTL-GND
--
5 V applied
5 V applied
--
Serial Data Format (6-bit structure)*
1
A6:0
Crosspoint switch (and other device) address setting (binary)
D
Controls the crosspoint switch and power amplifier on/off state.
Electronic volume control and attenuator selection
D = 1: Crosspoint switch: on
D = 0: Crosspoint switch: off
*1. When 8-bit serial data input mode is used.
Since the serial data has a 6-bit structure, the first and second bits are unused when 8-bit input mode is
used.
*
2. When the reset value is issued, the D data value can be either 0 or 1.
Notes 1. A reset command must be issued 200 ms after power is applied.
2. The electronic volume control is set to 0 dB by a reset (address: 00000*).
3. Attenuator 1 is set to 0 dB by a reset (address: 00000*).
4. Attenuator 2 is set to 0 dB by a reset (address: 00000*).
No. 6951-9/17
LA8522M
A4
CE
DATA
A13754
FIRST BIT
CLOCK
A3
A2
A1
A0
D
Address table (Crosspoint switch)
Input - Output
OUT1
OUT2
OUT3
OUT4
AMP1
10000
10100
11000
11100
AMP2
10001
10101
11001
11101
AMP3
10010
10110
11010
11110
AMP4
10011
10111
11011
11111
Address No.
A4:0
D
Mode
00000
*
Reset, control switch default
*
2
00011
0
BTL power amplifier: off
Default setting
00011
1
BTL power amplifier: on
01000
0
Electronic volume control
0 dB
Default setting
01001
0
Electronic volume control
4 dB
01010
0
Electronic volume control
8 dB
01011
0
Electronic volume control
12 dB
01100
0
Electronic volume control
16 dB
01101
0
Electronic volume control
20 dB
01110
0
Electronic volume control
24 dB
01111
0
Electronic volume control
28 dB
01000
1
Attenuator 1-0
0 dB
Default setting
01010
1
Attenuator 1-1
4 dB
01100
1
Attenuator 1-2
8 dB
01110
1
Attenuator 1-3
12 dB
00010
0
Attenuator 2-0
0 dB
Default setting
00010
1
Attenuator 2-1
6 dB
[Data A4:0]
Other addresses [Data A4:0, D]
Serial Data Timing
fmax (Maximum clock frequency)
500 kHz
t
WL
(Low-level clock pulse width)
At least 1 s
t
WH
(High-level clock pulse width) At least 1 s
t
CS
(Chip enable setup time)
At least 1 s
t
CH
(Chip enable hold time)
At least 1 s
t
DS
(Data setup time)
At least 1 s
t
DH
(Data hold time)
At least 1 s
t
WC
(Chip enable pulse time)
At least 1 s
Usage Notes
Attenuator 1
Normally, attenuator 1 is set to 0 dB. It can be set to attenuate by -4, -8, or -12 dB by issuing serial data with a value of
010101, 011001, or 011101, respectively.
No. 6951-10/17
LA8522M
A4
A4
DATA
A13755
CLOCK
CE
A3
A3
A2
A1
A0
D
tCS
tCH tWC
tWH tWH
tDS tDH
fmax
A13756
23
ATT1
Crosspoint switch
ATT1-OUT
Attenuator 2
Normally, attenuator 2 is set to 0 dB. It can be set to attenuate by -6 dB by issuing serial data with a value of 000101.
A13757
Crosspoint switch
22
ATT2
ATT2-OUT
Power amplifier phase compensation capacitors (Values shown are examples for reference purposes.)
19
PWR-VREF
PWR-IN
PWR-GND
PWR-OUT1
PWR-OUT2
PWR-VCC
C1
C2
C3
C7
C4
C5
SP
A13758
C6
10k
100k
0.33
18
+
14
+
17
16
15
C1: 100 F
C2: 0.1 F
C3: 0.1 F
C4: 0.1 F
C5: 0.1 F
C6: 100 F
C7: 100 pF (The time constant will be under 10 s.)
SP8: 8 to 32
Voltage gain: 20 to 30 dB
Of the external components, the capacitors C2 and C3 are the power amplifier phase compensation capacitors. If these
capacitors are located away from the IC pin due to layout considerations, the impedance relationship will result in a
reduction in the phase compensation effect, and high band oscillator may occur.
Therefore, we recommend that the two capacitors C2 and C3 discussed above be located as close as possible to the IC
pins in the layout. However, if you find that, due to layout relationships, the circuit tends to oscillate, we recommend
that, rather than compensation using only capacitors, you use a phase compensation design with resistors (about 1 to
2.2
) inserted in series with the capacitors.
If the capacitor C7 is added to the feedback resistor path, the phase of the feedback path will be delayed and capacitors
C4 and C5 will be required. Here, the time constant of the feedback resistor and C7 must be 10 s or less (100 k
,
100 pF).
LA8522M ground line layout (See the figure on the following page.)
The LA8522M circuit blocks can be roughly classified as follows.
(1) Power amplifier system, (2) Crosspoint switch small-signal system
Since this block structure involves two significantly different circuit types, each block has independent VCC and
ground pins. It is best if external devices are connected to the ground line for the corresponding block, and that finally
the two block ground lines are connected to the power supply (regulator) ground, which is the final reference. In
particular, the PCB pattern should be formed with two ground lines.
There are cases, however, where a single line is used for the power supply ground due to limitations on protruding PCB
areas. In such cases, the ground line layout must be designed so that the sections of the ground line that carry large
currents (the power amplifier block) are closer to the power supply ground (and thus have a lower impedance) than the
sections of the ground line for circuits that draw smaller currents.
If the large currents drawn by the power amplifier pass through ground line that handles the lower currents from the
small-signal processing blocks, the signal path may be influenced by the ground, loops may be created, and low-band
oscillation may occur.
Therefore we recommend that the ground lines be designed as described above so that lines that carry larger amounts of
current are connected the closest to the power supply ground that serves as the reference.
Inter-pin shorting
This IC may be damaged or destroyed if power is applied with any pins shorted together. Therefore, when mounting
this IC to a printed circuit board always check for pin shorting caused by stray solder or any other foreign material
before applying power.
Load shorting
This IC may be damaged or destroyed if it is operated for extended periods with the load shorted. Do not allow the load
to be shorted.
Maximum ratings
The slightest fluctuations in operating conditions may cause the ratings to be exceeded if this IC is operated in the
vicinity of the maximum ratings. Since this can lead to destruction of the device, applications must be designed with
adequate margins with respect to the power-supply voltage and other parameters so that the maximum ratings are never
exceeded.
No. 6951-11/17
LA8522M
No. 6951-12/17
LA8522M
Continued from preceding page.
Ground Line Layout
+
+
+
CPU
A13759
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SP
T
op view
LA8522M
No. 6951-13/17
LA8522M
RL=8
fIN=1kHz
V
CC
=4.5V
V
CC
=5V
V
CC
=5.5V
VO20 -- VCC
RL=32
fIN=1kHz
VIN=100mVrms
fIN=100Hz
RL=16
19Pin:100
F
VIN=42V
Input to pin 2
(Amplifier 1 input)
Output from pin 20
fIN=1kHz
RL=10
VIN=42V
Input to pin 2
(Amplifier 1 input)
Output from pin 20
fIN=1kHz
RL=10
VCC=5V
fIN=100Hz
19Pin:100
F
V
CC
=4.5V
V
CC
=5V
V
CC
=5.5V
RL=16
fIN=1kHz
V
CC
=4.5V
V
CC
=5V
V
CC
=5.5V
15Pin:BTL-OUT1
16Pin:BTL-OUT2
16Pin:OUT1
15Pin:OUT2
16Pin:OUT1
15Pin:OUT2
Rg=620
0.1
1.0
2
3
5
7
10
2
3
5
7
2
3
5
7
100
10
2
3
7
100
5
2
3
5
7
1k
0.1
10
15
20
25
30
1.0
2
3
5
7
10
2
3
5
7
2
3
5
7
100
10
2
4
4.5
5
5.5
6
6.5
7
30
35
40
45
50
55
60
65
70
30
25
20
15
3
7
100
5
2
3
5
7
1k
0.1
1.0
2
3
5
7
10
2
3
5
7
2
3
5
7
100
10
2
3
7
100
5
2
3
5
7
1k
30
40
50
60
70
4
4.5
5
5.5
6
6.5
7
20
15
10
5
4
4.5
5
5.5
6
6.5
7
2
3
4
5
6
4
4.5
5
5.5
6
6.5
7
Output level, V
O
20 -- dBV
Step width -- dB
Output power, P
O
-- mW
Total harmonic distortion, THD -- %
Supply voltage, V
CC
-- V
Input level -- dBV
Ripple rejection ratio, SVRR -- dB
Output noise, Output N
O
--
Vrms
BTL Amplifier Output Distortion Characteristics (1)
BTL Amplifier Output Distortion Characteristics (2)
Total harmonic distortion, THD -- %
Output power, P
O
-- mW
BTL Amplifier Output Distortion Characteristics (3)
Output power, P
O
-- mW
Total harmonic distortion, THD -- %
BTL Amplifier Output Noise V
CC
Dependence
BTL Amplifier Ripple Rejection Ratio V
CC
Dependence
Supply voltage, V
CC
-- V
BTL Amplifier Ripple Rejection Ratio I/O Characteristics
Ripple rejection ratio, SVRR -- dB
Supply voltage, V
CC
-- V
Supply voltage, V
CC
-- V
Electronic Volume Control Step Width V
CC
Dependence
No. 6951-14/17
LA8522M
15
14
13
12
11
10
9
8
7
6
5
4
4.5
5
5.5
6
6.5
7
15
14
13
12
11
10
9
8
7
6
5
4
4.5
5
5.5
6
6.5
7
0
1
2
3
4
5
6
7
8
9
10
4
4.5
5
5.5
6
6.5
7
130
120
110
100
90
80
70
60
50
40
30
20
10
0
5
6
7
8
9
10
11
12
13
14
15
4
4.5
5
5.5
6
6.5
7
1
2
3
5
7
10
4
4.5
5
5.5
6
6.5
7
4
4.5
5
5.5
6
6.5
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4
4.5
5
5.5
6
6.5
7
1
2
3
5
7
10
2
3
5
7
100
VIN=26V
Input to pin 7
(Amplifier 3 input)
Output from pin 23
fIN=1kHz
RL=10
VIN=14V
Input to pin 8
(Amplifier 4 input)
Output from pin 22
fIN=1kHz
RL=10
ATT1-1
ATT1-2
ATT1-3
VIN=26V
Input to pin 7
Rg=620
Rg=620
(Amplifier 3 input)
Output from pin 23
fIN=1kHz
RL=10
ATT2-1
PWR-AMP:OFF
VOUT:4Pin (AMP1)
VOUT:6Pin (AMP2)
VOUT:23Pin
VOUT:20Pin
VOUT:22Pin
VOUT:21Pin
PWR-AMP:ON
VCC=5V
fIN=1kHz
with:1k-BPF
OP2-IN/OUT1, SW:OFF
OP3-IN/OUT2, SW:OFF
OP1-IN/OUT1, SW:OFF
OP2-IN/OUT3, SW:OFF
OP3-IN/OUT1, SW:OFF
OP1-IN/OUT4, SW:OFF
OP3-IN/OUT2, SW:111101
VO23 -- VCC
VO22 -- VCC
VNI -- VCC
VNO -- VCC
VIN=14V
Input to pin 8
(Amplifier 4 input)
Output from pin 22
fIN=1kHz
RL=10
Equivalent input noise voltage, V
NI
--
Vrms
Output noise voltage, V
NO
--
Vrms
Supply voltage, V
CC
-- V
Output level, V
O
23 -- dBV
Supply voltage, V
CC
-- V
Input level -- dBV
No signal current drain, I
CCO
-- mA
Attenuation, ATT -- dB
Attenuator 1 Attenuation V
CC
Dependence
Attenuation, ATT -- dB
Supply voltage, V
CC
-- V
Supply voltage, V
CC
-- V
Output level, V
O
22 -- dBV
Attenuator 2 Attenuation V
CC
Dependence
No Signal Current Drain V
CC
Dependence
Supply voltage, V
CC
-- V
Crosstalk I/O Characteristics
Crosstalk level, CT -- dBV
Supply voltage, V
CC
-- V
Supply voltage, V
CC
-- V
No. 6951-15/17
LA8522M
0.1
1.0
2
3
5
7
10
2
3
5
7
2
3
5
7
100
10
2
3
7
100
5
2
3
5
7
1k
10
2
3
5
7
100
20
10
0
10
20
30
40
50
60
70
20
15
10
5
20
10
0
10
20
30
40
50
60
70
15
10
5
0
20
10
0
10
20
30
40
50
60
70
15
10
5
0
20
10
0
10
20
30
40
50
60
70
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
20
10
0
10
20
30
40
50
60
70
20
10
0
10
20
30
40
50
60
70
3
3.5
4
4.5
5
20
10
0
10
20
30
40
50
60
70
VCC=5V
fIN=1kHz
RL=16
TEMP:+70
C
TEMP:20
C
TEMP:+25
C
VCC=5V
Rg=620
BTL-OUT1:16Pin
BTL-OUT2:15Pin
STEP1, STEP
STEP4, STEP
STEP2, STEP
VIN=42dBV
Input to pin 2
(Amplifier 1 input)
Output from pin 20
fIN=1kHz
RL=10k
VIN=42dBV
Input to pin 2
(Amplifier 1 input)
Output from pin 20
fIN=1kHz
RL=10k
VIN=44dBV
Input to pin 5
(Amplifier 2 input)
Output from pin 23
fIN=1kHz
RL=10k
VIN=32dBV
Input to pin 5
(Amplifier 2 input)
Output from pin 22
fIN=1kHz
RL=10k
VIN=32dBV
Input to pin 5
(Amplifier 2 input)
Output from pin 22
fIN=1kHz
RL=10k
VIN=44dBV
Input to pin 5
(Amplifier 2 input)
Output from pin 23
fIN=1kHz
RL=10k
ATT1-1
ATT1-2
ATT2-1
ATT1-3
VO20 -- Ta
VO23 -- Ta
VO22 -- Ta
Output level, V
O
22 -- dBV
Attenuation, ATT -- dB
Output power, P
O
-- mV
Total harmonic distortion, THD -- %
Ambient temperature, Ta -- C
Output level, V
O
23 -- dBV
Step width -- dB
Output noise voltage, V
NO
--
Vrms
Ambient temperature, Ta -- C
Ambient temperature, Ta -- C
Output level, V
O
20 -- dBV
Electronic Volume Control Step Width Temperature Dependence
Attenuator Attenuation Temperature Dependence
Attenuation, ATT -- dB
BTL Amplifier Output Distortion Characteristics (4)
Output Amplifier Output Noise Temperature Dependence
Ambient temperature, Ta -- C
Ambient temperature, Ta -- C
Ambient temperature, Ta -- C
Ambient temperature, Ta -- C
Attenuator Attenuation Temperature Dependence
No. 6951-16/17
LA8522M
0.01
2
3
5
7
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
55
50
45
40
35
25
20
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
25
20
15
10
5
0
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
0.1
2
3
5
7
10
2
3
5
7
100
25
20
15
10
5
0
5
20
10
0
10
20
30
40
50
60
70
0.1
2
3
5
7
10
2
3
5
7
100
2
3
5
7
1000
20
10
0
10
20
30
40
50
60
70
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
25
20
15
10
5
0
5
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
25
20
15
10
5
0
0.01
2
3
5
7
0.1
2
3
5
7
1.0
2
3
5
7
10
2
3
5
7
100
45
40
35
30
25
20
15
THD -- VO20
THD -- VO22
VNI -- Ta
VNO -- Ta
THD -- VO23
THD -- VO21
VCC=5V
fIN=1kHz
Input to pin 2
Output from pin 4
fIN=1kHz
Input to pin 5
(Amplifier 2 input)
Output from pin 20
fIN=1kHz
Input to pin 5
(Amplifier 2 input)
Output from pin 22
fIN=1kHz
Input to pin 5
(Amplifier 2 input)
Output from pin 23
fIN=1kHz
Input to pin 5
(Amplifier 2 input)
Output from pin 20
VCC=5V
fIN=1kHz
Input to pin 5
Output from pin 6
TEMP:+70
C
TEMP:+70
C
TEMP:+70
C
TEMP:+70
C
TEMP:+70
C
TEMP:+70
C
TEMP:20
C
TEMP:+25
C
TEMP:20
C
TEMP:20
C
TEMP:20
C
TEMP:+25
C
TEMP:+25
C
TEMP:+25
C
TEMP:20
C
TEMP:20
C
TEMP:+25
C
TEMP:+25
C
VCC=5V
Rg=620
VCC=5V
Rg=620
AMP1
OUT1
OUT4
OUT2
OUT3
AMP2
Equivalent input noise voltage, V
NI
--
Vrms
Output noise voltage, V
NO
--
Vrms
Input level -- dBV
Total harmonic distortion, THD -- %
Output level, V
O
21 -- dBV
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
Input level -- dBV
Output level, V
O
20 -- dBV
Total harmonic distortion, THD -- %
Total harmonic distortion, THD -- %
Amplifier 1 I/O Characteristics
Amplifier 2 I/O Characteristics
Output level, V
O
22 -- dBV
Ambient temperature, Ta -- C
Ambient temperature, Ta -- C
Output level, V
O
23 -- dBV
PS No. 6951-17/17
LA8522M
This catalog provides information as of October, 2002. Specifications and information herein are subject
to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.