Ordering number : ENN7110
D1503SI (OT) No. 7110-1/11
Overview
The LB11827 is a three-phase brushless motor driver that
is optimal for driving drum and paper feed motors in laser
printers and plain paper copiers. This IC adopts a direct
PWM drive technique for minimal power loss. Flexible
control of motor speed in response to an externally
provided clock frequency (corresponding to the FG
frequency) can be implemented by using the LB11827 in
conjunction with the Sanyo LB11825M.
Functions and Features
Three-phase bipolar drive (30 V, 3.5 A)
Direct PWM drive
Built-in low side inductive kickback absorbing diode
Speed discriminator + P
LL
speed control
Speed locked state detection output
Built-in forward/reverse switching circuit
Full complement of built-in protection circuits,
including current limiter circuit, thermal protection
circuit, and motor constraint protection circuit.
Package Dimensions
unit: mm
3147B-DIP28H
1
14
28
15
0.4
0.6
4.0
4.0
27.0
20.0
R1.7
8.4
1.93
1.78
1.0
12.7
11.2
SANYO: DIP28H (500 mil)
[LB11827]
LB11827
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Three-Phase Brushless Motor Driver for OA Products
Monolithic Digital IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
CC
max
30
V
Output current
I
O
m ax
T
500 ms
3.5
A
Allowable power dissipation 1
Pd max1
Independent IC
3
W
Allowable power dissipation 2
Pd max2
When infinitely large heat sink
20
W
Operating temperature
Topr
20 to +80
C
Storage temperature
Tstg
55 to +150
C
Specifications
Absolute Maximum Ratings at
Ta = 25C
No. 7110-2/11
LB11827
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range 1
V
CC
9.5 to 28
V
Regulator voltage output current
I
REG
0 to 30
mA
LD output current
ILD
0 to 15
mA
Absolute Maximum Ratings at
Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply current 1
I
CC
1
23
30
mA
Supply current 2
I
CC
2
When stopped
3.5
5
mA
[Output Block]
Output saturation voltage 1
V
O
sat1
I
O
= 1.0 A, V
O
(SINK)+ V
O
(SOURCE)
2.0
2.5
V
Output saturation voltage 2
V
O
sat2
I
O
= 2.0 A, V
O
(SINK)+ V
O
(SOURCE)
2.6
3.2
V
Output leakage current
V
O
leak
100
A
Lower side diode forward voltage 1
VD1
ID = 1.0 A
1.2
1.5
V
Lower side diode forward voltage 2
VD2
ID = 2.0 A
1.5
2.0
V
[5 V Regulator Voltage Output]
Output voltage
VREG
I
O
= 5 mA
4.65
5.00
5.35
V
Voltage regulation
VREG1
V
CC
= 9.5 to 28 V
30
100
mV
Load regulation
VREG2
I
O
= 5 to 20 mA
20
100
mV
[Hall Amplifier]
Input bias current
IHB
2
0.5
A
Common-mode input voltage range
VICM
1.5
VREG1.5
V
Hall input sensitivity
80
mV
P-P
Hysteresis
V
IN
15
24
42
mV
Input voltage low
high
VSLH
12
mV
Input voltage high
low
VSHL
12
mV
[PWM Oscillator Circuit]
Output H level voltage
V
OH
(PWM)
2.5
2.8
3.1
V
Output L level voltage
V
OL
(PWM)
1.2
1.5
1.8
V
Oscillator frequency
f(PWM)
C = 3900 pF
18
kHz
Amplitude
V(PWM)
1.05
1.30
1.55
V
P-P
[CSD Circuit]
Operating voltage
V
OH
(CSD)
3.6
3.9
4.2
V
External C charging current
ICHG
17
12
9
A
Operating time
T(CSD)
C = 10 F Design target value
*
3.3
s
[Current Limiter Operation]
Limiter
VRF
V
CC
VM
0.45
0.5
0.55
V
[Thermal Shutdown Operation]
Thermal shutdown operating temperature
TSD
Design target value
*
(junction temperature)
150
180
C
Hysteresis
TSD
Design target value
*
(junction temperature)
50
C
[FG Amplifier]
Input offset voltage
VIO(FG)
10
10
mV
Input bias current
IB(FG)
1
1
A
Output H level voltage
V
OH
(FG)
IFGO = 0.2 mA
VREG1.2
VREG0.8
V
Output L level voltage
V
OL
(FG)
IFGO = 0.2 mA
0.8
1.2
V
FG input sensitivity
Gain: 100
3
mV
Schmitt amplitude for the next stage
Design target value
*
100
180
250
mV
Operating frequency range
2
kHz
Open-loop gain
f(FG) = 2 kHz
45
51
dB
Electrical Characteristics
at Ta = 25C, V
CC
= VM = 24 V
Continued on next page.
Note:
*
These are design target values and are not tested.
No. 7110-3/11
LB11827
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Speed Discriminator]
Output H level voltage
V
OH
(D)
IDO = 0.1 mA
VREG1.0
VREG0.7
V
Output L level voltage
V
OL
(D)
IDO = 0.1 mA
0.8
1.1
V
Number of counts
512
[PLL Output]
Output H level voltage
V
OH
(P)
IPO = 0.1 mA
VREG1.8
VREG1.5
VREG1.2
V
Output L level voltage
V
OL
(P)
IPO = 0.1 mA
1.2
1.5
1.8
V
[Lock Detection]
Output L level voltage
V
OL
(LD)
ILD = 10 mA
0.15
0.5
V
Lock range
6.25
%
[Integrator]
Input bias current
IB(INT)
0.4
0.4
A
Output H level voltage
V
OH
(INT)
IINTO = 0.2 mA
VREG1.2
VREG0.8
V
Output L level voltage
V
OL
(INT)
IINTO = 0.2 mA
0.8
1.2
V
Open-loop gain
f(INT) = 1 kHz
45
51
dB
Gain width product
Design target value
*
450
kHz
Reference voltage
Design target value
*
5%
VREG/2
5%
V
[Clock Input Pin]
Operating frequency range
f
OSC
1
MHz
L level pin voltage
V
OSCL
I
OSC
= 0.5 mA
1.55
V
H level pin current
I
OSCH
V
OSC
= V
OSCL
+0.5 V
0.4
mA
[Start/Stop Pin]
H level input voltage range
V
IH
(S/S)
3.5
VREG
V
L level input voltage range
V
IL
(S/S)
0
1.5
V
Input open voltage
V
IO
(S/S)
VREG0.5
VREG
V
Hysteresis
V
IN
0.35
0.50
0.65
V
H level input current
I
IH
(S/S)
V(S/S) = VREG
10
0
10
A
L level input current
I
IL
(S/S)
V(S/S) = 0 V
280
210
A
[Forward/Reverse Pin]
H level input voltage range
V
IH
(F/R)
3.5
VREG
V
L level input voltage range
V
IL
(F/R)
0
1.5
V
Input open voltage
V
IO
(F/R)
VREG0.5
VREG
V
Hysteresis
V
IN
0.35
0.50
0.65
V
H level input current
I
IH
(F/R)
V(F/R) = VREG
10
0
10
A
L level input current
I
IL
(F/R)
V(F/R) = 0 V
280
210
A
Continued from preceding page.
Note:
*
These are design target values and are not tested.
No. 7110-4/11
LB11827
Truth Table
Source
F/R = "L"
F/R = "H"
Sink
IN1
IN2
IN3
IN1
IN2
IN3
1
OUT2
OUT1
H
L
H
L
H
L
2
OUT3
OUT1
H
L
L
L
H
H
3
OUT3
OUT2
H
H
L
L
L
H
4
OUT1
OUT2
L
H
L
H
L
H
5
OUT1
OUT3
L
H
H
H
L
L
6
OUT2
OUT3
L
L
H
H
H
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
OUT
INT
OUT
V
CC
XO
XI
CSD
PWM
VREG
VM
GND2
GND1
OUT3
OUT2
OUT1
F/R
IN3+
IN3-
IN2+
IN2-
IN1+
IN1-
S/S
P
OUT
Top view
INT
IN
FG
IN
+
FG
OUT
LD
FG
IN
-
LB11827
Pin Assignment
Infinitely large heat sink
With no heat sink
Allowable power dissipation, Pdmax--W
Ambient temperature, Ta --C
The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation.
fFG(servo) = fCLK/<number of counts>
= fCLK/512
Equivalent Circuit Block Diagram and Peripheral Circuits
No. 7110-5/11
LB11827
Pin No.
Pin
Function
Equivalent circuit
8
300
1 k
V
REG
300
5
1
3
2
28
V
CC
VM
7
200
2 k
V
REG
No. 7110-6/11
LB11827
Pin Description
Motor drive output pin
Connect the Schottky diode between the output V
CC
.
28
1
2
OUT1
OUT2
OUT3
Output GND pin
3
GND2
Power and output current detection pins of the output. Connect a
low resistance (Rf) between this pin and V
CC
.
The output current is limited to the current value set with I
OUT
=
VRF/Rf.
5
VM
Stabilized power supply output pin (5 V output)
Connect a capacitor (about 0.1 F) between this pin and GND for
stabilization
6
VREG
Power pin (Other than the output)
4
V
CC
Pin to set the PWM oscillation frequency.
Connect a capacitor between this pin and GND.
This can be set to about 18 kHz with C =3900 pF.
7
PWM
Pin to set the operation time of motor lock protection circuit.
Connection of a capacitor (about 10 F) between CSD and GND
can set the protection operation time of about 3.3seconds.
8
CSD
Continued on next page.
6
V
CC
P
OUT
13
300
V
REG
12
300
V
REG
11
V
REG
PWM Comparator
40 k
10
9
V
REG
No. 7110-7/11
LB11827
Continued from preceding page.
Pin No.
Pin
Function
Equivalent circuit
Clock input pin, which enters the clock signal (1 MHz or less) to
the XI pin via resistor (about 5.1 k
).
Keep the XO pin open.
9
10
XI
XO
Integrating amplifier output (speed control pin).
11
INT
OUT
Integrating amplifier input pin
12
INT
IN
PLL output pin
13
Continued on next page.
No. 7110-8/11
LB11827
Continued from preceding page.
Pin No.
Pin
Function
Equivalent circuit
Speed discriminator output.
Accelerate: high, decelerate: low
14
DOUT
14
300
V
REG
16
V
REG
40 k
15
V
REG
Speed lock detection output.
L when the motor speed is within the speed lock range (6.25%).
Voltage resistance 30 Vmax
15
LD
300
FG Reset
300
17
18
V
REG
20 k
20 k
2 k
19
V
REG
22 k
FG amplifier input pin.
Connection of a capacitor (about 0.1 F) between FGIN and
GND causes initial reset to the logic circuit.
Start/stop control pin.
Low: 0 V to 1.5 V
High: 3.5 V to VREG
H level when open.
Hysteresis width about 0.5 V
17
FG
IN
18
FG
IN
+
19
S/S
FG amplifier output pin
16
FG
OUT
Continued on next page.
FG schmitt comparator
Pin No.
Pin
Function
Equivalent circuit
No. 7110-9/11
LB11827
Continued from preceding page.
GND pin (Other than the output)
20
GND1
2 k
27
V
REG
22 k
300
300
22
24
26
21
23
25
V
REG
Hall amplifier input.
IN+ > IN is the input high state, and the reverse is the input low
state.
It is recommended that the Hall signal has an amplitude of 100m
Vp-p (differential) or more.
Connect a capacitor between the IN+ and IN inputs if there is
noise in the Hall sensor signals.
22
21
24
23
26
25
IN1+
IN1
IN2+
IN2
IN3+
IN3
Forward/reverse control pin
Low: 0 V to 1.5 V
High: 3.5 V to VREG
H level when open
Hysteresis width about 0.5 V
27
F/R
Function Description
1. Speed control circuit
This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit
outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase
error signal once for each cycle of FG.
As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock
frequency.
f
FG
(servo) = f
CLK
/512
f
CLK
: Clock frequency
This IC achieves variable speed control with ease when combined with LB11825M.
2. Output drive circuit
This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated
at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the
output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between
OUT and V
CC
(because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a
short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output
current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or
schottky diode externally.
3. Current limiting circuit
The current limiting circuit performs limiting with the current determined from I = V
RF
/Rf (V
RF
= 0.5 Vtyp, Rf:
current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
No. 7110-10/11
LB11827
4. Power save circuit
This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias
current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given.
5. Reference clock
This is entered from the external signal source (1 MHz max) via a resistor (reference: about 5.1 k
) in series with the
XI pin. The XO pin is left open.
Input signal source levels:
Low-level voltage: 0 to 0.8 V
High-level voltage: 2.5 to 5.0 V
6. Speed lock range
The speed lock range is 6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes
to "L" (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive
output changes according to the speed error, causing control to keep the motor speed within the lock range.
7. PWM frequency
PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin.
f
PWM
1/(14,400
C)
It is recommended to keep the PWM frequency at 15 25 kHz. GND of a capacitor to be connected must be connected
to the GND1 pin with the shortest possible wiring.
8. Hall input signal
The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42 mV max). Considering
the effect of noise, the input with the amplitude of 100 mV or more is recommended.
When the output waveform is disturbed due to noise effects at a time of changeover of the output phase, connect a
capacitor between Hall input pins (+ and -) at a point as near as possible to the pin.
9. F/R changeover
Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay
attention to following points.
For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is
necessary to prevent exceeding of the rated voltage (30 V) due to rise of V
CC
voltage at a time of changeover
(because the motor current returns instantaneously to the power supply). When this problem exists, increase the
capacity of a capacitor between V
CC
and GND.
When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the
upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive
voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (3.5 A).
(F/R changeover speed is dangerous.)
10. Motor lock protection circuit
A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked.
When the LD output is "H" (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This
time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with
the capacity of 10 F (variance about 30%).
Set time (s)
0.33
C (F)
When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time,
etc.
Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock
protection circuit is not to be used, connect the CSD pin to GND.
When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be
discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is
PS No. 7110-11/11
LB11827
This catalog provides information as of December, 2003. Specifications and information herein are
subject to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to
restart in the motor start transient condition.)
Stop time (ms)
15
C (F)
11. Power supply stabilization
This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is
therefore necessary to connect a capacitor with a sufficient capacity (several ten F or more) between the VCC pin and
GND for stabilization. GND of a capacitor to be connected must be connected to the GND2 pin (GND of the power
block) at a point as near as possible to the pin. If a capacitor (electrolytic) cannot be provided near the pin because of
existence of a heat sink, etc., provide a ceramic capacitor of about 0.1 F near the pin.
When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power
line is particularly readily oscillated. The larger capacity need be selected.
12. VREG stabilization
The V
REG
pin (5 V regulator output) that is a power supply for control circuit must be provided with a stabilizing
capacitor (about 0.1 F). GND of a capacitor to be connected must be connected to the GND1 pin with the shortest
possible wiring.
13. Constant of integrating amplifier parts
Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange
them by keeping the largest possible distance from the motor.
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