Overview
The LC66354C, LC66356C, and LC66358C are 4-bit
CMOS microcontrollers that integrate on a single chip all
the functions required in a system controller, including
ROM, RAM, I/O ports, a serial interface, comparator
inputs, three-value inputs, timers, and interrupt functions.
These three microcontrollers are available in a 42-pin
package.
These products differ from the earlier LC66358A Series
and LC66358B Series in the power-supply voltage range,
the operating speed, and other points.
Features and Functions
On-chip ROM capacities of 4, 6, and 8 kilobytes, and an
on-chip RAM capacity of 512
4 bits.
Fully supports the LC66000 Series common instruction
set (128 instructions).
I/O ports: 36 pins
8-bit serial interface: two circuits (can be connected in
cascade to form a 16-bit interface)
Instruction cycle time: 0.92 to 10 s (at 2.5 to 5.5 V)
-- For the earlier LC66358A Series: 1.96 to 10 s (at
3.0 to 5.5 V) and 3.92 to 10 s (at 2.2 to 5.5 V)
-- For the earlier LC66358B Series: 0.92 to 10 s (at
3.0 to 5.5 V)
Powerful timer functions and prescalers
-- Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
-- Time limit timer, event counter, PWM output, and
square wave output using an 8-bit timer.
-- Time base function using a 12-bit prescaler.
Powerful interrupt system with 8 interrupt factors and 8
interrupt vector locations.
-- External interrupts: 3 factors/3 vector locations
-- Internal interrupts: 5 factors/5 vector locations
Flexible I/O functions
Comparator inputs, three-value inputs, 20-mA drive
outputs, 15-V high-voltage pins, and pull-up/open-drain
options.
Optional runaway detection function (watchdog timer)
8-bit I/O functions
Power saving functions using halt and hold modes.
Packages: DIP42S, QIP48E (QFP48E)
Evaluation LSIs
-- LC66599 (evaluation chip) + EVA85/800-TB6630X
-- LC66E308 (on-chip EPROM microcontroller)
used together.
Package Dimensions
unit: mm
3025B-DIP42S
22897HA (OT) No. 5484-1/21
Preliminary
LC66354C, 66356C, 66358C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Four-Bit Single-Chip Microcontrollers
with 4, 6, and 8 KB of On-Chip ROM
CMOS LSI
SANYO: DIP42S
unit: mm
3156-QFP48E
(STAND OFF)
1.5
17.2
17.2
1.5
1.5
1.5
1.6
1.6
14.0
0.35
15.6
0.8
1.0
1.0
3.0max
2.70
0.1
0.15
1
12
24
25
13
48
36
14.0
37
SANYO: QFP48E
[LC66354C/66356C/66358C]
1
37.9
0.95
0.48
1.78
1.15
15.24
13.8
0.25
3.8
4.25
0.51 min
5.1
max
22
21
42
[LC66354C/66356C/66358C]
No. 5484
Series Organization
Note:
*
Under development
No. 5484-2/21
LC66354C, 66356C, 66358C
Type No.
No. of
ROM capacity
RAM
Package
Features
pins
capacity
LC66304A/306A/308A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66404A/406A/408A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66506B/508B/512B/516B
64
6 K/8 K/12 K/16 KB
512 W
DIP64S
QFP64A
LC66354A/356A/358A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66354S/356S/358S
42
4 K/6 K/8 KB
512 W
QFP44M
LC66556A/558A/562A/566A
64
6 K/8 K/12 K/16 KB
512 W
DIP64S
QFP64E
LC66354B/356B/358B
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC66556B/558B
64
6 K/8 KB
512 W
DIP64S
QFP64E
LC66562B/566B
64
12 K/16 KB
512 W
DIP64S
QFP64E
LC66354C/356C/358C
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
2.5 to 5.5 V/0.92 s
LC662304A/2306A/2308A
42
4 K/6 K/8 KB
512 W
DIP42S
QFP48E
LC662312A/2316A
42
12 K/16 KB
512 W
DIP42S
QFP48E
LC665304A/665306A/665308A
48
4 K/6 K/8 KB
512 W
DIP48S
QFP48E
LC665312A/5316A
48
12 K/16 KB
512 W
DIP48S
QFP48E
LC66E308
42
EPROM 8 KB
512 W
DIC42S
QFC48
with window
with window
LC66P308
42
OTPROM 8 KB
512 W
DIP42S
QFP48E
LC66E408
42
EPROM 8 KB
512 W
DIC42S
QFC48
with window
with window
LC66P408
42
OTPROM 8 KB
512 W
DIP42S
QFP48E
LC66E516
64
EPROM 16 KB
512 W
DIC64S
QFC64
with window
with window
LC66P516
64
OTPROM 16 KB
512 W
DIP64S
QFP64E
LC66E2316
42
EPROM 16 KB
512 W
DIC42S
QFC48
with window
with window
4.5 to 5.5 V/0.95 s
LC66E5316
52/48
EPROM 16 KB
512 W
DIC52S
QFC48
with window
with window
LC66P2316
*
42
OTPROM 16 KB
512 W
DIP42S
QFP48E
4.0 to 5.5 V/0.95 s
LC66P5316
48
OTPROM 16 KB
512 W
DIP48S
QFP48E
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 s
Dual oscillator support
3.0 to 5.5 V/0.95 s
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 s
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 s
Low-voltage versions
2.2 to 5.5 V/3.92 s
Normal versions
4.0 to 6.0 V/0.92 s
Pin Assignments
We recommend the use of reflow-soldering techniques to solder-mount QFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly
immersed in a dip-soldering bath (dip-soldering techniques).
No. 5484-3/21
LC66354C, 66356C, 66358C
DIP42S
P00
P01
P02
P03
P10
P11
P12
P13
SI0/P20
SO0/P21
SCK0/P22
INT0/P23
INT1/P30
POUT0/P31
POUT1/P32
HOLD/P33
P40
P41
TEST
VSS
OSC1
PE1/TRB
PE0/TRA
VDD
PD3/CMP3
PD2/CMP2
PD1/CMP1
PD0/CMP0
PC3/VREF1
PC2/VREF0
P63/PIN1
P62/SCK1
P61/SO1
P60/SI1
P53/INT2
P52
P51
P50
P43
P42
RES
OSC2
LC66354C
356C
358C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
QFP48E
LC66354C
356C
358C
36
37
CMP2/PD2
PD1/CMP1
1
P11
35
PD0/CMP0
2
P12
34
PC3/VREF1
3
P13
33
PC2/VREF0
4
S10/P20
32
P63/PIN1
5
S00/P21
31
P62/SCK1
6
NC
30
NC
7
SCK0/P22
29
P61/S01
8
INT0/P23
28
P60/S11
9
INT1/P30
27
P53/INT2
10
POUT0/P31
26
P52
11
POUT1/P32
25
P51
12
HOLD/P33
24
P50
38
CMP3/PD3
23
P43
39
VDD
22
P42
40
TRA/PE0
21
RES
41
TRB/PE1
20
OSC2
42
NC
19
NC
43
NC
18
NC
44
P00
17
OSC1
45
P01
16
VSS
46
P02
15
TEST
47
P03
14
P41
48
P10
13
P40
Top view
System Block Diagram
Differences between the LC66354C, LC66356C, and LC66358C and the LC6630X Series
Note: 1. An RC oscillator cannot be used with the LC66354C, LC66356C, and LC66358C.
2. There are other differences, including differences in output currents and port input voltages.
For details, see the data sheets for the LC66308A, LC66E308, and LC66P308.
3. Pay close attention to the differences listed here when using the LC66E308 and LC66P308 for evaluation.
No. 5484-4/21
LC66354C, 66356C, 66358C
Item
LC6630X Series
LC6635XC Series
(Including the LC66599 evaluation chip)
System differences
65536 cycles
16384 cycles
Hardware wait time (number of cycles)
About 64 ms at 4 MHz (Tcyc = 1 s)
About 16 ms at 4 MHz (Tcyc = 1 s)
when hold mode is cleared
Value of timer 0 after a reset
(Including the value after hold mode is
Set to FF0.
Set to FFC.
cleared)
2.5 to 5.5 V/0.92 to 10 s
Difference in major features
LC66304A/306A/308A
LC6635XA
Operating power-supply voltage and
4.0 to 6.0 V/0.92 to 10 s
2.2 to 5.5 V/3.92 to 10 s
operating speed (cycle time)
LC66E308/P308
3.0 to 5.5 V/1.96 to 10 s
4.5 to 5.5 V/0.92 to 10 s
LC6635XB
3.0 to 5.5 V/0.92 to 10 s
SYSTEM
CONTROL
RAM STACK
(512W)
SP
E
A
ROM
(4K/6K/8K)
PC
POUT0
SI0
SO0
SCK0
INT0
INT1. INT2
PIN1. POUT1
FLAG
INTERRUPT
CONTROL
MPX
MPX
TIMER1
MPX
TIMER0
SERIAL I/O 0
PE
PD
PC
E
M
R
D
P
L
D
P
H
D
P
X
D
P
Y
P0
P1
P2
P3
P4
P5
P6
C
Z
ALU
RES
TRA
CMP0
CMP1
CMP2
CMP3
TRB
TEST
OSC1
OSC2
HOLD
SI1
SO1
SCK1
SERIAL I/O 1
PRESCALER
Pin Function Overview
No. 5484-5/21
LC66354C, 66356C, 66358C
Pin
I/O
Overview
Output driver type
Options
State after a reset
P00
P01
P02
P03
P10
P11
P12
P13
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
P30/INT1
P31/POUT0
P32/POUT1
P33/HOLD
P40
P41
P42
P43
P50
P51
P52
P53/INT2
I/O ports P00 to P03
Input or output in 4-bit or 1-bit units
P00 to P03 support the halt mode control
function
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
I/O ports P20 to P23
Input or output in 4-bit or 1-bit units
P20 is also used as the serial input SI0
pin.
P21 is also used as the serial output
SO0 pin.
P22 is also used as the serial clock
SCK0 pin.
P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
I/O ports P30 to P32
Input or output in 3-bit or 1-bit units
P30 is also used as the INT1 interrupt
request.
P31 is also used for the square wave
output from timer 0.
P32 is also used for the square wave
output from timer 1.
Hold mode control input
Hold mode is set up by the HOLD
instruction when HOLD is low.
In hold mode, the CPU is restarted by
setting HOLD to the high level.
This pin can be used as input port P33
along with P30 to P32.
When the P33/HOLD pin is at the low
level, the CPU will not be reset by a low
level on the RES pin. Therefore,
applications must not set P33/HOLD low
when power is first applied.
I/O ports P40 to P43
Input or output in 4-bit or 1-bit units
Input or output in 8-bit units when used
in conjunction with P50 to P53.
Can be used for output of 8-bit ROM
data when used in conjunction with P50
to P53.
I/O ports P50 to P53
Input or output in 4-bit or 1-bit units
Input or output in 8-bit units when used
in conjunction with P40 to P43.
Can be used for output of 8-bit ROM
data when used in conjunction with P40
to P43.
P53 is also used as the INT2 interrupt
request.
I/O
I/O
I/O
I/O
I
I/O
I/O
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Pch: CMOS type
Nch: Intermediate sink current
type
Nch: +15-V handling when OD
option selected
Pch: CMOS type
Nch: Intermediate sink current
type
Nch: +15-V handling when OD
option selected
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Nch: +15-V handling when OD
option selected
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Nch: +15-V handling when OD
option selected
Pull-up MOS or Nch
OD output
Output level on reset
Pull-up MOS or Nch
OD output
Output level on reset
CMOS or Nch OD
output
CMOS or Nch OD
output
Pull-up MOS or Nch OD
output
Pull-up MOS or Nch OD
output
High or low
(option)
High or low
(option)
H
H
H
H
Continued on next page.
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